+
+ /* Create map for register access */
+ gen3_mem_map[i].virt = 0xc0000000ULL;
+ gen3_mem_map[i].phys = 0xc0000000ULL;
+ gen3_mem_map[i].size = 0x40000000ULL;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ i++;
+
+ /* Generate entires for DRAM in 64bit address space */
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = gd->bd->bi_dram[bank].start;
+ size = gd->bd->bi_dram[bank].size;
+
+ /* Skip empty DRAM banks */
+ if (!size)
+ continue;
+
+ /* Skip DRAM below 4 GiB */
+ if (!(start >> 32ULL))
+ continue;
+
+ gen3_mem_map[i].virt = start;
+ gen3_mem_map[i].phys = start;
+ gen3_mem_map[i].size = size;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ i++;
+ }
+
+ /* Zero out the remaining regions. */
+ for (; i < GEN3_NR_REGIONS; i++) {
+ gen3_mem_map[i].virt = 0;
+ gen3_mem_map[i].phys = 0;
+ gen3_mem_map[i].size = 0;
+ gen3_mem_map[i].attrs = 0;
+ }
+
+ icache_enable();
+ dcache_enable();