+
+void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
+{
+ struct ti_sci_msg_fwl_region region;
+ struct ti_sci_fwl_ops *fwl_ops;
+ struct ti_sci_handle *ti_sci;
+ size_t i, j;
+
+ ti_sci = get_ti_sci_handle();
+ fwl_ops = &ti_sci->ops.fwl_ops;
+ for (i = 0; i < fwl_data_size; i++) {
+ for (j = 0; j < fwl_data[i].regions; j++) {
+ region.fwl_id = fwl_data[i].fwl_id;
+ region.region = j;
+ region.n_permission_regs = 3;
+
+ fwl_ops->get_fwl_region(ti_sci, ®ion);
+
+ if (region.control != 0) {
+ pr_debug("Attempting to disable firewall %5d (%25s)\n",
+ region.fwl_id, fwl_data[i].name);
+ region.control = 0;
+
+ if (fwl_ops->set_fwl_region(ti_sci, ®ion))
+ pr_err("Could not disable firewall %5d (%25s)\n",
+ region.fwl_id, fwl_data[i].name);
+ }
+ }
+ }
+}
+
+void spl_enable_dcache(void)
+{
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+ phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
+
+ dram_init_banksize();
+
+ /* reserve TLB table */
+ gd->arch.tlb_size = PGTABLE_SIZE;
+
+ ram_top += get_effective_memsize();
+ /* keep ram_top in the 32-bit address space */
+ if (ram_top >= 0x100000000)
+ ram_top = (phys_addr_t) 0x100000000;
+
+ gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
+ debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+
+ dcache_enable();
+#endif
+}
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+void spl_board_prepare_for_boot(void)
+{
+ dcache_disable();
+}
+
+void spl_board_prepare_for_boot_linux(void)
+{
+ dcache_disable();
+}
+#endif