+#endif
+
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
+/*
+ * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_SPEED_SHIFT 8
+enum cpu_speed {
+ OCOTP_TESTER3_SPEED_GRADE0,
+ OCOTP_TESTER3_SPEED_GRADE1,
+ OCOTP_TESTER3_SPEED_GRADE2,
+ OCOTP_TESTER3_SPEED_GRADE3,
+ OCOTP_TESTER3_SPEED_GRADE4,
+};
+
+u32 get_cpu_speed_grade_hz(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->tester3);
+ val >>= OCOTP_TESTER3_SPEED_SHIFT;
+
+ if (is_imx8mn() || is_imx8mp()) {
+ val &= 0xf;
+ return 2300000000 - val * 100000000;
+ }
+
+ if (is_imx8mm())
+ val &= 0x7;
+ else
+ val &= 0x3;
+
+ switch(val) {
+ case OCOTP_TESTER3_SPEED_GRADE0:
+ return 800000000;
+ case OCOTP_TESTER3_SPEED_GRADE1:
+ return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
+ case OCOTP_TESTER3_SPEED_GRADE2:
+ return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
+ case OCOTP_TESTER3_SPEED_GRADE3:
+ return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
+ case OCOTP_TESTER3_SPEED_GRADE4:
+ return 2000000000;
+ }
+
+ return 0;
+}
+
+/*
+ * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_TEMP_SHIFT 6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->tester3);
+ val >>= OCOTP_TESTER3_TEMP_SHIFT;
+ val &= 0x3;
+
+ if (minc && maxc) {
+ if (val == TEMP_AUTOMOTIVE) {
+ *minc = -40;
+ *maxc = 125;
+ } else if (val == TEMP_INDUSTRIAL) {
+ *minc = -40;
+ *maxc = 105;
+ } else if (val == TEMP_EXTCOMMERCIAL) {
+ *minc = -20;
+ *maxc = 105;
+ } else {
+ *minc = 0;
+ *maxc = 95;
+ }
+ }
+ return val;
+}
+#endif
+
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
+enum boot_device get_boot_device(void)
+{
+ struct bootrom_sw_info **p =
+ (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
+
+ enum boot_device boot_dev = SD1_BOOT;
+ u8 boot_type = (*p)->boot_dev_type;
+ u8 boot_instance = (*p)->boot_dev_instance;
+
+ switch (boot_type) {
+ case BOOT_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BOOT_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BOOT_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BOOT_TYPE_QSPI:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BOOT_TYPE_WEIM:
+ boot_dev = WEIM_NOR_BOOT;
+ break;
+ case BOOT_TYPE_SPINOR:
+ boot_dev = SPI_NOR_BOOT;
+ break;
+#ifdef CONFIG_IMX8M
+ case BOOT_TYPE_USB:
+ boot_dev = USB_BOOT;
+ break;
+#endif
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
+#endif
+
+#ifdef CONFIG_NXP_BOARD_REVISION
+int nxp_board_rev(void)
+{
+ /*
+ * Get Board ID information from OCOTP_GP1[15:8]
+ * RevA: 0x1
+ * RevB: 0x2
+ * RevC: 0x3
+ */
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
+ struct fuse_bank4_regs *fuse =
+ (struct fuse_bank4_regs *)bank->fuse_regs;
+
+ return (readl(&fuse->gp1) >> 8 & 0x0F);
+}
+
+char nxp_board_rev_string(void)
+{
+ const char *rev = "A";
+
+ return (*rev + nxp_board_rev() - 1);
+}
+#endif