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armv8: ls1046a: Enable workaround for erratum A-008336
[oweals/u-boot.git]
/
arch
/
arm
/
mach-exynos
/
dmc_init_ddr3.c
diff --git
a/arch/arm/mach-exynos/dmc_init_ddr3.c
b/arch/arm/mach-exynos/dmc_init_ddr3.c
index 7c0b12ae51addbffee5af54128ddd2f57a539adf..6a5d26cc69dbe7952c1a98416b9a4315a56c3451 100644
(file)
--- a/
arch/arm/mach-exynos/dmc_init_ddr3.c
+++ b/
arch/arm/mach-exynos/dmc_init_ddr3.c
@@
-20,8
+20,8
@@
#define TIMEOUT_US 10000
#define NUM_BYTE_LANES 4
#define DEFAULT_DQS 8
#define TIMEOUT_US 10000
#define NUM_BYTE_LANES 4
#define DEFAULT_DQS 8
-#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
- || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
+#define DEFAULT_DQS_X4 (
(
DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+ || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
)
#ifdef CONFIG_EXYNOS5250
static void reset_phy_ctrl(void)
#ifdef CONFIG_EXYNOS5250
static void reset_phy_ctrl(void)
@@
-618,7
+618,7
@@
int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
/*
* Send NOP, MRS and ZQINIT commands
* Sending MRS command will reset the DRAM. We should not be
/*
* Send NOP, MRS and ZQINIT commands
* Sending MRS command will reset the DRAM. We should not be
- * reseting the DRAM after resume, this will lead to memory
+ * reset
t
ing the DRAM after resume, this will lead to memory
* corruption as DRAM content is lost after DRAM reset
*/
dmc_config_mrs(mem, &drex0->directcmd);
* corruption as DRAM content is lost after DRAM reset
*/
dmc_config_mrs(mem, &drex0->directcmd);
@@
-856,10
+856,10
@@
int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
*/
val = readl(&drex0->concontrol);
val |= CONCONTROL_UPDATE_MODE;
*/
val = readl(&drex0->concontrol);
val |= CONCONTROL_UPDATE_MODE;
- writel(val
, &drex0->concontrol);
+ writel(val, &drex0->concontrol);
val = readl(&drex1->concontrol);
val |= CONCONTROL_UPDATE_MODE;
val = readl(&drex1->concontrol);
val |= CONCONTROL_UPDATE_MODE;
- writel(val
, &drex1->concontrol);
+ writel(val, &drex1->concontrol);
return 0;
}
return 0;
}