+/* Bit field in I/O Calibration Register */
+#define ATMEL_MPDDRC_IO_CALIBR_RDIV 0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_34_3 0x1
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_40 0x2
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48 0x3
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_60 0x4
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_80 0x6
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_120 0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_35 0x2
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_43 0x3
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 0x4
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_70 0x6
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_105 0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_TZQIO (0x7f << 8)
+#define ATMEL_MPDDRC_IO_CALIBR_TZQIO_(x) (((x) & 0x7f) << 8)
+
+#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP (0xf << 16)
+#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP_(x) (((x) & 0xf) << 16)
+#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN (0xf << 20)
+#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN_(x) (((x) & 0xf) << 20)
+
+#define ATMEL_MPDDRC_IO_CALIBR_EN_CALIB (0x1 << 4)
+
+/* Bit field in Read Data Path Register */
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING 0x3
+#define ATMEL_MPDDRC_RD_DATA_PATH_NO_SHIFT 0x0
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE 0x1
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE 0x2
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE 0x3
+