projects
/
oweals
/
u-boot.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
armv8: ls1088aqds: Add IFC-NOR as boot source for LS1088
[oweals/u-boot.git]
/
arch
/
arm
/
lib
/
cache-cp15.c
diff --git
a/arch/arm/lib/cache-cp15.c
b/arch/arm/lib/cache-cp15.c
index 3aabda156b319779bfee87d2da6e0c17ec38b960..f0c1b03728be3bca6ff16e0ded0abb4eeb19abae 100644
(file)
--- a/
arch/arm/lib/cache-cp15.c
+++ b/
arch/arm/lib/cache-cp15.c
@@
-22,16
+22,6
@@
__weak void arm_init_domains(void)
{
}
{
}
-static void cp_delay (void)
-{
- volatile int i;
-
- /* copro seems to need some delay between reading and writing */
- for (i = 0; i < 100; i++)
- nop();
- asm volatile("" : : : "memory");
-}
-
void set_section_dcache(int section, enum dcache_option option)
{
#ifdef CONFIG_ARMV7_LPAE
void set_section_dcache(int section, enum dcache_option option)
{
#ifdef CONFIG_ARMV7_LPAE
@@
-66,15
+56,32
@@
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
#else
u32 *page_table = (u32 *)gd->arch.tlb_addr;
#endif
#else
u32 *page_table = (u32 *)gd->arch.tlb_addr;
#endif
+ unsigned long startpt, stoppt;
unsigned long upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
start = start >> MMU_SECTION_SHIFT;
unsigned long upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
start = start >> MMU_SECTION_SHIFT;
- debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
+#ifdef CONFIG_ARMV7_LPAE
+ debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
+ option);
+#else
+ debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
option);
option);
+#endif
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);
- mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+
+ /*
+ * Make sure range is cache line aligned
+ * Only CPU maintains page tables, hence it is safe to always
+ * flush complete cache lines...
+ */
+
+ startpt = (unsigned long)&page_table[start];
+ startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ stoppt = (unsigned long)&page_table[end];
+ stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
+ mmu_page_table_flush(startpt, stoppt);
}
__weak void dram_bank_mmu_setup(int bank)
}
__weak void dram_bank_mmu_setup(int bank)
@@
-112,7
+119,7
@@
static inline void mmu_setup(void)
dram_bank_mmu_setup(i);
}
dram_bank_mmu_setup(i);
}
-#if
def CONFIG_ARMV7_LPAE
+#if
defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
/* Set up 4 PTE entries pointing to our 4 1GB page tables */
for (i = 0; i < 4; i++) {
u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
/* Set up 4 PTE entries pointing to our 4 1GB page tables */
for (i = 0; i < 4; i++) {
u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
@@
-130,7
+137,7
@@
static inline void mmu_setup(void)
#endif
if (is_hyp()) {
#endif
if (is_hyp()) {
- /* Set H
CT
R to enable LPAE */
+ /* Set H
TC
R to enable LPAE */
asm volatile("mcr p15, 4, %0, c2, c0, 2"
: : "r" (reg) : "memory");
/* Set HTTBR0 */
asm volatile("mcr p15, 4, %0, c2, c0, 2"
: : "r" (reg) : "memory");
/* Set HTTBR0 */
@@
-155,6
+162,15
@@
static inline void mmu_setup(void)
: : "r" (MEMORY_ATTRIBUTES) : "memory");
}
#elif defined(CONFIG_CPU_V7)
: : "r" (MEMORY_ATTRIBUTES) : "memory");
}
#elif defined(CONFIG_CPU_V7)
+ if (is_hyp()) {
+ /* Set HTCR to disable LPAE */
+ asm volatile("mcr p15, 4, %0, c2, c0, 2"
+ : : "r" (0) : "memory");
+ } else {
+ /* Set TTBCR to disable LPAE */
+ asm volatile("mcr p15, 0, %0, c2, c0, 2"
+ : : "r" (0) : "memory");
+ }
/* Set TTBR0 */
reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
/* Set TTBR0 */
reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
@@
-179,7
+195,6
@@
static inline void mmu_setup(void)
/* and enable the mmu */
reg = get_cr(); /* get control reg. */
/* and enable the mmu */
reg = get_cr(); /* get control reg. */
- cp_delay();
set_cr(reg | CR_M);
}
set_cr(reg | CR_M);
}
@@
-197,7
+212,6
@@
static void cache_enable(uint32_t cache_bit)
if ((cache_bit == CR_C) && !mmu_enabled())
mmu_setup();
reg = get_cr(); /* get control reg. */
if ((cache_bit == CR_C) && !mmu_enabled())
mmu_setup();
reg = get_cr(); /* get control reg. */
- cp_delay();
set_cr(reg | cache_bit);
}
set_cr(reg | cache_bit);
}
@@
-207,7
+221,6
@@
static void cache_disable(uint32_t cache_bit)
uint32_t reg;
reg = get_cr();
uint32_t reg;
reg = get_cr();
- cp_delay();
if (cache_bit == CR_C) {
/* if cache isn;t enabled no need to disable */
if (cache_bit == CR_C) {
/* if cache isn;t enabled no need to disable */
@@
-217,7
+230,7
@@
static void cache_disable(uint32_t cache_bit)
cache_bit |= CR_M;
}
reg = get_cr();
cache_bit |= CR_M;
}
reg = get_cr();
- cp_delay();
+
if (cache_bit == (CR_C | CR_M))
flush_dcache_all();
set_cr(reg & ~cache_bit);
if (cache_bit == (CR_C | CR_M))
flush_dcache_all();
set_cr(reg & ~cache_bit);