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Revert "stm32: Change USART port to USART6 for stm32f746 discovery board"
[oweals/u-boot.git]
/
arch
/
arm
/
include
/
asm
/
omap_common.h
diff --git
a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 8fd728a1e8c48389e0d49d1f44b291ee92d4a06e..605c549f0a5a647b84874d7cd4ed108762c63cc5 100644
(file)
--- a/
arch/arm/include/asm/omap_common.h
+++ b/
arch/arm/include/asm/omap_common.h
@@
-145,6
+145,7
@@
struct prcm_regs {
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl;
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl;
+ u32 cm_coreaon_usb_phy3_core_clkctrl;
u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
/* cm2.core */
u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
/* cm2.core */
@@
-234,6
+235,7
@@
struct prcm_regs {
u32 cm_l3init_usb_otg_ss1_clkctrl;
u32 cm_l3init_usb_otg_ss2_clkctrl;
u32 cm_l3init_usb_otg_ss1_clkctrl;
u32 cm_l3init_usb_otg_ss2_clkctrl;
+ u32 prm_irqstatus_mpu;
u32 prm_irqstatus_mpu_2;
/* cm2.l4per */
u32 prm_irqstatus_mpu_2;
/* cm2.l4per */
@@
-321,6
+323,14
@@
struct prcm_regs {
u32 prm_vc_cfg_i2c_clk;
u32 prm_abbldo_mpu_setup;
u32 prm_abbldo_mpu_ctrl;
u32 prm_vc_cfg_i2c_clk;
u32 prm_abbldo_mpu_setup;
u32 prm_abbldo_mpu_ctrl;
+ u32 prm_abbldo_mm_setup;
+ u32 prm_abbldo_mm_ctrl;
+ u32 prm_abbldo_iva_setup;
+ u32 prm_abbldo_iva_ctrl;
+ u32 prm_abbldo_eve_setup;
+ u32 prm_abbldo_eve_ctrl;
+ u32 prm_abbldo_gpu_setup;
+ u32 prm_abbldo_gpu_ctrl;
u32 cm_div_m4_dpll_core;
u32 cm_div_m5_dpll_core;
u32 cm_div_m4_dpll_core;
u32 cm_div_m5_dpll_core;
@@
-363,7
+373,6
@@
struct omap_sys_ctrl_regs {
u32 control_core_mac_id_0_hi;
u32 control_core_mac_id_1_lo;
u32 control_core_mac_id_1_hi;
u32 control_core_mac_id_0_hi;
u32 control_core_mac_id_1_lo;
u32 control_core_mac_id_1_hi;
- u32 control_std_fuse_opp_vdd_mpu_2;
u32 control_phy_power_usb;
u32 control_core_mmr_lock1;
u32 control_core_mmr_lock2;
u32 control_phy_power_usb;
u32 control_core_mmr_lock1;
u32 control_core_mmr_lock2;
@@
-442,6
+451,10
@@
struct omap_sys_ctrl_regs {
u32 control_emif1_sdram_config_ext;
u32 control_emif2_sdram_config_ext;
u32 control_wkup_ldovbb_mpu_voltage_ctrl;
u32 control_emif1_sdram_config_ext;
u32 control_emif2_sdram_config_ext;
u32 control_wkup_ldovbb_mpu_voltage_ctrl;
+ u32 control_wkup_ldovbb_mm_voltage_ctrl;
+ u32 control_wkup_ldovbb_iva_voltage_ctrl;
+ u32 control_wkup_ldovbb_eve_voltage_ctrl;
+ u32 control_wkup_ldovbb_gpu_voltage_ctrl;
u32 control_smart1nopmio_padconf_0;
u32 control_smart1nopmio_padconf_1;
u32 control_padconf_mode;
u32 control_smart1nopmio_padconf_0;
u32 control_smart1nopmio_padconf_1;
u32 control_padconf_mode;
@@
-541,6
+554,8
@@
struct volts {
u32 addr;
struct volts_efuse_data efuse;
struct pmic_data *pmic;
u32 addr;
struct volts_efuse_data efuse;
struct pmic_data *pmic;
+
+ u32 abb_tx_done_mask;
};
struct vcores_data {
};
struct vcores_data {
@@
-604,6
+619,7
@@
void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
void omap_die_id_serial(void);
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
void omap_die_id_serial(void);
+void omap_die_id_get_board_serial(struct tag_serialnr *serialnr);
void omap_die_id_usbethaddr(void);
void omap_die_id_display(void);
void omap_die_id_usbethaddr(void);
void omap_die_id_display(void);
@@
-611,11
+627,20
@@
void recalibrate_iodelay(void);
void omap_smc1(u32 service, u32 val);
void omap_smc1(u32 service, u32 val);
+/*
+ * Low-level helper function used when performing secure ROM calls on high-
+ * security (HS) device variants by doing a specially-formed smc entry.
+ */
+u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
+
void enable_edma3_clocks(void);
void disable_edma3_clocks(void);
void omap_die_id(unsigned int *die_id);
void enable_edma3_clocks(void);
void disable_edma3_clocks(void);
void omap_die_id(unsigned int *die_id);
+/* Initialize general purpose I2C(0) on the SoC */
+void gpi2c_init(void);
+
/* ABB */
#define OMAP_ABB_NOMINAL_OPP 0
#define OMAP_ABB_FAST_OPP 1
/* ABB */
#define OMAP_ABB_NOMINAL_OPP 0
#define OMAP_ABB_FAST_OPP 1
@@
-696,6
+721,18
@@
static inline u8 is_dra72x(void)
#define DRA752_ES1_1 0x07520110
#define DRA752_ES2_0 0x07520200
#define DRA722_ES1_0 0x07220100
#define DRA752_ES1_1 0x07520110
#define DRA752_ES2_0 0x07520200
#define DRA722_ES1_0 0x07220100
+#define DRA722_ES2_0 0x07220200
+
+/*
+ * silicon device type
+ * Moving to common from cpu.h, since it is shared by various omap devices
+ */
+#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
+#define TST_DEVICE 0x0
+#define EMU_DEVICE 0x1
+#define HS_DEVICE 0x2
+#define GP_DEVICE 0x3
+
/*
* SRAM scratch space entries
/*
* SRAM scratch space entries
@@
-709,7
+746,9
@@
static inline u8 is_dra72x(void)
#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
-#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#define OMAP_SRAM_SCRATCH_SPACE_END (OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
/* Boot parameters */
#define DEVICE_DATA_OFFSET 0x18
/* Boot parameters */
#define DEVICE_DATA_OFFSET 0x18