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aspeed: Add P-Bus clock in ast2500 clock driver
[oweals/u-boot.git]
/
arch
/
arm
/
include
/
asm
/
macro.h
diff --git
a/arch/arm/include/asm/macro.h
b/arch/arm/include/asm/macro.h
index 2553e3e349c5da1a4572fe735e0cbb5ec4ea5f04..e1916f7705d1c4a8ef830520b084356b83bd08ec 100644
(file)
--- a/
arch/arm/include/asm/macro.h
+++ b/
arch/arm/include/asm/macro.h
@@
-182,11
+182,17
@@
lr .req x30
/*
* The next lower exception level is AArch64, 64bit EL2 | HCE |
/*
* The next lower exception level is AArch64, 64bit EL2 | HCE |
- * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+ * RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+ * and the SMD depends on requirements.
*/
*/
+#ifdef CONFIG_ARMV8_PSCI
+ ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
+ SCR_EL3_RES1 | SCR_EL3_NS_EN)
+#else
ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
SCR_EL3_NS_EN)
ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
SCR_EL3_NS_EN)
+#endif
msr scr_el3, \tmp
/* Return to the EL2_SP2 mode from EL3 */
msr scr_el3, \tmp
/* Return to the EL2_SP2 mode from EL3 */