+ u32 emif_ddr_ext_phy_ctrl_25;
+ u32 emif_ddr_ext_phy_ctrl_25_shdw;
+ u32 emif_ddr_ext_phy_ctrl_26;
+ u32 emif_ddr_ext_phy_ctrl_26_shdw;
+ u32 emif_ddr_ext_phy_ctrl_27;
+ u32 emif_ddr_ext_phy_ctrl_27_shdw;
+ u32 emif_ddr_ext_phy_ctrl_28;
+ u32 emif_ddr_ext_phy_ctrl_28_shdw;
+ u32 emif_ddr_ext_phy_ctrl_29;
+ u32 emif_ddr_ext_phy_ctrl_29_shdw;
+ u32 emif_ddr_ext_phy_ctrl_30;
+ u32 emif_ddr_ext_phy_ctrl_30_shdw;
+ u32 emif_ddr_ext_phy_ctrl_31;
+ u32 emif_ddr_ext_phy_ctrl_31_shdw;
+ u32 emif_ddr_ext_phy_ctrl_32;
+ u32 emif_ddr_ext_phy_ctrl_32_shdw;
+ u32 emif_ddr_ext_phy_ctrl_33;
+ u32 emif_ddr_ext_phy_ctrl_33_shdw;
+ u32 emif_ddr_ext_phy_ctrl_34;
+ u32 emif_ddr_ext_phy_ctrl_34_shdw;
+ u32 emif_ddr_ext_phy_ctrl_35;
+ u32 emif_ddr_ext_phy_ctrl_35_shdw;
+ union {
+ u32 emif_ddr_ext_phy_ctrl_36;
+ u32 emif_ddr_fifo_misaligned_clear_1;
+ };
+ union {
+ u32 emif_ddr_ext_phy_ctrl_36_shdw;
+ u32 emif_ddr_fifo_misaligned_clear_2;
+ };