+ u32 padding7[4];
+ u32 emif_prio_class_serv_map;
+ u32 emif_connect_id_serv_1_map;
+ u32 emif_connect_id_serv_2_map;
+ u32 padding8[5];
+ u32 emif_rd_wr_exec_thresh;
+ u32 emif_cos_config;
+ u32 padding9[6];
+ u32 emif_ddr_phy_status[28];
+ u32 padding10[20];
+ u32 emif_ddr_ext_phy_ctrl_1;
+ u32 emif_ddr_ext_phy_ctrl_1_shdw;
+ u32 emif_ddr_ext_phy_ctrl_2;
+ u32 emif_ddr_ext_phy_ctrl_2_shdw;
+ u32 emif_ddr_ext_phy_ctrl_3;
+ u32 emif_ddr_ext_phy_ctrl_3_shdw;
+ u32 emif_ddr_ext_phy_ctrl_4;
+ u32 emif_ddr_ext_phy_ctrl_4_shdw;
+ u32 emif_ddr_ext_phy_ctrl_5;
+ u32 emif_ddr_ext_phy_ctrl_5_shdw;
+ u32 emif_ddr_ext_phy_ctrl_6;
+ u32 emif_ddr_ext_phy_ctrl_6_shdw;
+ u32 emif_ddr_ext_phy_ctrl_7;
+ u32 emif_ddr_ext_phy_ctrl_7_shdw;
+ u32 emif_ddr_ext_phy_ctrl_8;
+ u32 emif_ddr_ext_phy_ctrl_8_shdw;
+ u32 emif_ddr_ext_phy_ctrl_9;
+ u32 emif_ddr_ext_phy_ctrl_9_shdw;
+ u32 emif_ddr_ext_phy_ctrl_10;
+ u32 emif_ddr_ext_phy_ctrl_10_shdw;
+ u32 emif_ddr_ext_phy_ctrl_11;
+ u32 emif_ddr_ext_phy_ctrl_11_shdw;
+ u32 emif_ddr_ext_phy_ctrl_12;
+ u32 emif_ddr_ext_phy_ctrl_12_shdw;
+ u32 emif_ddr_ext_phy_ctrl_13;
+ u32 emif_ddr_ext_phy_ctrl_13_shdw;
+ u32 emif_ddr_ext_phy_ctrl_14;
+ u32 emif_ddr_ext_phy_ctrl_14_shdw;
+ u32 emif_ddr_ext_phy_ctrl_15;
+ u32 emif_ddr_ext_phy_ctrl_15_shdw;
+ u32 emif_ddr_ext_phy_ctrl_16;
+ u32 emif_ddr_ext_phy_ctrl_16_shdw;
+ u32 emif_ddr_ext_phy_ctrl_17;
+ u32 emif_ddr_ext_phy_ctrl_17_shdw;
+ u32 emif_ddr_ext_phy_ctrl_18;
+ u32 emif_ddr_ext_phy_ctrl_18_shdw;
+ u32 emif_ddr_ext_phy_ctrl_19;
+ u32 emif_ddr_ext_phy_ctrl_19_shdw;
+ u32 emif_ddr_ext_phy_ctrl_20;
+ u32 emif_ddr_ext_phy_ctrl_20_shdw;
+ u32 emif_ddr_ext_phy_ctrl_21;
+ u32 emif_ddr_ext_phy_ctrl_21_shdw;
+ u32 emif_ddr_ext_phy_ctrl_22;
+ u32 emif_ddr_ext_phy_ctrl_22_shdw;
+ u32 emif_ddr_ext_phy_ctrl_23;
+ u32 emif_ddr_ext_phy_ctrl_23_shdw;
+ u32 emif_ddr_ext_phy_ctrl_24;
+ u32 emif_ddr_ext_phy_ctrl_24_shdw;
+ u32 emif_ddr_ext_phy_ctrl_25;
+ u32 emif_ddr_ext_phy_ctrl_25_shdw;
+ u32 emif_ddr_ext_phy_ctrl_26;
+ u32 emif_ddr_ext_phy_ctrl_26_shdw;
+ u32 emif_ddr_ext_phy_ctrl_27;
+ u32 emif_ddr_ext_phy_ctrl_27_shdw;
+ u32 emif_ddr_ext_phy_ctrl_28;
+ u32 emif_ddr_ext_phy_ctrl_28_shdw;
+ u32 emif_ddr_ext_phy_ctrl_29;
+ u32 emif_ddr_ext_phy_ctrl_29_shdw;
+ u32 emif_ddr_ext_phy_ctrl_30;
+ u32 emif_ddr_ext_phy_ctrl_30_shdw;
+ u32 emif_ddr_ext_phy_ctrl_31;
+ u32 emif_ddr_ext_phy_ctrl_31_shdw;
+ u32 emif_ddr_ext_phy_ctrl_32;
+ u32 emif_ddr_ext_phy_ctrl_32_shdw;
+ u32 emif_ddr_ext_phy_ctrl_33;
+ u32 emif_ddr_ext_phy_ctrl_33_shdw;
+ u32 emif_ddr_ext_phy_ctrl_34;
+ u32 emif_ddr_ext_phy_ctrl_34_shdw;
+ u32 emif_ddr_ext_phy_ctrl_35;
+ u32 emif_ddr_ext_phy_ctrl_35_shdw;
+ union {
+ u32 emif_ddr_ext_phy_ctrl_36;
+ u32 emif_ddr_fifo_misaligned_clear_1;
+ };
+ union {
+ u32 emif_ddr_ext_phy_ctrl_36_shdw;
+ u32 emif_ddr_fifo_misaligned_clear_2;
+ };