projects
/
oweals
/
u-boot.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
arm: Move check_cache_range() into a common place
[oweals/u-boot.git]
/
arch
/
arm
/
include
/
asm
/
cache.h
diff --git
a/arch/arm/include/asm/cache.h
b/arch/arm/include/asm/cache.h
index 6d60a4a6d955d276d12a492bdcf59342882a7dc0..16e65c36a9a5dacefadd4281b30a8a4d4bc77c41 100644
(file)
--- a/
arch/arm/include/asm/cache.h
+++ b/
arch/arm/include/asm/cache.h
@@
-11,9
+11,14
@@
#include <asm/system.h>
#include <asm/system.h>
+#ifndef CONFIG_ARM64
+
/*
* Invalidate L2 Cache using co-proc instruction
*/
/*
* Invalidate L2 Cache using co-proc instruction
*/
+#ifdef CONFIG_SYS_THUMB_BUILD
+void invalidate_l2_cache(void);
+#else
static inline void invalidate_l2_cache(void)
{
unsigned int val=0;
static inline void invalidate_l2_cache(void)
{
unsigned int val=0;
@@
-22,12
+27,21
@@
static inline void invalidate_l2_cache(void)
: : "r" (val) : "cc");
isb();
}
: : "r" (val) : "cc");
isb();
}
+#endif
+
+int check_cache_range(unsigned long start, unsigned long stop);
void l2_cache_enable(void);
void l2_cache_disable(void);
void set_section_dcache(int section, enum dcache_option option);
void l2_cache_enable(void);
void l2_cache_disable(void);
void set_section_dcache(int section, enum dcache_option option);
+void arm_init_before_mmu(void);
+void arm_init_domains(void);
+void cpu_cache_initialization(void);
void dram_bank_mmu_setup(int bank);
void dram_bank_mmu_setup(int bank);
+
+#endif
+
/*
* The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
* use that value for aligning DMA buffers unless the board config has specified
/*
* The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
* use that value for aligning DMA buffers unless the board config has specified