+ uint32_t scr; /* offset 0x10: System Control Register */
+ uint32_t ccr; /* offset 0x14: Config and Control Register */
+ uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */
+ uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */
+ uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */
+ uint32_t shcrs; /* offset 0x24: System Handler Control State */
+ uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */
+ uint32_t hfsr; /* offset 0x2C: HardFault Status Register */
+ uint32_t res; /* offset 0x30: reserved */
+ uint32_t mmar; /* offset 0x34: MemManage Fault Address Reg */
+ uint32_t bfar; /* offset 0x38: BusFault Address Reg */
+ uint32_t afsr; /* offset 0x3C: Auxiliary Fault Status Reg */