+#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000)
+#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000)
+#define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000)
+#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000)
+#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000)
+