+/* CCM bits common to all Display Engine 2.0 clock ctrl regs */
+#define CCM_DE2_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_DE2_CTRL_PLL_MASK (3 << 24)
+#define CCM_DE2_CTRL_PLL6_2X (0 << 24)
+#define CCM_DE2_CTRL_PLL10 (1 << 24)
+#define CCM_DE2_CTRL_GATE (0x1 << 31)
+
+/* CCU security switch, H3 only */
+#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2)
+#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1)
+#define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0)
+