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rockchip: clk: rv1108: remove duplicate reset init
[oweals/u-boot.git]
/
arch
/
arm
/
include
/
asm
/
arch-rockchip
/
cru_rk3399.h
diff --git
a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
index 98fba2bd7556a16f2d686d46f290902dfcf2be82..15eeb9c44073fd80f263ee8580ae4a93c6c0529b 100644
(file)
--- a/
arch/arm/include/asm/arch-rockchip/cru_rk3399.h
+++ b/
arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@
-1,7
+1,6
@@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_CRU_RK3399_H_
*/
#ifndef __ASM_ARCH_CRU_RK3399_H_
@@
-12,7
+11,10
@@
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3399_clk_priv {
struct rk3399_cru *cru;
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3399_clk_priv {
struct rk3399_cru *cru;
- ulong rate;
+};
+
+struct rk3399_pmuclk_priv {
+ struct rk3399_pmucru *pmucru;
};
struct rk3399_pmucru {
};
struct rk3399_pmucru {
@@
-67,16
+69,21
@@
check_member(rk3399_cru, sdio1_con[1], 0x594);
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24*MHz)
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24*MHz)
-#define APLL_HZ (600*MHz)
+#define LPLL_HZ (600*MHz)
+#define BPLL_HZ (600*MHz)
#define GPLL_HZ (594*MHz)
#define CPLL_HZ (384*MHz)
#define PPLL_HZ (676*MHz)
#define PMU_PCLK_HZ (48*MHz)
#define GPLL_HZ (594*MHz)
#define CPLL_HZ (384*MHz)
#define PPLL_HZ (676*MHz)
#define PMU_PCLK_HZ (48*MHz)
-#define ACLKM_CORE_HZ (300*MHz)
-#define ATCLK_CORE_HZ (300*MHz)
-#define PCLK_DBG_HZ (100*MHz)
+#define ACLKM_CORE_L_HZ (300*MHz)
+#define ATCLK_CORE_L_HZ (300*MHz)
+#define PCLK_DBG_L_HZ (100*MHz)
+
+#define ACLKM_CORE_B_HZ (300*MHz)
+#define ATCLK_CORE_B_HZ (300*MHz)
+#define PCLK_DBG_B_HZ (100*MHz)
#define PERIHP_ACLK_HZ (148500*KHz)
#define PERIHP_HCLK_HZ (148500*KHz)
#define PERIHP_ACLK_HZ (148500*KHz)
#define PERIHP_HCLK_HZ (148500*KHz)
@@
-96,4
+103,13
@@
enum apll_l_frequencies {
APLL_L_600_MHZ,
};
APLL_L_600_MHZ,
};
+enum apll_b_frequencies {
+ APLL_B_600_MHZ,
+};
+
+void rk3399_configure_cpu_l(struct rk3399_cru *cru,
+ enum apll_l_frequencies apll_l_freq);
+void rk3399_configure_cpu_b(struct rk3399_cru *cru,
+ enum apll_b_frequencies apll_b_freq);
+
#endif /* __ASM_ARCH_CRU_RK3399_H_ */
#endif /* __ASM_ARCH_CRU_RK3399_H_ */