+ CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
+
+extern struct fman_icid_id_table fman_icid_tbl[];
+extern int fman_icid_tbl_sz;
+
+#else /* CONFIG_FSL_LSCH2 */
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define GUR_IS_LE true
+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
+#define GUR_IS_LE false
+#endif
+
+#define QDMA_IS_LE true
+
+#define SET_GUR_ICID(compat, streamid, name, compataddr) \
+ SET_ICID_ENTRY(compat, streamid, streamid, \
+ offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
+ compataddr, GUR_IS_LE)
+
+#define SET_USB_ICID(usb_num, compat, streamid) \
+ SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
+ CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+
+#define SET_SATA_ICID(sata_num, compat, streamid) \
+ SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
+ AHCI_BASE_ADDR##sata_num)
+
+#define SET_SDHC_ICID(sdhc_num, streamid) \
+ SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\
+ FSL_ESDHC##sdhc_num##_BASE_ADDR)
+
+#define SET_EDMA_ICID(streamid) \
+ SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\
+ EDMA_BASE_ADDR)
+
+#define SET_GPU_ICID(compat, streamid) \
+ SET_GUR_ICID(compat, streamid, misc1_amqr,\
+ GPU_BASE_ADDR)
+
+#define SET_DISPLAY_ICID(streamid) \
+ SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\
+ DISPLAY_BASE_ADDR)
+
+#define SEC_ICID_REG_VAL(streamid) (streamid)
+
+#endif /* CONFIG_FSL_LSCH2 */
+
+#define SET_QDMA_ICID(compat, streamid) \
+ SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
+ QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
+ QDMA_BASE_ADDR, QDMA_IS_LE), \
+ SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
+ QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
+ QDMA_BASE_ADDR, QDMA_IS_LE)