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ARM: tegra: add PCIe controller to Tegra186 SoC DT
[oweals/u-boot.git]
/
arch
/
arm
/
dts
/
zynq-zc770-xm012.dts
diff --git
a/arch/arm/dts/zynq-zc770-xm012.dts
b/arch/arm/dts/zynq-zc770-xm012.dts
index 127a6619c6314d6b9c4ef3cac97e69713bd1a8be..6cab8326677009a48c1f674f0ded01b7decfa763 100644
(file)
--- a/
arch/arm/dts/zynq-zc770-xm012.dts
+++ b/
arch/arm/dts/zynq-zc770-xm012.dts
@@
-1,7
+1,7
@@
/*
* Xilinx ZC770 XM012 board DTS
*
/*
* Xilinx ZC770 XM012 board DTS
*
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2013
- 2015
Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@
-9,15
+9,58
@@
#include "zynq-7000.dtsi"
/ {
#include "zynq-7000.dtsi"
/ {
- model = "Zynq ZC770 XM012 Board";
compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
aliases {
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
serial0 = &uart1;
serial0 = &uart1;
+ spi0 = &spi1;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
};
memory {
device_type = "memory";
- reg = <0 0x40000000>;
+ reg = <0x0 0x40000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ m24c02_eeprom@52 {
+ compatible = "at,24c02";
+ reg = <0x52>;
};
};
};
};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ m24c02_eeprom@52 {
+ compatible = "at,24c02";
+ reg = <0x52>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};