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armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry
[oweals/u-boot.git]
/
arch
/
arm
/
cpu
/
armv8
/
fsl-layerscape
/
cpu.c
diff --git
a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 978d46b32fcb18cbbad8459df6c603417bed1d54..db7577b6ed35414e0c6d1330bd887c64ccd55b8f 100644
(file)
--- a/
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@
-251,7
+251,7
@@
static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
-#if
defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+#if
def CONFIG_SYS_PCIE4_PHYS_ADDR
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
@@
-388,7
+388,7
@@
void cpu_name(char *name)
strcpy(name, "unknown");
}
strcpy(name, "unknown");
}
-#if
ndef CONFIG_SYS_DCACHE_OFF
+#if
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
@@
-453,11
+453,13
@@
static void fix_pcie_mmu_map(void)
final_map[i].virt = 0x3000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
final_map[i].virt = 0x3000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
case CONFIG_SYS_PCIE4_PHYS_ADDR:
final_map[i].phys = 0x3800000000ULL;
final_map[i].virt = 0x3800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
case CONFIG_SYS_PCIE4_PHYS_ADDR:
final_map[i].phys = 0x3800000000ULL;
final_map[i].virt = 0x3800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
+#endif
default:
break;
}
default:
break;
}
@@
-611,7
+613,7
@@
void enable_caches(void)
icache_enable();
dcache_enable();
}
icache_enable();
dcache_enable();
}
-#endif /*
CONFIG_SYS_DCACHE_OFF
*/
+#endif /*
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
*/
#ifdef CONFIG_TFABOOT
enum boot_src __get_boot_src(u32 porsr1)
#ifdef CONFIG_TFABOOT
enum boot_src __get_boot_src(u32 porsr1)