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armv8: fsl-layerscape: Fix "cpu release" command
[oweals/u-boot.git]
/
arch
/
arm
/
cpu
/
armv8
/
cache.S
diff --git
a/arch/arm/cpu/armv8/cache.S
b/arch/arm/cpu/armv8/cache.S
index 249799cd01973facb26ff65f73050beea8458325..ab8c08917ad7c5ba1b9e48799b629c3f9f0f5286 100644
(file)
--- a/
arch/arm/cpu/armv8/cache.S
+++ b/
arch/arm/cpu/armv8/cache.S
@@
-9,7
+9,6
@@
#include <asm-offsets.h>
#include <config.h>
#include <asm-offsets.h>
#include <config.h>
-#include <version.h>
#include <asm/macro.h>
#include <linux/linkage.h>
#include <asm/macro.h>
#include <linux/linkage.h>
@@
-31,9
+30,7
@@
ENTRY(__asm_flush_dcache_level)
add x2, x2, #4 /* x2 <- log2(cache line size) */
mov x3, #0x3ff
and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
add x2, x2, #4 /* x2 <- log2(cache line size) */
mov x3, #0x3ff
and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
- add w4, w3, w3
- sub w4, w4, 1 /* round up log2(#ways + 1) */
- clz w5, w4 /* bit position of #ways */
+ clz w5, w3 /* bit position of #ways */
mov x4, #0x7fff
and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
/* x12 <- cache level << 1 */
mov x4, #0x7fff
and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
/* x12 <- cache level << 1 */
@@
-96,7
+93,7
@@
skip:
b.gt loop_level
mov x0, #0
b.gt loop_level
mov x0, #0
- msr csselr_el1, x0 /* res
ot
re csselr_el1 */
+ msr csselr_el1, x0 /* res
to
re csselr_el1 */
dsb sy
isb
mov lr, x15
dsb sy
isb
mov lr, x15
@@
-115,7
+112,7
@@
ENDPROC(__asm_flush_dcache_all)
ENTRY(__asm_invalidate_dcache_all)
mov x16, lr
ENTRY(__asm_invalidate_dcache_all)
mov x16, lr
- mov x0, #0x
ffff
+ mov x0, #0x
1
bl __asm_dcache_all
mov lr, x16
ret
bl __asm_dcache_all
mov lr, x16
ret
@@
-157,3
+154,9
@@
ENTRY(__asm_invalidate_icache_all)
isb sy
ret
ENDPROC(__asm_invalidate_icache_all)
isb sy
ret
ENDPROC(__asm_invalidate_icache_all)
+
+ENTRY(__asm_flush_l3_cache)
+ mov x0, #0 /* return status as success */
+ ret
+ENDPROC(__asm_flush_l3_cache)
+ .weak __asm_flush_l3_cache