+ { PLL1_CFG(30, 1, 0, 0), 1440000000},
+ { PLL1_CFG(29, 1, 0, 0), 1392000000},
+ { PLL1_CFG(28, 1, 0, 0), 1344000000},
+ { PLL1_CFG(27, 1, 0, 0), 1296000000},
+ { PLL1_CFG(26, 1, 0, 0), 1248000000},
+ { PLL1_CFG(25, 1, 0, 0), 1200000000},
+ { PLL1_CFG(24, 1, 0, 0), 1152000000},
+ { PLL1_CFG(23, 1, 0, 0), 1104000000},
+ { PLL1_CFG(22, 1, 0, 0), 1056000000},
+ { PLL1_CFG(21, 1, 0, 0), 1008000000},
+ { PLL1_CFG(20, 1, 0, 0), 960000000 },
+ { PLL1_CFG(19, 1, 0, 0), 912000000 },
+ { PLL1_CFG(16, 1, 0, 0), 768000000 },
+ /* Final catchall entry 384MHz*/
+ { PLL1_CFG(16, 0, 0, 0), 0 },
+