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Merge branch 'master' of git://git.denx.de/u-boot-arm
[oweals/u-boot.git]
/
arch
/
arm
/
cpu
/
armv7
/
start.S
diff --git
a/arch/arm/cpu/armv7/start.S
b/arch/arm/cpu/armv7/start.S
index 6387b8b0aa1c381817227c23f3f5cfbcad2263ab..eee648bdc405f8ac8db7c0e4414f0c79c81d319f 100644
(file)
--- a/
arch/arm/cpu/armv7/start.S
+++ b/
arch/arm/cpu/armv7/start.S
@@
-70,6
+70,18
@@
_end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_TEGRA2
+/*
+ * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
+ * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
+ * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
+ * to pick up its reset vector, which points here.
+ */
+.globl _armboot_start
+_armboot_start:
+ .word _start
+#endif
+
/*
* These are defined in the board-specific linker script.
*/
/*
* These are defined in the board-specific linker script.
*/
@@
-243,6
+255,14
@@
clbss_l:str r2, [r0] /* clear loop... */
* initialization, now running from RAM.
*/
jump_2_ram:
* initialization, now running from RAM.
*/
jump_2_ram:
+/*
+ * If I-cache is enabled invalidate it
+ */
+#ifndef CONFIG_SYS_ICACHE_OFF
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
+ mcr p15, 0, r0, c7, c10, 4 @ DSB
+ mcr p15, 0, r0, c7, c5, 4 @ ISB
+#endif
ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1
ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1
@@
-263,6
+283,7
@@
_rel_dyn_end_ofs:
_dynsym_start_ofs:
.word __dynsym_start - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*************************************************************************
*
* CPU_init_critical registers
/*************************************************************************
*
* CPU_init_critical registers
@@
-278,6
+299,9
@@
cpu_init_crit:
mov r0, #0 @ set up for MCR
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
mov r0, #0 @ set up for MCR
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
+ mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
+ mcr p15, 0, r0, c7, c10, 4 @ DSB
+ mcr p15, 0, r0, c7, c5, 4 @ ISB
/*
* disable MMU stuff and caches
/*
* disable MMU stuff and caches
@@
-286,7
+310,12
@@
cpu_init_crit:
bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
- orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
+ orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
+#ifdef CONFIG_SYS_ICACHE_OFF
+ bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
+#else
+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
+#endif
mcr p15, 0, r0, c1, c0, 0
/*
mcr p15, 0, r0, c1, c0, 0
/*
@@
-299,6
+328,7
@@
cpu_init_crit:
bl lowlevel_init @ go setup pll,mux,memory
mov lr, ip @ restore link
mov pc, lr @ back to my caller
bl lowlevel_init @ go setup pll,mux,memory
mov lr, ip @ restore link
mov pc, lr @ back to my caller
+#endif
/*
*************************************************************************
*
/*
*************************************************************************
*