+
+ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+ clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
+ 0x0000001F, ptr->m2);
+
+ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+ clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
+ 0x0007FF00, ptr->m << 8);
+
+ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+ clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
+ 0x0000007F, ptr->n);
+
+ /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
+ clrsetbits_le32(&prcm_base->clken_pll_iva2,
+ 0x000000F0, ptr->fsel << 4);
+
+ /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ clrsetbits_le32(&prcm_base->clken_pll_iva2,
+ 0x00000007, PLL_LOCK);
+
+ wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
+}
+
+/*
+ * OMAP3630 specific functions
+ */
+
+static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
+ void (*f_lock_pll) (u32, u32, u32, u32);
+ int xip_safe, p0, p1, p2, p3;
+
+ xip_safe = is_running_in_sram();
+
+ /* Moving it to the right sysclk base */
+ ptr += clk_index;
+
+ if (xip_safe) {
+ /* CORE DPLL */
+
+ /* Select relock bypass: CM_CLKEN_PLL[0:2] */
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x00000007, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
+ LDELAY);
+
+ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
+ clrsetbits_le32(&prcm_base->clksel1_emu,
+ 0x001F0000, CORE_M3X2 << 16);
+
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0xF8000000, ptr->m2 << 27);
+
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0x07FF0000, ptr->m << 16);
+
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0x00007F00, ptr->n << 8);
+
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
+
+ /* SSI */
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000F00, CORE_SSI_DIV << 8);
+ /* FSUSB */
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000030, CORE_FUSB_DIV << 4);
+ /* L4 */
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x0000000C, CORE_L4_DIV << 2);
+ /* L3 */
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000003, CORE_L3_DIV);
+ /* GFX */
+ clrsetbits_le32(&prcm_base->clksel_gfx,
+ 0x00000007, GFX_DIV_36X);
+ /* RESET MGR */
+ clrsetbits_le32(&prcm_base->clksel_wkup,
+ 0x00000006, WKUP_RSM << 1);
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x000000F0, ptr->fsel << 4);
+ /* LOCK MODE */
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x00000007, PLL_LOCK);
+
+ wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
+ LDELAY);
+ } else if (is_running_in_flash()) {
+ /*
+ * if running from flash, jump to small relocated code
+ * area in SRAM.
+ */
+ f_lock_pll = (void *) (SRAM_CLK_CODE);
+
+ p0 = readl(&prcm_base->clken_pll);
+ clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
+
+ p1 = readl(&prcm_base->clksel1_pll);
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ clrbits_le32(&p1, 0x00000040);
+
+ p2 = readl(&prcm_base->clksel_core);
+ /* SSI */
+ clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
+ /* FSUSB */
+ clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
+ /* L4 */
+ clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
+ /* L3 */
+ clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
+
+ p3 = (u32)&prcm_base->idlest_ckgen;
+
+ (*f_lock_pll) (p0, p1, p2, p3);
+ }
+}
+
+static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ struct dpll_per_36x_param *ptr;
+
+ ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr += clk_index;
+
+ /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
+ wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
+
+ /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
+ clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
+
+ /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
+ clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
+
+ /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
+ clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
+
+ /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
+ clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
+
+ /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
+ clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
+
+ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
+ clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
+
+ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+ clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
+
+ /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
+ clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
+
+ /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
+ wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
+}
+
+static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr = ptr + clk_index;
+
+ /* PER2 DPLL (DPLL5) */
+ clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
+ wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
+ /* set M2 (usbtll_fck) */
+ clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
+ /* set m (11-bit multiplier) */
+ clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
+ /* set n (7-bit divider)*/
+ clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);