+static void exynos5420_i2c_config(int peripheral)
+{
+ struct exynos5420_gpio_part1 *gpio1 =
+ (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C8:
+ s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C9:
+ s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C10:
+ s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
+ break;
+ }
+}
+
+static void exynos5_i2s_config(int peripheral)
+{
+ int i;
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
+ struct exynos5_gpio_part4 *gpio4 =
+ (struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2S0:
+ for (i = 0; i < 5; i++)
+ s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
+ break;
+ case PERIPH_ID_I2S1:
+ for (i = 0; i < 5; i++)
+ s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+ break;
+ }
+}
+
+void exynos5_spi_config(int peripheral)
+{
+ int cfg = 0, pin = 0, i;
+ struct s5p_gpio_bank *bank = NULL;
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+ struct exynos5_gpio_part2 *gpio2 =
+ (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
+
+ switch (peripheral) {
+ case PERIPH_ID_SPI0:
+ bank = &gpio1->a2;
+ cfg = GPIO_FUNC(0x2);
+ pin = 0;
+ break;
+ case PERIPH_ID_SPI1:
+ bank = &gpio1->a2;
+ cfg = GPIO_FUNC(0x2);
+ pin = 4;
+ break;
+ case PERIPH_ID_SPI2:
+ bank = &gpio1->b1;
+ cfg = GPIO_FUNC(0x5);
+ pin = 1;
+ break;
+ case PERIPH_ID_SPI3:
+ bank = &gpio2->f1;
+ cfg = GPIO_FUNC(0x2);
+ pin = 0;
+ break;
+ case PERIPH_ID_SPI4:
+ for (i = 0; i < 2; i++) {
+ s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+ }
+ break;
+ }
+ if (peripheral != PERIPH_ID_SPI4) {
+ for (i = pin; i < pin + 4; i++)
+ s5p_gpio_cfg_pin(bank, i, cfg);
+ }
+}
+
+void exynos5420_spi_config(int peripheral)
+{
+ int cfg, pin, i;
+ struct s5p_gpio_bank *bank = NULL;
+ struct exynos5420_gpio_part1 *gpio1 =
+ (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+ struct exynos5420_gpio_part4 *gpio4 =
+ (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
+
+ switch (peripheral) {
+ case PERIPH_ID_SPI0:
+ bank = &gpio1->a2;
+ cfg = GPIO_FUNC(0x2);
+ pin = 0;
+ break;
+ case PERIPH_ID_SPI1:
+ bank = &gpio1->a2;
+ cfg = GPIO_FUNC(0x2);
+ pin = 4;
+ break;
+ case PERIPH_ID_SPI2:
+ bank = &gpio1->b1;
+ cfg = GPIO_FUNC(0x5);
+ pin = 1;
+ break;
+ case PERIPH_ID_SPI3:
+ bank = &gpio4->f1;
+ cfg = GPIO_FUNC(0x2);
+ pin = 0;
+ break;
+ case PERIPH_ID_SPI4:
+ cfg = 0;
+ pin = 0;
+ break;
+ default:
+ cfg = 0;
+ pin = 0;
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
+ }
+
+ if (peripheral != PERIPH_ID_SPI4) {
+ for (i = pin; i < pin + 4; i++)
+ s5p_gpio_cfg_pin(bank, i, cfg);
+ } else {
+ for (i = 0; i < 2; i++) {
+ s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
+ }
+ }
+}
+