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sun6i: cpu_reset: Do not return from cpu_reset()
[oweals/u-boot.git]
/
arch
/
arm
/
cpu
/
armv7
/
am33xx
/
emif4.c
diff --git
a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 3e39752380d700e542df390918121e19d4a38ae5..27fa3fb4628bbfa08ff38a29386d09144e799668 100644
(file)
--- a/
arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/
arch/arm/cpu/armv7/am33xx/emif4.c
@@
-21,6
+21,10
@@
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
int dram_init(void)
{
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ sdram_init();
+#endif
+
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
@@
-35,7
+39,7
@@
void dram_init_banksize(void)
}
}
-#if
defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#if
ndef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_TI81XX
static struct dmm_lisa_map_regs *hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)DMM_BASE;
#ifdef CONFIG_TI81XX
static struct dmm_lisa_map_regs *hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)DMM_BASE;
@@
-108,17
+112,21
@@
void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
#endif
#ifdef CONFIG_AM43XX
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
#endif
#ifdef CONFIG_AM43XX
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
- while ((readl(&cm_device->cm_dll_ctrl) &
&
CM_DLL_READYST) == 0)
+ while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
;
;
- writel(0x80000000, &ddrctrl->ddrioctrl);
config_io_ctrl(ioregs);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
config_io_ctrl(ioregs);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
+ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+ /* Allow EMIF to control DDR_RESET */
+ writel(0x00000000, &ddrctrl->ddrioctrl);
#endif
/* Program EMIF instance */
#endif
/* Program EMIF instance */