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arm/davinci/da850: add uart0 pinmux
[oweals/u-boot.git]
/
arch
/
arm
/
cpu
/
arm926ejs
/
cache.c
diff --git
a/arch/arm/cpu/arm926ejs/cache.c
b/arch/arm/cpu/arm926ejs/cache.c
index 5b23e3a71b759db16dc7e14deab73b4c72d80aa8..2740ad7e29bef7b59704e691ca95964e9b9fc662 100644
(file)
--- a/
arch/arm/cpu/arm926ejs/cache.c
+++ b/
arch/arm/cpu/arm926ejs/cache.c
@@
-30,7
+30,7
@@
void invalidate_dcache_all(void)
{
void invalidate_dcache_all(void)
{
- asm volatile("mcr p15, 0, %0, c7, c6, 0\n"
::
"r"(0));
+ asm volatile("mcr p15, 0, %0, c7, c6, 0\n"
: :
"r"(0));
}
void flush_dcache_all(void)
}
void flush_dcache_all(void)
@@
-40,7
+40,7
@@
void flush_dcache_all(void)
"mrc p15, 0, r15, c7, c14, 3\n"
"bne 0b\n"
"mcr p15, 0, %0, c7, c10, 4\n"
"mrc p15, 0, r15, c7, c14, 3\n"
"bne 0b\n"
"mcr p15, 0, %0, c7, c10, 4\n"
-
::"r"(0):
"memory"
+
: : "r"(0) :
"memory"
);
}
);
}
@@
-55,7
+55,7
@@
static int check_cache_range(unsigned long start, unsigned long stop)
ok = 0;
if (!ok)
ok = 0;
if (!ok)
-
printf
("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+
debug
("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
start, stop);
return ok;
start, stop);
return ok;
@@
-67,7
+67,7
@@
void invalidate_dcache_range(unsigned long start, unsigned long stop)
return;
while (start < stop) {
return;
while (start < stop) {
- asm volatile("mcr p15, 0, %0, c7, c6, 1\n"
::
"r"(start));
+ asm volatile("mcr p15, 0, %0, c7, c6, 1\n"
: :
"r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
}
start += CONFIG_SYS_CACHELINE_SIZE;
}
}
@@
-78,11
+78,11
@@
void flush_dcache_range(unsigned long start, unsigned long stop)
return;
while (start < stop) {
return;
while (start < stop) {
- asm volatile("mcr p15, 0, %0, c7, c14, 1\n"
::
"r"(start));
+ asm volatile("mcr p15, 0, %0, c7, c14, 1\n"
: :
"r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
start += CONFIG_SYS_CACHELINE_SIZE;
}
- asm
("mcr p15, 0, %0, c7, c10, 4\n"::
"r"(0));
+ asm
volatile("mcr p15, 0, %0, c7, c10, 4\n" : :
"r"(0));
}
void flush_cache(unsigned long start, unsigned long size)
}
void flush_cache(unsigned long start, unsigned long size)
@@
-114,8
+114,7
@@
void flush_cache(unsigned long start, unsigned long size)
/*
* Stub implementations for l2 cache operations
*/
/*
* Stub implementations for l2 cache operations
*/
-void __l2_cache_disable(void)
-{
-}
+void __l2_cache_disable(void) {}
+
void l2_cache_disable(void)
void l2_cache_disable(void)
-
__attribute__((weak, alias("__l2_cache_disable")));
+ __attribute__((weak, alias("__l2_cache_disable")));