#include <asm/io.h>
#include <asm/pci.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define GPIO_PER_BANK 32
struct ich6_bank_priv {
/* Is the device present? */
tmpword = x86_pci_read_config16(pci_dev, PCI_VENDOR_ID);
if (tmpword != PCI_VENDOR_ID_INTEL) {
- debug("%s: wrong VendorID\n", __func__);
+ debug("%s: wrong VendorID %x\n", __func__, tmpword);
return -ENODEV;
}
* at the offset that we just read. Bit 0 indicates that it's
* an I/O address, not a memory address, so mask that off.
*/
- return tmplong & 0xfffc;
+ return tmplong & 1 ? tmplong & ~3 : tmplong & ~15;
}
static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
debug("%s: io-base offset not present\n", __func__);
} else {
iobase = gpio_ich6_get_base(iobase_offset);
- if (iobase < 0) {
+ if (IS_ERR_VALUE(iobase)) {
debug("%s: invalid IOBASE address (%08x)\n", __func__,
iobase);
return -EINVAL;
{
struct ich6_bank_priv *bank = dev_get_priv(dev);
- return _ich6_gpio_set_direction(inl(bank->io_sel), offset, 0);
+ return _ich6_gpio_set_direction(bank->io_sel, offset, 0);
}
static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
int ret;
struct ich6_bank_priv *bank = dev_get_priv(dev);
- ret = _ich6_gpio_set_direction(inl(bank->io_sel), offset, 1);
+ ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);
if (ret)
return ret;