#include <common.h>
#include <miiphy.h>
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
#include <asm/types.h>
#include <linux/list.h>
#include <malloc.h>
#include <net.h>
/* local debug macro */
-#define MII_DEBUG
#undef MII_DEBUG
#undef debug
unsigned short tmp;
if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
-#ifdef DEBUG
- puts ("PHY ID register 2 read failed\n");
-#endif
+ debug ("PHY ID register 2 read failed\n");
return (-1);
}
reg = tmp;
-#ifdef DEBUG
- printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
-#endif
+ debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
+
if (reg == 0xFFFF) {
/* No physical device present at this address */
return (-1);
}
if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
-#ifdef DEBUG
- puts ("PHY ID register 1 read failed\n");
-#endif
+ debug ("PHY ID register 1 read failed\n");
return (-1);
}
reg |= tmp << 16;
-#ifdef DEBUG
- printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
-#endif
+ debug ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
+
*oui = (reg >> 10);
*model = (unsigned char)((reg >> 4) & 0x0000003F);
*rev = (unsigned char)(reg & 0x0000000F);
int miiphy_reset (char *devname, unsigned char addr)
{
unsigned short reg;
- int loop_cnt;
+ int timeout = 500;
if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) {
-#ifdef DEBUG
- printf ("PHY status read failed\n");
-#endif
+ debug ("PHY status read failed\n");
return (-1);
}
- if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) {
-#ifdef DEBUG
- puts ("PHY reset failed\n");
-#endif
+ if (miiphy_write (devname, addr, PHY_BMCR, reg | PHY_BMCR_RESET) != 0) {
+ debug ("PHY reset failed\n");
return (-1);
}
#ifdef CONFIG_PHY_RESET_DELAY
* auto-clearing). This should happen within 0.5 seconds per the
* IEEE spec.
*/
- loop_cnt = 0;
reg = 0x8000;
- while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
- if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) {
-# ifdef DEBUG
- puts ("PHY status read failed\n");
-# endif
- return (-1);
+ while (((reg & 0x8000) != 0) && timeout--) {
+ if (miiphy_read(devname, addr, PHY_BMCR, ®) != 0) {
+ debug("PHY status read failed\n");
+ return -1;
}
+ udelay(1000);
}
if ((reg & 0x8000) == 0) {
return (0);
/* Get speed from basic control settings. */
return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET;
- miiphy_read_failed:
+miiphy_read_failed:
printf (" read failed, assuming 10BASE-T\n");
return _10BASET;
}
/* Get speed from basic control settings. */
return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF;
- miiphy_read_failed:
+miiphy_read_failed:
printf (" read failed, assuming half duplex\n");
return HALF;
}
#endif
}
-#ifdef CFG_FAULT_ECHO_LINK_DOWN
+#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/*****************************************************************************
*
* Determine link status
}
}
#endif
-#endif /* CONFIG_MII */