ed4aadf2beb2888b3943fe1ce584131686890fcd
[oweals/openwrt.git] /
1 From 28b5c129ca6e585ec95c160ec4297bc6c6360b6f Mon Sep 17 00:00:00 2001
2 From: Minas Harutyunyan <minas.harutyunyan@synopsys.com>
3 Date: Mon, 4 Mar 2019 17:08:07 +0400
4 Subject: usb: dwc2: Set lpm mode parameters depend on HW configuration
5
6 If core not supported lpm, i.e. BCM2835 then confusing warnings seen
7 in log.
8
9 To avoid these warnings, added function dwc2_set_param_lpm() to set
10 lpm and other lpm related parameters based on lpm support by core.
11
12 Signed-off-by: Minas Harutyunyan <hminas@synopsys.com>
13 Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
14 ---
15  drivers/usb/dwc2/params.c | 23 ++++++++++++++++++-----
16  1 file changed, 18 insertions(+), 5 deletions(-)
17
18 --- a/drivers/usb/dwc2/params.c
19 +++ b/drivers/usb/dwc2/params.c
20 @@ -273,6 +273,23 @@ static void dwc2_set_param_power_down(st
21         hsotg->params.power_down = val;
22  }
23  
24 +static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
25 +{
26 +       struct dwc2_core_params *p = &hsotg->params;
27 +
28 +       p->lpm = hsotg->hw_params.lpm_mode;
29 +       if (p->lpm) {
30 +               p->lpm_clock_gating = true;
31 +               p->besl = true;
32 +               p->hird_threshold_en = true;
33 +               p->hird_threshold = 4;
34 +       } else {
35 +               p->lpm_clock_gating = false;
36 +               p->besl = false;
37 +               p->hird_threshold_en = false;
38 +       }
39 +}
40 +
41  /**
42   * dwc2_set_default_params() - Set all core parameters to their
43   * auto-detected default values.
44 @@ -291,6 +308,7 @@ static void dwc2_set_default_params(stru
45         dwc2_set_param_speed(hsotg);
46         dwc2_set_param_phy_utmi_width(hsotg);
47         dwc2_set_param_power_down(hsotg);
48 +       dwc2_set_param_lpm(hsotg);
49         p->phy_ulpi_ddr = false;
50         p->phy_ulpi_ext_vbus = false;
51  
52 @@ -303,11 +321,6 @@ static void dwc2_set_default_params(stru
53         p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
54         p->uframe_sched = true;
55         p->external_id_pin_ctl = false;
56 -       p->lpm = true;
57 -       p->lpm_clock_gating = true;
58 -       p->besl = true;
59 -       p->hird_threshold_en = true;
60 -       p->hird_threshold = 4;
61         p->ipg_isoc_en = false;
62         p->max_packet_count = hw->max_packet_count;
63         p->max_transfer_size = hw->max_transfer_size;