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1 From 99c659cf345640fd0f733cbcaf4583cc2c868ec0 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Mon, 29 Apr 2013 13:21:48 +0200
4 Subject: [PATCH] rt2x00: rt2800lib: add RFCSR initialization for RT3883
5
6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7 ---
8  drivers/net/wireless/ralink/rt2x00/rt2800.h    |    1 +
9  drivers/net/wireless/ralink/rt2x00/rt2800lib.c |  141 +++++++++++++++++++++++++++++++
10  2 files changed, 142 insertions(+)
11
12 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
13 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
14 @@ -2312,6 +2312,7 @@ struct mac_iveiv_entry {
15  /*
16   * RFCSR 2:
17   */
18 +#define RFCSR2_RESCAL_BP               FIELD8(0x40)
19  #define RFCSR2_RESCAL_EN               FIELD8(0x80)
20  #define RFCSR2_RX2_EN_MT7620           FIELD8(0x02)
21  #define RFCSR2_TX2_EN_MT7620           FIELD8(0x20)
22 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
23 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
24 @@ -7878,6 +7878,144 @@ static void rt2800_init_rfcsr_5350(struc
25         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
26  }
27  
28 +static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
29 +{
30 +       u8 rfcsr;
31 +
32 +       /* TODO: get the actual ECO value from the SoC */
33 +       const unsigned int eco = 5;
34 +
35 +       rt2800_rf_init_calibration(rt2x00dev, 2);
36 +
37 +       rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
38 +       rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
39 +       rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
40 +       rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
41 +       rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
42 +       rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
43 +       rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
44 +       rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
45 +       rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
46 +       rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
47 +       rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
48 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
49 +       rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
50 +       rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
51 +       rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
52 +       rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
53 +       rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
54 +
55 +       /* RFCSR 17 will be initialized later based on the
56 +        * frequency offset stored in the EEPROM
57 +        */
58 +
59 +       rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
60 +       rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
61 +       rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
62 +       rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
63 +       rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
64 +       rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
65 +       rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
66 +       rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
67 +       rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
68 +       rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
69 +       rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
70 +       rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
71 +       rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
72 +       rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
73 +       rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
74 +       rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
75 +       rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
76 +       rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
77 +       rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
78 +       rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
79 +       rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
80 +       rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
81 +       rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
82 +       rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
83 +       rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
84 +       rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
85 +       rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
86 +       rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
87 +       rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
88 +       rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
89 +       rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
90 +       rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
91 +       rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
92 +       rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
93 +       rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
94 +       rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
95 +       rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
96 +       rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
97 +       rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
98 +       rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
99 +       rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
100 +       rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
101 +       rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
102 +       rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
103 +       rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
104 +       rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
105 +
106 +       /* TODO: rx filter calibration? */
107 +
108 +       rt2800_bbp_write(rt2x00dev, 137, 0x0f);
109 +
110 +       rt2800_bbp_write(rt2x00dev, 163, 0x9d);
111 +
112 +       rt2800_bbp_write(rt2x00dev, 105, 0x05);
113 +
114 +       rt2800_bbp_write(rt2x00dev, 179, 0x02);
115 +       rt2800_bbp_write(rt2x00dev, 180, 0x00);
116 +       rt2800_bbp_write(rt2x00dev, 182, 0x40);
117 +       rt2800_bbp_write(rt2x00dev, 180, 0x01);
118 +       rt2800_bbp_write(rt2x00dev, 182, 0x9c);
119 +
120 +       rt2800_bbp_write(rt2x00dev, 179, 0x00);
121 +
122 +       rt2800_bbp_write(rt2x00dev, 142, 0x04);
123 +       rt2800_bbp_write(rt2x00dev, 143, 0x3b);
124 +       rt2800_bbp_write(rt2x00dev, 142, 0x06);
125 +       rt2800_bbp_write(rt2x00dev, 143, 0xa0);
126 +       rt2800_bbp_write(rt2x00dev, 142, 0x07);
127 +       rt2800_bbp_write(rt2x00dev, 143, 0xa1);
128 +       rt2800_bbp_write(rt2x00dev, 142, 0x08);
129 +       rt2800_bbp_write(rt2x00dev, 143, 0xa2);
130 +       rt2800_bbp_write(rt2x00dev, 148, 0xc8);
131 +
132 +       if (eco == 5) {
133 +               rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
134 +               rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
135 +       }
136 +
137 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
138 +       rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
139 +       rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
140 +       rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
141 +       msleep(1);
142 +       rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
143 +       rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
144 +
145 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
146 +       rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
147 +       rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
148 +
149 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
150 +       rfcsr |= 0xc0;
151 +       rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
152 +
153 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
154 +       rfcsr |= 0x20;
155 +       rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
156 +
157 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
158 +       rfcsr |= 0x20;
159 +       rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
160 +
161 +       rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
162 +       rfcsr &= ~0xee;
163 +       rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
164 +}
165 +
166  static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
167  {
168         rt2800_rf_init_calibration(rt2x00dev, 2);
169 @@ -8720,6 +8858,9 @@ static void rt2800_init_rfcsr(struct rt2
170         case RT3390:
171                 rt2800_init_rfcsr_3390(rt2x00dev);
172                 break;
173 +       case RT3883:
174 +               rt2800_init_rfcsr_3883(rt2x00dev);
175 +               break;
176         case RT3572:
177                 rt2800_init_rfcsr_3572(rt2x00dev);
178                 break;