git.librecmc.org Git - oweals/openwrt.git/blob

   1 From 233c77d4f1d12e4337fba1146d5197f4c0f9107d Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Wed, 25 Jul 2018 10:37:45 +0200
   4 Subject: [PATCH] ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanism
   5
   6 v1 was the incorrect choice here and sometimes the board
   7 would not come up properly.
   8
   9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  10 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
  11 Signed-off-by: John Crispin <john@phrozen.org>
  12 Signed-off-by: Andy Gross <andy.gross@linaro.org>
  13 ---
  14  arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++--------
  15  1 file changed, 17 insertions(+), 8 deletions(-)
  16
  17 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  18 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  19 @@ -52,7 +52,8 @@
  20                 cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a7";
  23 -                       enable-method = "qcom,kpss-acc-v1";
  24 +                       enable-method = "qcom,kpss-acc-v2";
  25 +                       next-level-cache = <&L2>;
  26                         qcom,acc = <&acc0>;
  27                         qcom,saw = <&saw0>;
  28                         reg = <0x0>;
  29 @@ -71,7 +72,8 @@
  30                 cpu@1 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a7";
  33 -                       enable-method = "qcom,kpss-acc-v1";
  34 +                       enable-method = "qcom,kpss-acc-v2";
  35 +                       next-level-cache = <&L2>;
  36                         qcom,acc = <&acc1>;
  37                         qcom,saw = <&saw1>;
  38                         reg = <0x1>;
  39 @@ -90,7 +92,8 @@
  40                 cpu@2 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a7";
  43 -                       enable-method = "qcom,kpss-acc-v1";
  44 +                       enable-method = "qcom,kpss-acc-v2";
  45 +                       next-level-cache = <&L2>;
  46                         qcom,acc = <&acc2>;
  47                         qcom,saw = <&saw2>;
  48                         reg = <0x2>;
  49 @@ -109,7 +112,8 @@
  50                 cpu@3 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53 -                       enable-method = "qcom,kpss-acc-v1";
  54 +                       enable-method = "qcom,kpss-acc-v2";
  55 +                       next-level-cache = <&L2>;
  56                         qcom,acc = <&acc3>;
  57                         qcom,saw = <&saw3>;
  58                         reg = <0x3>;
  59 @@ -124,6 +128,11 @@
  60                         >;
  61                         clock-latency = <256000>;
  62                 };
  63 +
  64 +               L2: l2-cache {
  65 +                       compatible = "cache";
  66 +                       cache-level = <2>;
  67 +               };
  68         };
  69
  70         pmu {
  71 @@ -292,22 +301,22 @@
  72                 };
  73
  74                  acc0: clock-controller@b088000 {
  75 -                        compatible = "qcom,kpss-acc-v1";
  76 +                        compatible = "qcom,kpss-acc-v2";
  77                          reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
  78                  };
  79
  80                  acc1: clock-controller@b098000 {
  81 -                        compatible = "qcom,kpss-acc-v1";
  82 +                        compatible = "qcom,kpss-acc-v2";
  83                          reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
  84                  };
  85
  86                  acc2: clock-controller@b0a8000 {
  87 -                        compatible = "qcom,kpss-acc-v1";
  88 +                        compatible = "qcom,kpss-acc-v2";
  89                          reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
  90                  };
  91
  92                  acc3: clock-controller@b0b8000 {
  93 -                        compatible = "qcom,kpss-acc-v1";
  94 +                        compatible = "qcom,kpss-acc-v2";
  95                          reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
  96                  };
  97