git.librecmc.org Git - oweals/openwrt.git/blob

   1 From e03f571b1e9564ca422134b2013d80c8373c9db2 Mon Sep 17 00:00:00 2001
   2 From: Alison Wang <b18965@freescale.com>
   3 Date: Fri, 13 May 2016 10:19:24 +0800
   4 Subject: [PATCH 01/93] armv8: Support loading 32-bit OS in AArch32 execution
   5  state
   6
   7 To support loading a 32-bit OS, the execution state will change from
   8 AArch64 to AArch32 when jumping to kernel.
   9
  10 The architecture information will be got through checking FIT
  11 image, then U-Boot will load 32-bit OS or 64-bit OS automatically.
  12
  13 Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
  14 Signed-off-by: Alison Wang <alison.wang@nxp.com>
  15 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
  16 ---
  17  arch/arm/cpu/armv8/transition.S |  100 +++++++++++++++++++++++++++++++++++++++
  18  arch/arm/include/asm/system.h   |    2 +
  19  arch/arm/lib/bootm.c            |   20 +++++++-
  20  common/image-fit.c              |   12 ++++-
  21  4 files changed, 131 insertions(+), 3 deletions(-)
  22
  23 diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
  24 index 253a39b..9d7a17a 100644
  25 --- a/arch/arm/cpu/armv8/transition.S
  26 +++ b/arch/arm/cpu/armv8/transition.S
  27 @@ -21,3 +21,103 @@ ENTRY(armv8_switch_to_el1)
  28  0:     ret
  29  1:     armv8_switch_to_el1_m x0, x1
  30  ENDPROC(armv8_switch_to_el1)
  31 +
  32 +/*
  33 + * x0: kernel entry point
  34 + * x1: machine nr
  35 + * x2: fdt address
  36 + */
  37 +ENTRY(armv8_switch_to_el2_aarch32)
  38 +       switch_el x3, 1f, 0f, 0f
  39 +0:     ret
  40 +1:
  41 +       mov     x7, x0
  42 +       mov     x8, x1
  43 +       mov     x9, x2
  44 +
  45 +       /* 32bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
  46 +       mov     x1, 0x1b1
  47 +       msr     scr_el3, x1
  48 +       msr     cptr_el3, xzr   /* Disable coprocessor traps to EL3 */
  49 +       mov     x1, 0x33ff
  50 +       msr     cptr_el2, x1    /* Disable coprocessor traps to EL2 */
  51 +
  52 +       /* Initialize Generic Timers */
  53 +       msr     cntvoff_el2, xzr
  54 +
  55 +       mov     x1, #0x0830
  56 +       movk    x1, #0x30c5, lsl #16
  57 +       msr     sctlr_el2, x1
  58 +
  59 +       /* Return to AArch32 Hypervisor mode */
  60 +       mov     x1, sp
  61 +       msr     sp_el2, x1
  62 +       mrs     x1, vbar_el3
  63 +       msr     vbar_el2, x1    /* Migrate VBAR */
  64 +       mov     x1, #0x1da
  65 +       msr     spsr_el3, x1
  66 +       msr     elr_el3, x7
  67 +
  68 +       mov     x0, #0
  69 +       mov     x1, x8
  70 +       mov     x2, x9
  71 +
  72 +       eret
  73 +ENDPROC(armv8_switch_to_el2_aarch32)
  74 +
  75 +/*
  76 + * x0: kernel entry point
  77 + * x1: machine nr
  78 + * x2: fdt address
  79 + */
  80 +ENTRY(armv8_switch_to_el1_aarch32)
  81 +       switch_el x3, 0f, 1f, 0f
  82 +0:     ret
  83 +1:
  84 +       mov     x7, x0
  85 +       mov     x8, x1
  86 +       mov     x9, x2
  87 +
  88 +       /* Initialize Generic Timers */
  89 +       mrs     x0, cnthctl_el2
  90 +       orr     x0, x0, #0x3            /* Enable EL1 access to timers */
  91 +       msr     cnthctl_el2, x0
  92 +       msr     cntvoff_el2, xzr
  93 +
  94 +        /* Initialize MPID/MPIDR registers */
  95 +       mrs     x0, midr_el1
  96 +       mrs     x1, mpidr_el1
  97 +       msr     vpidr_el2, x0
  98 +       msr     vmpidr_el2, x1
  99 +
 100 +        /* Disable coprocessor traps */
 101 +       mov     x0, #0x33ff
 102 +       msr     cptr_el2, x0            /* Disable coprocessor traps to EL2 */
 103 +        msr    hstr_el2, xzr           /* Disable coprocessor traps to EL2 */
 104 +        mov    x0, #3 << 20
 105 +        msr    cpacr_el1, x0           /* Enable FP/SIMD at EL1 */
 106 +
 107 +       /* Initialize HCR_EL2 */
 108 +       mov     x0, #(0 << 31)          /* 32bit EL1 */
 109 +       orr     x0, x0, #(1 << 29)      /* Disable HVC */
 110 +       msr     hcr_el2, x0
 111 +
 112 +       mov     x0, #0x0800
 113 +       movk    x0, #0x30d0, lsl #16
 114 +       msr     sctlr_el1, x0
 115 +
 116 +       /* Return to AArch32 Supervisor mode */
 117 +       mov     x0, sp
 118 +       msr     sp_el1, x0              /* Migrate SP */
 119 +       mrs     x0, vbar_el2
 120 +       msr     vbar_el1, x0            /* Migrate VBAR */
 121 +       mov     x0, #0x1d3
 122 +       msr     spsr_el2, x0
 123 +       msr     elr_el2, x7
 124 +
 125 +       mov     x0, #0
 126 +       mov     x1, x8
 127 +       mov     x2, x9
 128 +
 129 +       eret
 130 +ENDPROC(armv8_switch_to_el1_aarch32)
 131 diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
 132 index 71b3108..0ecbcf7 100644
 133 --- a/arch/arm/include/asm/system.h
 134 +++ b/arch/arm/include/asm/system.h
 135 @@ -81,6 +81,8 @@ int __asm_flush_l3_cache(void);
 136
 137  void armv8_switch_to_el2(void);
 138  void armv8_switch_to_el1(void);
 139 +void armv8_switch_to_el2_aarch32(u64 entry_point, u64 mach_nr, u64 fdt_addr);
 140 +void armv8_switch_to_el1_aarch32(u64 entry_point, u64 mach_nr, u64 fdt_addr);
 141  void gic_init(void);
 142  void gic_send_sgi(unsigned long sgino);
 143  void wait_for_wakeup(void);
 144 diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
 145 index a477cae..36f2cb0 100644
 146 --- a/arch/arm/lib/bootm.c
 147 +++ b/arch/arm/lib/bootm.c
 148 @@ -276,8 +276,24 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 149         announce_and_cleanup(fake);
 150
 151         if (!fake) {
 152 -               do_nonsec_virt_switch();
 153 -               kernel_entry(images->ft_addr, NULL, NULL, NULL);
 154 +               if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
 155 +                   (images->os.arch == IH_ARCH_ARM)) {
 156 +                       smp_kick_all_cpus();
 157 +                       dcache_disable();
 158 +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
 159 +                       armv8_switch_to_el2();
 160 +                       armv8_switch_to_el1_aarch32((u64)images->ep,
 161 +                                                   (u64)gd->bd->bi_arch_number,
 162 +                                                   (u64)images->ft_addr);
 163 +#else
 164 +                       armv8_switch_to_el2_aarch32((u64)images->ep,
 165 +                                                   (u64)gd->bd->bi_arch_number,
 166 +                                                   (u64)images->ft_addr);
 167 +#endif
 168 +               } else {
 169 +                       do_nonsec_virt_switch();
 170 +                       kernel_entry(images->ft_addr, NULL, NULL, NULL);
 171 +               }
 172         }
 173  #else
 174         unsigned long machid = gd->bd->bi_arch_number;
 175 diff --git a/common/image-fit.c b/common/image-fit.c
 176 index c531ee7..0d54f71 100644
 177 --- a/common/image-fit.c
 178 +++ b/common/image-fit.c
 179 @@ -1144,7 +1144,8 @@ int fit_image_check_arch(const void *fit, int noffset, uint8_t arch)
 180         if (fit_image_get_arch(fit, noffset, &image_arch))
 181                 return 0;
 182         return (arch == image_arch) ||
 183 -               (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64);
 184 +               (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64) ||
 185 +               (arch == IH_ARCH_ARM64 && image_arch == IH_ARCH_ARM);
 186  }
 187
 188  /**
 189 @@ -1567,6 +1568,9 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 190         int type_ok, os_ok;
 191         ulong load, data, len;
 192         uint8_t os;
 193 +#ifndef USE_HOSTCC
 194 +       uint8_t os_arch;
 195 +#endif
 196         const char *prop_name;
 197         int ret;
 198
 199 @@ -1650,6 +1654,12 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 200                 return -ENOEXEC;
 201         }
 202  #endif
 203 +
 204 +#ifndef USE_HOSTCC
 205 +       fit_image_get_arch(fit, noffset, &os_arch);
 206 +       images->os.arch = os_arch;
 207 +#endif
 208 +
 209         if (image_type == IH_TYPE_FLATDT &&
 210             !fit_image_check_comp(fit, noffset, IH_COMP_NONE)) {
 211                 puts("FDT image is compressed");
 212 --
 213 1.7.9.5
 214