7eb586f849964710e45f3d678ff4edf52e8e7b03
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1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
2 Subject: [PATCH] ARM: BCM5301X: Set 5 GHz wireless frequency limits on Netgear
3  R8000
4 MIME-Version: 1.0
5 Content-Type: text/plain; charset=UTF-8
6 Content-Transfer-Encoding: 8bit
7
8 Netgear R8000 is a tri-band home router. It has three BCM43602 chipsets
9 two of them for 5 GHz band. Both seem the same and their firmwares
10 report the same set of channels. The problem is due to hardware / board
11 design there are extra limitations that should be respected.
12
13 First PHY should be used for U-NII-2 and U-NII-3. Third PHY should be
14 used for U-NII-1. Using them in a different way may result in wireless
15 not working or in noticeably reduced performance. Basic version of this
16 info was provided by Broadcom employee, then it has been verified by me
17 using original vendor firmware (which has limitations hardcoded in UI).
18
19 This patch uses recently introduced ieee80211-freq-limit property to
20 describe these limitations at DT level.
21
22 Referencing PCIe devices in DT required specifying all related bridges.
23 Below you can see (a bit complex) PCI tree from R8000 that explains all
24 entries that I needed to put in DT.
25
26 0000:00:00.0            14e4:8012       Bridge Device
27 └─ 0000:01:00.0             14e4:aa52       Network Controller
28
29 0001:00:00.0            14e4:8012       Bridge Device
30 └─ 0001:01:00.0             10b5:8603       Bridge Device
31    ├─ 0001:02:01.0  10b5:8603       Bridge Device
32    │  └─ 0001:03:00.0     14e4:aa52       Network Controller
33    ├─ 0001:02:02.0  10b5:8603       Bridge Device
34    │  └─ 0001:04:00.0     14e4:aa52       Network Controller
35    ├─ 0001:02:03.0  000d:0000       0x000000
36    ├─ 0001:02:04.0  000d:0000       0x000000
37    ├─ 0001:02:05.0  000d:0000       0x000000
38    ├─ 0001:02:06.0  000d:0000       0x000000
39    ├─ (...)
40    ├─ 0001:02:1d.0  000d:0000       0x000000
41    ├─ 0001:02:1e.0  000d:0000       0x000000
42    └─ 0001:02:1f.0  000d:0000       0x000000
43
44 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
45 ---
46  arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 48 +++++++++++++++++++++++++++++
47  arch/arm/boot/dts/bcm5301x.dtsi             |  8 +++++
48  2 files changed, 56 insertions(+)
49
50 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
51 +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
52 @@ -108,6 +108,54 @@
53         };
54  };
55  
56 +&pcie0 {
57 +       #address-cells = <3>;
58 +       #size-cells = <2>;
59 +
60 +       bridge@0,0,0 {
61 +               reg = <0x0000 0 0 0 0>;
62 +
63 +               #address-cells = <3>;
64 +               #size-cells = <2>;
65 +
66 +               wifi@0,1,0 {
67 +                       reg = <0x0000 0 0 0 0>;
68 +                       ieee80211-freq-limit = <5735000 5835000>;
69 +               };
70 +       };
71 +};
72 +
73 +&pcie1 {
74 +       #address-cells = <3>;
75 +       #size-cells = <2>;
76 +
77 +       bridge@1,0,0 {
78 +               reg = <0x0000 0 0 0 0>;
79 +
80 +               #address-cells = <3>;
81 +               #size-cells = <2>;
82 +
83 +               bridge@1,1,0 {
84 +                       reg = <0x0000 0 0 0 0>;
85 +
86 +                       #address-cells = <3>;
87 +                       #size-cells = <2>;
88 +
89 +                       bridge@1,2,2 {
90 +                               reg = <0x1000 0 0 0 0>;
91 +
92 +                               #address-cells = <3>;
93 +                               #size-cells = <2>;
94 +
95 +                               wifi@1,4,0 {
96 +                                       reg = <0x0000 0 0 0 0>;
97 +                                       ieee80211-freq-limit = <5170000 5730000>;
98 +                               };
99 +                       };
100 +               };
101 +       };
102 +};
103 +
104  &usb2 {
105         vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
106  };
107 --- a/arch/arm/boot/dts/bcm5301x.dtsi
108 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
109 @@ -243,6 +243,14 @@
110                         #gpio-cells = <2>;
111                 };
112  
113 +               pcie0: pcie@12000 {
114 +                       reg = <0x00012000 0x1000>;
115 +               };
116 +
117 +               pcie1: pcie@13000 {
118 +                       reg = <0x00013000 0x1000>;
119 +               };
120 +
121                 usb2: usb2@21000 {
122                         reg = <0x00021000 0x1000>;
123