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   1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   2 Subject: [PATCH 1/2] net: phy: cherry-pick Broadcom drivers updates from
   3  v4.10-rc1
   4
   5 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
   6 ---
   7
   8 --- a/drivers/net/phy/broadcom.c
   9 +++ b/drivers/net/phy/broadcom.c
  10 @@ -337,6 +337,41 @@ static int bcm5481_config_aneg(struct ph
  11         return ret;
  12  }
  13
  14 +static int bcm54612e_config_aneg(struct phy_device *phydev)
  15 +{
  16 +       int ret;
  17 +
  18 +       /* First, auto-negotiate. */
  19 +       ret = genphy_config_aneg(phydev);
  20 +
  21 +       /* Clear TX internal delay unless requested. */
  22 +       if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
  23 +           (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
  24 +               /* Disable TXD to GTXCLK clock delay (default set) */
  25 +               /* Bit 9 is the only field in shadow register 00011 */
  26 +               bcm_phy_write_shadow(phydev, 0x03, 0);
  27 +       }
  28 +
  29 +       /* Clear RX internal delay unless requested. */
  30 +       if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
  31 +           (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
  32 +               u16 reg;
  33 +
  34 +               /* Errata: reads require filling in the write selector field */
  35 +               bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  36 +                                    MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
  37 +               reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
  38 +               /* Disable RXD to RXC delay (default set) */
  39 +               reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
  40 +               /* Clear shadow selector field */
  41 +               reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
  42 +               bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  43 +                                    MII_BCM54XX_AUXCTL_MISC_WREN | reg);
  44 +       }
  45 +
  46 +       return ret;
  47 +}
  48 +
  49  static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
  50  {
  51         int val;
  52 @@ -488,6 +523,19 @@ static struct phy_driver broadcom_driver
  53         .config_intr    = bcm_phy_config_intr,
  54         .driver         = { .owner = THIS_MODULE },
  55  }, {
  56 +       .phy_id         = PHY_ID_BCM54612E,
  57 +       .phy_id_mask    = 0xfffffff0,
  58 +       .name           = "Broadcom BCM54612E",
  59 +       .features       = PHY_GBIT_FEATURES |
  60 +                         SUPPORTED_Pause | SUPPORTED_Asym_Pause,
  61 +       .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
  62 +       .config_init    = bcm54xx_config_init,
  63 +       .config_aneg    = bcm54612e_config_aneg,
  64 +       .read_status    = genphy_read_status,
  65 +       .ack_interrupt  = bcm_phy_ack_intr,
  66 +       .config_intr    = bcm_phy_config_intr,
  67 +       .driver         = { .owner = THIS_MODULE },
  68 +}, {
  69         .phy_id         = PHY_ID_BCM54616S,
  70         .phy_id_mask    = 0xfffffff0,
  71         .name           = "Broadcom BCM54616S",
  72 @@ -612,6 +660,7 @@ static struct mdio_device_id __maybe_unu
  73         { PHY_ID_BCM5411, 0xfffffff0 },
  74         { PHY_ID_BCM5421, 0xfffffff0 },
  75         { PHY_ID_BCM5461, 0xfffffff0 },
  76 +       { PHY_ID_BCM54612E, 0xfffffff0 },
  77         { PHY_ID_BCM54616S, 0xfffffff0 },
  78         { PHY_ID_BCM5464, 0xfffffff0 },
  79         { PHY_ID_BCM5481, 0xfffffff0 },
  80 --- a/include/linux/brcmphy.h
  81 +++ b/include/linux/brcmphy.h
  82 @@ -18,6 +18,7 @@
  83  #define PHY_ID_BCM5421                 0x002060e0
  84  #define PHY_ID_BCM5464                 0x002060b0
  85  #define PHY_ID_BCM5461                 0x002060c0
  86 +#define PHY_ID_BCM54612E               0x03625e60
  87  #define PHY_ID_BCM54616S               0x03625d10
  88  #define PHY_ID_BCM57780                        0x03625d90
  89
  90 @@ -102,11 +103,12 @@
  91  #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA      0x0800
  92
  93  #define MII_BCM54XX_AUXCTL_MISC_WREN   0x8000
  94 +#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW   0x0100
  95  #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX    0x0200
  96  #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC     0x7000
  97  #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC        0x0007
  98
  99 -#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL      0x0000
 100 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK        0x0007
 101
 102  /*
 103   * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,