git.librecmc.org Git - oweals/openwrt.git/blob

   1 From 125afc5cf080b29e9114d89f6052fa4a936a3f19 Mon Sep 17 00:00:00 2001
   2 From: Stefan Wahren <wahrenst@gmx.net>
   3 Date: Thu, 19 Sep 2019 20:12:15 +0200
   4 Subject: [PATCH] clk: bcm2835: Introduce SoC specific clock
   5  registration
   6
   7 commit ee0a5a9013b2b2502571a763c3093d400d18191f upstream.
   8
   9 In order to support SoC specific clocks (e.g. emmc2 for BCM2711), we
  10 extend the description with a SoC support flag. This approach avoids long
  11 and mostly redundant lists of clock IDs. Since PLLH is specific to
  12 BCM2835, we register only rest of the clocks as common to all SoC.
  13
  14 Suggested-by: Florian Fainelli <f.fainelli@gmail.com>
  15 Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
  16 Reviewed-by: Matthias Brugger <mbrugger@suse.com>
  17 Acked-by: Eric Anholt <eric@anholt.net>
  18 Reviewed-by: Eric Anholt <eric@anholt.net>
  19 ---
  20  drivers/clk/bcm/clk-bcm2835.c | 115 +++++++++++++++++++++++++++++-----
  21  1 file changed, 98 insertions(+), 17 deletions(-)
  22
  23 --- a/drivers/clk/bcm/clk-bcm2835.c
  24 +++ b/drivers/clk/bcm/clk-bcm2835.c
  25 @@ -40,7 +40,7 @@
  26  #include <linux/debugfs.h>
  27  #include <linux/delay.h>
  28  #include <linux/module.h>
  29 -#include <linux/of.h>
  30 +#include <linux/of_device.h>
  31  #include <linux/platform_device.h>
  32  #include <linux/slab.h>
  33  #include <dt-bindings/clock/bcm2835.h>
  34 @@ -301,6 +301,9 @@
  35
  36  #define VCMSG_ID_CORE_CLOCK     4
  37
  38 +#define SOC_BCM2835            BIT(0)
  39 +#define SOC_ALL                        (SOC_BCM2835)
  40 +
  41  /*
  42   * Names of clocks used within the driver that need to be replaced
  43   * with an external parent's name.  This array is in the order that
  44 @@ -333,6 +336,10 @@ struct bcm2835_cprman {
  45         struct clk_hw_onecell_data onecell;
  46  };
  47
  48 +struct cprman_plat_data {
  49 +       unsigned int soc;
  50 +};
  51 +
  52  static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
  53  {
  54         writel(CM_PASSWORD | val, cprman->regs + reg);
  55 @@ -1528,22 +1535,28 @@ typedef struct clk_hw *(*bcm2835_clk_reg
  56                                                const void *data);
  57  struct bcm2835_clk_desc {
  58         bcm2835_clk_register clk_register;
  59 +       unsigned int supported;
  60         const void *data;
  61  };
  62
  63  /* assignment helper macros for different clock types */
  64 -#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
  65 -                           .data = __VA_ARGS__ }
  66 -#define REGISTER_PLL(...)      _REGISTER(&bcm2835_register_pll,        \
  67 +#define _REGISTER(f, s, ...) { .clk_register = (bcm2835_clk_register)f, \
  68 +                              .supported = s,                          \
  69 +                              .data = __VA_ARGS__ }
  70 +#define REGISTER_PLL(s, ...)   _REGISTER(&bcm2835_register_pll,        \
  71 +                                         s,                            \
  72                                           &(struct bcm2835_pll_data)    \
  73                                           {__VA_ARGS__})
  74 -#define REGISTER_PLL_DIV(...)  _REGISTER(&bcm2835_register_pll_divider, \
  75 -                                         &(struct bcm2835_pll_divider_data) \
  76 -                                         {__VA_ARGS__})
  77 -#define REGISTER_CLK(...)      _REGISTER(&bcm2835_register_clock,      \
  78 +#define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \
  79 +                                          s,                             \
  80 +                                          &(struct bcm2835_pll_divider_data) \
  81 +                                          {__VA_ARGS__})
  82 +#define REGISTER_CLK(s, ...)   _REGISTER(&bcm2835_register_clock,      \
  83 +                                         s,                            \
  84                                           &(struct bcm2835_clock_data)  \
  85                                           {__VA_ARGS__})
  86 -#define REGISTER_GATE(...)     _REGISTER(&bcm2835_register_gate,       \
  87 +#define REGISTER_GATE(s, ...)  _REGISTER(&bcm2835_register_gate,       \
  88 +                                         s,                            \
  89                                           &(struct bcm2835_gate_data)   \
  90                                           {__VA_ARGS__})
  91
  92 @@ -1557,7 +1570,8 @@ static const char *const bcm2835_clock_o
  93         "testdebug1"
  94  };
  95
  96 -#define REGISTER_OSC_CLK(...)  REGISTER_CLK(                           \
  97 +#define REGISTER_OSC_CLK(s, ...)       REGISTER_CLK(                   \
  98 +       s,                                                              \
  99         .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),       \
 100         .parents = bcm2835_clock_osc_parents,                           \
 101         __VA_ARGS__)
 102 @@ -1574,7 +1588,8 @@ static const char *const bcm2835_clock_p
 103         "pllh_aux",
 104  };
 105
 106 -#define REGISTER_PER_CLK(...)  REGISTER_CLK(                           \
 107 +#define REGISTER_PER_CLK(s, ...)       REGISTER_CLK(                   \
 108 +       s,                                                              \
 109         .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),       \
 110         .parents = bcm2835_clock_per_parents,                           \
 111         __VA_ARGS__)
 112 @@ -1599,7 +1614,8 @@ static const char *const bcm2835_pcm_per
 113         "-",
 114  };
 115
 116 -#define REGISTER_PCM_CLK(...)  REGISTER_CLK(                           \
 117 +#define REGISTER_PCM_CLK(s, ...)       REGISTER_CLK(                   \
 118 +       s,                                                              \
 119         .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents),         \
 120         .parents = bcm2835_pcm_per_parents,                             \
 121         __VA_ARGS__)
 122 @@ -1618,7 +1634,8 @@ static const char *const bcm2835_clock_v
 123         "pllc_core2",
 124  };
 125
 126 -#define REGISTER_VPU_CLK(...)  REGISTER_CLK(                           \
 127 +#define REGISTER_VPU_CLK(s, ...)       REGISTER_CLK(                   \
 128 +       s,                                                              \
 129         .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),       \
 130         .parents = bcm2835_clock_vpu_parents,                           \
 131         __VA_ARGS__)
 132 @@ -1654,12 +1671,14 @@ static const char *const bcm2835_clock_d
 133         "dsi1_byte_inv",
 134  };
 135
 136 -#define REGISTER_DSI0_CLK(...) REGISTER_CLK(                           \
 137 +#define REGISTER_DSI0_CLK(s, ...)      REGISTER_CLK(                   \
 138 +       s,                                                              \
 139         .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents),      \
 140         .parents = bcm2835_clock_dsi0_parents,                          \
 141         __VA_ARGS__)
 142
 143 -#define REGISTER_DSI1_CLK(...) REGISTER_CLK(                           \
 144 +#define REGISTER_DSI1_CLK(s, ...)      REGISTER_CLK(                   \
 145 +       s,                                                              \
 146         .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents),      \
 147         .parents = bcm2835_clock_dsi1_parents,                          \
 148         __VA_ARGS__)
 149 @@ -1679,6 +1698,7 @@ static const struct bcm2835_clk_desc clk
 150          * AUDIO domain is on.
 151          */
 152         [BCM2835_PLLA]          = REGISTER_PLL(
 153 +               SOC_ALL,
 154                 .name = "plla",
 155                 .cm_ctrl_reg = CM_PLLA,
 156                 .a2w_ctrl_reg = A2W_PLLA_CTRL,
 157 @@ -1693,6 +1713,7 @@ static const struct bcm2835_clk_desc clk
 158                 .max_rate = 2400000000u,
 159                 .max_fb_rate = BCM2835_MAX_FB_RATE),
 160         [BCM2835_PLLA_CORE]     = REGISTER_PLL_DIV(
 161 +               SOC_ALL,
 162                 .name = "plla_core",
 163                 .source_pll = "plla",
 164                 .cm_reg = CM_PLLA,
 165 @@ -1702,6 +1723,7 @@ static const struct bcm2835_clk_desc clk
 166                 .fixed_divider = 1,
 167                 .flags = CLK_SET_RATE_PARENT),
 168         [BCM2835_PLLA_PER]      = REGISTER_PLL_DIV(
 169 +               SOC_ALL,
 170                 .name = "plla_per",
 171                 .source_pll = "plla",
 172                 .cm_reg = CM_PLLA,
 173 @@ -1711,6 +1733,7 @@ static const struct bcm2835_clk_desc clk
 174                 .fixed_divider = 1,
 175                 .flags = CLK_SET_RATE_PARENT),
 176         [BCM2835_PLLA_DSI0]     = REGISTER_PLL_DIV(
 177 +               SOC_ALL,
 178                 .name = "plla_dsi0",
 179                 .source_pll = "plla",
 180                 .cm_reg = CM_PLLA,
 181 @@ -1719,6 +1742,7 @@ static const struct bcm2835_clk_desc clk
 182                 .hold_mask = CM_PLLA_HOLDDSI0,
 183                 .fixed_divider = 1),
 184         [BCM2835_PLLA_CCP2]     = REGISTER_PLL_DIV(
 185 +               SOC_ALL,
 186                 .name = "plla_ccp2",
 187                 .source_pll = "plla",
 188                 .cm_reg = CM_PLLA,
 189 @@ -1730,6 +1754,7 @@ static const struct bcm2835_clk_desc clk
 190
 191         /* PLLB is used for the ARM's clock. */
 192         [BCM2835_PLLB]          = REGISTER_PLL(
 193 +               SOC_ALL,
 194                 .name = "pllb",
 195                 .cm_ctrl_reg = CM_PLLB,
 196                 .a2w_ctrl_reg = A2W_PLLB_CTRL,
 197 @@ -1744,6 +1769,7 @@ static const struct bcm2835_clk_desc clk
 198                 .max_rate = 3000000000u,
 199                 .max_fb_rate = BCM2835_MAX_FB_RATE),
 200         [BCM2835_PLLB_ARM]      = REGISTER_PLL_DIV(
 201 +               SOC_ALL,
 202                 .name = "pllb_arm",
 203                 .source_pll = "pllb",
 204                 .cm_reg = CM_PLLB,
 205 @@ -1760,6 +1786,7 @@ static const struct bcm2835_clk_desc clk
 206          * AUDIO domain is on.
 207          */
 208         [BCM2835_PLLC]          = REGISTER_PLL(
 209 +               SOC_ALL,
 210                 .name = "pllc",
 211                 .cm_ctrl_reg = CM_PLLC,
 212                 .a2w_ctrl_reg = A2W_PLLC_CTRL,
 213 @@ -1774,6 +1801,7 @@ static const struct bcm2835_clk_desc clk
 214                 .max_rate = 3000000000u,
 215                 .max_fb_rate = BCM2835_MAX_FB_RATE),
 216         [BCM2835_PLLC_CORE0]    = REGISTER_PLL_DIV(
 217 +               SOC_ALL,
 218                 .name = "pllc_core0",
 219                 .source_pll = "pllc",
 220                 .cm_reg = CM_PLLC,
 221 @@ -1783,6 +1811,7 @@ static const struct bcm2835_clk_desc clk
 222                 .fixed_divider = 1,
 223                 .flags = CLK_SET_RATE_PARENT),
 224         [BCM2835_PLLC_CORE1]    = REGISTER_PLL_DIV(
 225 +               SOC_ALL,
 226                 .name = "pllc_core1",
 227                 .source_pll = "pllc",
 228                 .cm_reg = CM_PLLC,
 229 @@ -1792,6 +1821,7 @@ static const struct bcm2835_clk_desc clk
 230                 .fixed_divider = 1,
 231                 .flags = CLK_SET_RATE_PARENT),
 232         [BCM2835_PLLC_CORE2]    = REGISTER_PLL_DIV(
 233 +               SOC_ALL,
 234                 .name = "pllc_core2",
 235                 .source_pll = "pllc",
 236                 .cm_reg = CM_PLLC,
 237 @@ -1801,6 +1831,7 @@ static const struct bcm2835_clk_desc clk
 238                 .fixed_divider = 1,
 239                 .flags = CLK_SET_RATE_PARENT),
 240         [BCM2835_PLLC_PER]      = REGISTER_PLL_DIV(
 241 +               SOC_ALL,
 242                 .name = "pllc_per",
 243                 .source_pll = "pllc",
 244                 .cm_reg = CM_PLLC,
 245 @@ -1817,6 +1848,7 @@ static const struct bcm2835_clk_desc clk
 246          * AUDIO domain is on.
 247          */
 248         [BCM2835_PLLD]          = REGISTER_PLL(
 249 +               SOC_ALL,
 250                 .name = "plld",
 251                 .cm_ctrl_reg = CM_PLLD,
 252                 .a2w_ctrl_reg = A2W_PLLD_CTRL,
 253 @@ -1831,6 +1863,7 @@ static const struct bcm2835_clk_desc clk
 254                 .max_rate = 2400000000u,
 255                 .max_fb_rate = BCM2835_MAX_FB_RATE),
 256         [BCM2835_PLLD_CORE]     = REGISTER_PLL_DIV(
 257 +               SOC_ALL,
 258                 .name = "plld_core",
 259                 .source_pll = "plld",
 260                 .cm_reg = CM_PLLD,
 261 @@ -1840,6 +1873,7 @@ static const struct bcm2835_clk_desc clk
 262                 .fixed_divider = 1,
 263                 .flags = CLK_SET_RATE_PARENT),
 264         [BCM2835_PLLD_PER]      = REGISTER_PLL_DIV(
 265 +               SOC_ALL,
 266                 .name = "plld_per",
 267                 .source_pll = "plld",
 268                 .cm_reg = CM_PLLD,
 269 @@ -1849,6 +1883,7 @@ static const struct bcm2835_clk_desc clk
 270                 .fixed_divider = 1,
 271                 .flags = CLK_SET_RATE_PARENT),
 272         [BCM2835_PLLD_DSI0]     = REGISTER_PLL_DIV(
 273 +               SOC_ALL,
 274                 .name = "plld_dsi0",
 275                 .source_pll = "plld",
 276                 .cm_reg = CM_PLLD,
 277 @@ -1857,6 +1892,7 @@ static const struct bcm2835_clk_desc clk
 278                 .hold_mask = CM_PLLD_HOLDDSI0,
 279                 .fixed_divider = 1),
 280         [BCM2835_PLLD_DSI1]     = REGISTER_PLL_DIV(
 281 +               SOC_ALL,
 282                 .name = "plld_dsi1",
 283                 .source_pll = "plld",
 284                 .cm_reg = CM_PLLD,
 285 @@ -1872,6 +1908,7 @@ static const struct bcm2835_clk_desc clk
 286          * It is in the HDMI power domain.
 287          */
 288         [BCM2835_PLLH]          = REGISTER_PLL(
 289 +               SOC_BCM2835,
 290                 "pllh",
 291                 .cm_ctrl_reg = CM_PLLH,
 292                 .a2w_ctrl_reg = A2W_PLLH_CTRL,
 293 @@ -1886,6 +1923,7 @@ static const struct bcm2835_clk_desc clk
 294                 .max_rate = 3000000000u,
 295                 .max_fb_rate = BCM2835_MAX_FB_RATE),
 296         [BCM2835_PLLH_RCAL]     = REGISTER_PLL_DIV(
 297 +               SOC_BCM2835,
 298                 .name = "pllh_rcal",
 299                 .source_pll = "pllh",
 300                 .cm_reg = CM_PLLH,
 301 @@ -1895,6 +1933,7 @@ static const struct bcm2835_clk_desc clk
 302                 .fixed_divider = 10,
 303                 .flags = CLK_SET_RATE_PARENT),
 304         [BCM2835_PLLH_AUX]      = REGISTER_PLL_DIV(
 305 +               SOC_BCM2835,
 306                 .name = "pllh_aux",
 307                 .source_pll = "pllh",
 308                 .cm_reg = CM_PLLH,
 309 @@ -1904,6 +1943,7 @@ static const struct bcm2835_clk_desc clk
 310                 .fixed_divider = 1,
 311                 .flags = CLK_SET_RATE_PARENT),
 312         [BCM2835_PLLH_PIX]      = REGISTER_PLL_DIV(
 313 +               SOC_BCM2835,
 314                 .name = "pllh_pix",
 315                 .source_pll = "pllh",
 316                 .cm_reg = CM_PLLH,
 317 @@ -1919,6 +1959,7 @@ static const struct bcm2835_clk_desc clk
 318
 319         /* One Time Programmable Memory clock.  Maximum 10Mhz. */
 320         [BCM2835_CLOCK_OTP]     = REGISTER_OSC_CLK(
 321 +               SOC_ALL,
 322                 .name = "otp",
 323                 .ctl_reg = CM_OTPCTL,
 324                 .div_reg = CM_OTPDIV,
 325 @@ -1930,6 +1971,7 @@ static const struct bcm2835_clk_desc clk
 326          * bythe watchdog timer and the camera pulse generator.
 327          */
 328         [BCM2835_CLOCK_TIMER]   = REGISTER_OSC_CLK(
 329 +               SOC_ALL,
 330                 .name = "timer",
 331                 .ctl_reg = CM_TIMERCTL,
 332                 .div_reg = CM_TIMERDIV,
 333 @@ -1940,12 +1982,14 @@ static const struct bcm2835_clk_desc clk
 334          * Generally run at 2Mhz, max 5Mhz.
 335          */
 336         [BCM2835_CLOCK_TSENS]   = REGISTER_OSC_CLK(
 337 +               SOC_ALL,
 338                 .name = "tsens",
 339                 .ctl_reg = CM_TSENSCTL,
 340                 .div_reg = CM_TSENSDIV,
 341                 .int_bits = 5,
 342                 .frac_bits = 0),
 343         [BCM2835_CLOCK_TEC]     = REGISTER_OSC_CLK(
 344 +               SOC_ALL,
 345                 .name = "tec",
 346                 .ctl_reg = CM_TECCTL,
 347                 .div_reg = CM_TECDIV,
 348 @@ -1954,6 +1998,7 @@ static const struct bcm2835_clk_desc clk
 349
 350         /* clocks with vpu parent mux */
 351         [BCM2835_CLOCK_H264]    = REGISTER_VPU_CLK(
 352 +               SOC_ALL,
 353                 .name = "h264",
 354                 .ctl_reg = CM_H264CTL,
 355                 .div_reg = CM_H264DIV,
 356 @@ -1961,6 +2006,7 @@ static const struct bcm2835_clk_desc clk
 357                 .frac_bits = 8,
 358                 .tcnt_mux = 1),
 359         [BCM2835_CLOCK_ISP]     = REGISTER_VPU_CLK(
 360 +               SOC_ALL,
 361                 .name = "isp",
 362                 .ctl_reg = CM_ISPCTL,
 363                 .div_reg = CM_ISPDIV,
 364 @@ -1973,6 +2019,7 @@ static const struct bcm2835_clk_desc clk
 365          * in the SDRAM controller can't be used.
 366          */
 367         [BCM2835_CLOCK_SDRAM]   = REGISTER_VPU_CLK(
 368 +               SOC_ALL,
 369                 .name = "sdram",
 370                 .ctl_reg = CM_SDCCTL,
 371                 .div_reg = CM_SDCDIV,
 372 @@ -1980,6 +2027,7 @@ static const struct bcm2835_clk_desc clk
 373                 .frac_bits = 0,
 374                 .tcnt_mux = 3),
 375         [BCM2835_CLOCK_V3D]     = REGISTER_VPU_CLK(
 376 +               SOC_ALL,
 377                 .name = "v3d",
 378                 .ctl_reg = CM_V3DCTL,
 379                 .div_reg = CM_V3DDIV,
 380 @@ -1993,6 +2041,7 @@ static const struct bcm2835_clk_desc clk
 381          * in various hardware documentation.
 382          */
 383         [BCM2835_CLOCK_VPU]     = REGISTER_VPU_CLK(
 384 +               SOC_ALL,
 385                 .name = "vpu",
 386                 .ctl_reg = CM_VPUCTL,
 387                 .div_reg = CM_VPUDIV,
 388 @@ -2004,6 +2053,7 @@ static const struct bcm2835_clk_desc clk
 389
 390         /* clocks with per parent mux */
 391         [BCM2835_CLOCK_AVEO]    = REGISTER_PER_CLK(
 392 +               SOC_ALL,
 393                 .name = "aveo",
 394                 .ctl_reg = CM_AVEOCTL,
 395                 .div_reg = CM_AVEODIV,
 396 @@ -2011,6 +2061,7 @@ static const struct bcm2835_clk_desc clk
 397                 .frac_bits = 0,
 398                 .tcnt_mux = 38),
 399         [BCM2835_CLOCK_CAM0]    = REGISTER_PER_CLK(
 400 +               SOC_ALL,
 401                 .name = "cam0",
 402                 .ctl_reg = CM_CAM0CTL,
 403                 .div_reg = CM_CAM0DIV,
 404 @@ -2018,6 +2069,7 @@ static const struct bcm2835_clk_desc clk
 405                 .frac_bits = 8,
 406                 .tcnt_mux = 14),
 407         [BCM2835_CLOCK_CAM1]    = REGISTER_PER_CLK(
 408 +               SOC_ALL,
 409                 .name = "cam1",
 410                 .ctl_reg = CM_CAM1CTL,
 411                 .div_reg = CM_CAM1DIV,
 412 @@ -2025,12 +2077,14 @@ static const struct bcm2835_clk_desc clk
 413                 .frac_bits = 8,
 414                 .tcnt_mux = 15),
 415         [BCM2835_CLOCK_DFT]     = REGISTER_PER_CLK(
 416 +               SOC_ALL,
 417                 .name = "dft",
 418                 .ctl_reg = CM_DFTCTL,
 419                 .div_reg = CM_DFTDIV,
 420                 .int_bits = 5,
 421                 .frac_bits = 0),
 422         [BCM2835_CLOCK_DPI]     = REGISTER_PER_CLK(
 423 +               SOC_ALL,
 424                 .name = "dpi",
 425                 .ctl_reg = CM_DPICTL,
 426                 .div_reg = CM_DPIDIV,
 427 @@ -2040,6 +2094,7 @@ static const struct bcm2835_clk_desc clk
 428
 429         /* Arasan EMMC clock */
 430         [BCM2835_CLOCK_EMMC]    = REGISTER_PER_CLK(
 431 +               SOC_ALL,
 432                 .name = "emmc",
 433                 .ctl_reg = CM_EMMCCTL,
 434                 .div_reg = CM_EMMCDIV,
 435 @@ -2049,6 +2104,7 @@ static const struct bcm2835_clk_desc clk
 436
 437         /* General purpose (GPIO) clocks */
 438         [BCM2835_CLOCK_GP0]     = REGISTER_PER_CLK(
 439 +               SOC_ALL,
 440                 .name = "gp0",
 441                 .ctl_reg = CM_GP0CTL,
 442                 .div_reg = CM_GP0DIV,
 443 @@ -2057,6 +2113,7 @@ static const struct bcm2835_clk_desc clk
 444                 .is_mash_clock = true,
 445                 .tcnt_mux = 20),
 446         [BCM2835_CLOCK_GP1]     = REGISTER_PER_CLK(
 447 +               SOC_ALL,
 448                 .name = "gp1",
 449                 .ctl_reg = CM_GP1CTL,
 450                 .div_reg = CM_GP1DIV,
 451 @@ -2066,6 +2123,7 @@ static const struct bcm2835_clk_desc clk
 452                 .is_mash_clock = true,
 453                 .tcnt_mux = 21),
 454         [BCM2835_CLOCK_GP2]     = REGISTER_PER_CLK(
 455 +               SOC_ALL,
 456                 .name = "gp2",
 457                 .ctl_reg = CM_GP2CTL,
 458                 .div_reg = CM_GP2DIV,
 459 @@ -2075,6 +2133,7 @@ static const struct bcm2835_clk_desc clk
 460
 461         /* HDMI state machine */
 462         [BCM2835_CLOCK_HSM]     = REGISTER_PER_CLK(
 463 +               SOC_ALL,
 464                 .name = "hsm",
 465                 .ctl_reg = CM_HSMCTL,
 466                 .div_reg = CM_HSMDIV,
 467 @@ -2082,6 +2141,7 @@ static const struct bcm2835_clk_desc clk
 468                 .frac_bits = 8,
 469                 .tcnt_mux = 22),
 470         [BCM2835_CLOCK_PCM]     = REGISTER_PCM_CLK(
 471 +               SOC_ALL,
 472                 .name = "pcm",
 473                 .ctl_reg = CM_PCMCTL,
 474                 .div_reg = CM_PCMDIV,
 475 @@ -2091,6 +2151,7 @@ static const struct bcm2835_clk_desc clk
 476                 .low_jitter = true,
 477                 .tcnt_mux = 23),
 478         [BCM2835_CLOCK_PWM]     = REGISTER_PER_CLK(
 479 +               SOC_ALL,
 480                 .name = "pwm",
 481                 .ctl_reg = CM_PWMCTL,
 482                 .div_reg = CM_PWMDIV,
 483 @@ -2099,6 +2160,7 @@ static const struct bcm2835_clk_desc clk
 484                 .is_mash_clock = true,
 485                 .tcnt_mux = 24),
 486         [BCM2835_CLOCK_SLIM]    = REGISTER_PER_CLK(
 487 +               SOC_ALL,
 488                 .name = "slim",
 489                 .ctl_reg = CM_SLIMCTL,
 490                 .div_reg = CM_SLIMDIV,
 491 @@ -2107,6 +2169,7 @@ static const struct bcm2835_clk_desc clk
 492                 .is_mash_clock = true,
 493                 .tcnt_mux = 25),
 494         [BCM2835_CLOCK_SMI]     = REGISTER_PER_CLK(
 495 +               SOC_ALL,
 496                 .name = "smi",
 497                 .ctl_reg = CM_SMICTL,
 498                 .div_reg = CM_SMIDIV,
 499 @@ -2114,6 +2177,7 @@ static const struct bcm2835_clk_desc clk
 500                 .frac_bits = 8,
 501                 .tcnt_mux = 27),
 502         [BCM2835_CLOCK_UART]    = REGISTER_PER_CLK(
 503 +               SOC_ALL,
 504                 .name = "uart",
 505                 .ctl_reg = CM_UARTCTL,
 506                 .div_reg = CM_UARTDIV,
 507 @@ -2123,6 +2187,7 @@ static const struct bcm2835_clk_desc clk
 508
 509         /* TV encoder clock.  Only operating frequency is 108Mhz.  */
 510         [BCM2835_CLOCK_VEC]     = REGISTER_PER_CLK(
 511 +               SOC_ALL,
 512                 .name = "vec",
 513                 .ctl_reg = CM_VECCTL,
 514                 .div_reg = CM_VECDIV,
 515 @@ -2137,6 +2202,7 @@ static const struct bcm2835_clk_desc clk
 516
 517         /* dsi clocks */
 518         [BCM2835_CLOCK_DSI0E]   = REGISTER_PER_CLK(
 519 +               SOC_ALL,
 520                 .name = "dsi0e",
 521                 .ctl_reg = CM_DSI0ECTL,
 522                 .div_reg = CM_DSI0EDIV,
 523 @@ -2144,6 +2210,7 @@ static const struct bcm2835_clk_desc clk
 524                 .frac_bits = 8,
 525                 .tcnt_mux = 18),
 526         [BCM2835_CLOCK_DSI1E]   = REGISTER_PER_CLK(
 527 +               SOC_ALL,
 528                 .name = "dsi1e",
 529                 .ctl_reg = CM_DSI1ECTL,
 530                 .div_reg = CM_DSI1EDIV,
 531 @@ -2151,6 +2218,7 @@ static const struct bcm2835_clk_desc clk
 532                 .frac_bits = 8,
 533                 .tcnt_mux = 19),
 534         [BCM2835_CLOCK_DSI0P]   = REGISTER_DSI0_CLK(
 535 +               SOC_ALL,
 536                 .name = "dsi0p",
 537                 .ctl_reg = CM_DSI0PCTL,
 538                 .div_reg = CM_DSI0PDIV,
 539 @@ -2158,6 +2226,7 @@ static const struct bcm2835_clk_desc clk
 540                 .frac_bits = 0,
 541                 .tcnt_mux = 12),
 542         [BCM2835_CLOCK_DSI1P]   = REGISTER_DSI1_CLK(
 543 +               SOC_ALL,
 544                 .name = "dsi1p",
 545                 .ctl_reg = CM_DSI1PCTL,
 546                 .div_reg = CM_DSI1PDIV,
 547 @@ -2174,6 +2243,7 @@ static const struct bcm2835_clk_desc clk
 548          * non-stop vpu clock.
 549          */
 550         [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
 551 +               SOC_ALL,
 552                 .name = "peri_image",
 553                 .parent = "vpu",
 554                 .ctl_reg = CM_PERIICTL),
 555 @@ -2221,11 +2291,16 @@ static int bcm2835_clk_probe(struct plat
 556         struct resource *res;
 557         const struct bcm2835_clk_desc *desc;
 558         const size_t asize = ARRAY_SIZE(clk_desc_array);
 559 +       const struct cprman_plat_data *pdata;
 560         struct device_node *fw_node;
 561         size_t i;
 562         u32 clk_id;
 563         int ret;
 564
 565 +       pdata = of_device_get_match_data(&pdev->dev);
 566 +       if (!pdata)
 567 +               return -ENODEV;
 568 +
 569         cprman = devm_kzalloc(dev,
 570                               struct_size(cprman, onecell.hws, asize),
 571                               GFP_KERNEL);
 572 @@ -2276,8 +2351,10 @@ static int bcm2835_clk_probe(struct plat
 573
 574         for (i = 0; i < asize; i++) {
 575                 desc = &clk_desc_array[i];
 576 -               if (desc->clk_register && desc->data)
 577 +               if (desc->clk_register && desc->data &&
 578 +                   (desc->supported & pdata->soc)) {
 579                         hws[i] = desc->clk_register(cprman, desc->data);
 580 +               }
 581         }
 582
 583         ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
 584 @@ -2295,8 +2372,12 @@ static int bcm2835_clk_probe(struct plat
 585         return 0;
 586  }
 587
 588 +static const struct cprman_plat_data cprman_bcm2835_plat_data = {
 589 +       .soc = SOC_BCM2835,
 590 +};
 591 +
 592  static const struct of_device_id bcm2835_clk_of_match[] = {
 593 -       { .compatible = "brcm,bcm2835-cprman", },
 594 +       { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
 595         {}
 596  };
 597  MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);