git.librecmc.org Git - oweals/openwrt.git/blob

   1 From 4ddd1240c612f39ea9282ec3f705e11bbb114e58 Mon Sep 17 00:00:00 2001
   2 From: Dave Stevenson <dave.stevenson@raspberrypi.org>
   3 Date: Wed, 31 Oct 2018 14:59:22 +0000
   4 Subject: [PATCH 198/782] media: bcm2835-unicam: Driver for CCP2/CSI2 camera
   5  interface
   6
   7 Add driver for the Unicam camera receiver block on
   8 BCM283x processors.
   9
  10 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
  11 ---
  12  drivers/media/platform/Kconfig                |    1 +
  13  drivers/media/platform/Makefile               |    2 +
  14  drivers/media/platform/bcm2835/Kconfig        |   14 +
  15  drivers/media/platform/bcm2835/Makefile       |    3 +
  16  .../media/platform/bcm2835/bcm2835-unicam.c   | 2101 +++++++++++++++++
  17  .../media/platform/bcm2835/vc4-regs-unicam.h  |  266 +++
  18  6 files changed, 2387 insertions(+)
  19  create mode 100644 drivers/media/platform/bcm2835/Kconfig
  20  create mode 100644 drivers/media/platform/bcm2835/Makefile
  21  create mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c
  22  create mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h
  23
  24 --- a/drivers/media/platform/Kconfig
  25 +++ b/drivers/media/platform/Kconfig
  26 @@ -137,6 +137,7 @@ source "drivers/media/platform/am437x/Kc
  27  source "drivers/media/platform/xilinx/Kconfig"
  28  source "drivers/media/platform/rcar-vin/Kconfig"
  29  source "drivers/media/platform/atmel/Kconfig"
  30 +source "drivers/media/platform/bcm2835/Kconfig"
  31
  32  config VIDEO_TI_CAL
  33         tristate "TI CAL (Camera Adaptation Layer) driver"
  34 --- a/drivers/media/platform/Makefile
  35 +++ b/drivers/media/platform/Makefile
  36 @@ -96,3 +96,5 @@ obj-$(CONFIG_VIDEO_QCOM_VENUS)                += qcom/
  37  obj-y                                  += meson/
  38
  39  obj-y                                  += cros-ec-cec/
  40 +
  41 +obj-y                                  += bcm2835/
  42 --- /dev/null
  43 +++ b/drivers/media/platform/bcm2835/Kconfig
  44 @@ -0,0 +1,14 @@
  45 +# Broadcom VideoCore4 V4L2 camera support
  46 +
  47 +config VIDEO_BCM2835_UNICAM
  48 +       tristate "Broadcom BCM2835 Unicam video capture driver"
  49 +       depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
  50 +       depends on ARCH_BCM2835 || COMPILE_TEST
  51 +       select VIDEOBUF2_DMA_CONTIG
  52 +       select V4L2_FWNODE
  53 +       help
  54 +         Say Y here to enable V4L2 subdevice for CSI2 receiver.
  55 +         This is a V4L2 subdevice that interfaces directly to the VC4 peripheral.
  56 +
  57 +          To compile this driver as a module, choose M here. The module
  58 +          will be called bcm2835-unicam.
  59 --- /dev/null
  60 +++ b/drivers/media/platform/bcm2835/Makefile
  61 @@ -0,0 +1,3 @@
  62 +# Makefile for BCM2835 Unicam driver
  63 +
  64 +obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o
  65 --- /dev/null
  66 +++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c
  67 @@ -0,0 +1,2101 @@
  68 +// SPDX-License-Identifier: GPL-2.0-only
  69 +/*
  70 + * BCM2835 Unicam capture Driver
  71 + *
  72 + * Copyright (C) 2017 - Raspberry Pi (Trading) Ltd.
  73 + *
  74 + * Dave Stevenson <dave.stevenson@raspberrypi.org>
  75 + *
  76 + * Based on TI am437x driver by Benoit Parrot and Lad, Prabhakar and
  77 + * TI CAL camera interface driver by Benoit Parrot.
  78 + *
  79 + *
  80 + * There are two camera drivers in the kernel for BCM283x - this one
  81 + * and bcm2835-camera (currently in staging).
  82 + *
  83 + * This driver directly controls the Unicam peripheral - there is no
  84 + * involvement with the VideoCore firmware. Unicam receives CSI-2 or
  85 + * CCP2 data and writes it into SDRAM. The only potential processing options are
  86 + * to repack Bayer data into an alternate format, and applying windowing.
  87 + * The repacking does not shift the data, so could repack V4L2_PIX_FMT_Sxxxx10P
  88 + * to V4L2_PIX_FMT_Sxxxx10, or V4L2_PIX_FMT_Sxxxx12P to V4L2_PIX_FMT_Sxxxx12,
  89 + * but not generically up to V4L2_PIX_FMT_Sxxxx16.
  90 + * Adding support for repacking and windowing may be added later.
  91 + *
  92 + * It should be possible to connect this driver to any sensor with a
  93 + * suitable output interface and V4L2 subdevice driver.
  94 + *
  95 + * bcm2835-camera uses the VideoCore firmware to control the sensor,
  96 + * Unicam, ISP, and all tuner control loops. Fully processed frames are
  97 + * delivered to the driver by the firmware. It only has sensor drivers
  98 + * for Omnivision OV5647, and Sony IMX219 sensors.
  99 + *
 100 + * The two drivers are mutually exclusive for the same Unicam instance.
 101 + * The VideoCore firmware checks the device tree configuration during boot.
 102 + * If it finds device tree nodes called csi0 or csi1 it will block the
 103 + * firmware from accessing the peripheral, and bcm2835-camera will
 104 + * not be able to stream data.
 105 + *
 106 + *
 107 + * This program is free software; you may redistribute it and/or modify
 108 + * it under the terms of the GNU General Public License as published by
 109 + * the Free Software Foundation; version 2 of the License.
 110 + *
 111 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 112 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 113 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 114 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 115 + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 116 + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 117 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 118 + * SOFTWARE.
 119 + */
 120 +
 121 +#include <linux/clk.h>
 122 +#include <linux/delay.h>
 123 +#include <linux/device.h>
 124 +#include <linux/err.h>
 125 +#include <linux/init.h>
 126 +#include <linux/interrupt.h>
 127 +#include <linux/io.h>
 128 +#include <linux/module.h>
 129 +#include <linux/of_device.h>
 130 +#include <linux/of_graph.h>
 131 +#include <linux/pinctrl/consumer.h>
 132 +#include <linux/platform_device.h>
 133 +#include <linux/pm_runtime.h>
 134 +#include <linux/slab.h>
 135 +#include <linux/uaccess.h>
 136 +#include <linux/videodev2.h>
 137 +
 138 +#include <media/v4l2-common.h>
 139 +#include <media/v4l2-ctrls.h>
 140 +#include <media/v4l2-dev.h>
 141 +#include <media/v4l2-device.h>
 142 +#include <media/v4l2-dv-timings.h>
 143 +#include <media/v4l2-event.h>
 144 +#include <media/v4l2-ioctl.h>
 145 +#include <media/v4l2-fwnode.h>
 146 +#include <media/videobuf2-dma-contig.h>
 147 +
 148 +#include "vc4-regs-unicam.h"
 149 +
 150 +#define UNICAM_MODULE_NAME     "unicam"
 151 +#define UNICAM_VERSION         "0.1.0"
 152 +
 153 +static int debug;
 154 +module_param(debug, int, 0644);
 155 +MODULE_PARM_DESC(debug, "Debug level 0-3");
 156 +
 157 +#define unicam_dbg(level, dev, fmt, arg...)    \
 158 +               v4l2_dbg(level, debug, &(dev)->v4l2_dev, fmt, ##arg)
 159 +#define unicam_info(dev, fmt, arg...)  \
 160 +               v4l2_info(&(dev)->v4l2_dev, fmt, ##arg)
 161 +#define unicam_err(dev, fmt, arg...)   \
 162 +               v4l2_err(&(dev)->v4l2_dev, fmt, ##arg)
 163 +
 164 +/*
 165 + * Stride is a 16 bit register, but also has to be a multiple of 16.
 166 + */
 167 +#define BPL_ALIGNMENT          16
 168 +#define MAX_BYTESPERLINE       ((1 << 16) - BPL_ALIGNMENT)
 169 +/*
 170 + * Max width is therefore determined by the max stride divided by
 171 + * the number of bits per pixel. Take 32bpp as a
 172 + * worst case.
 173 + * No imposed limit on the height, so adopt a square image for want
 174 + * of anything better.
 175 + */
 176 +#define MAX_WIDTH      (MAX_BYTESPERLINE / 4)
 177 +#define MAX_HEIGHT     MAX_WIDTH
 178 +/* Define a nominal minimum image size */
 179 +#define MIN_WIDTH      16
 180 +#define MIN_HEIGHT     16
 181 +/*
 182 + * Whilst Unicam doesn't require any additional padding on the image
 183 + * height, various other parts of the BCM283x frameworks require a multiple
 184 + * of 16.
 185 + * Seeing as image buffers are significantly larger than this extra
 186 + * padding, add it in order to simplify integration.
 187 + */
 188 +#define HEIGHT_ALIGNMENT       16
 189 +
 190 +/*
 191 + * struct unicam_fmt - Unicam media bus format information
 192 + * @pixelformat: V4L2 pixel format FCC identifier.
 193 + * @code: V4L2 media bus format code.
 194 + * @depth: Bits per pixel (when stored in memory).
 195 + * @csi_dt: CSI data type.
 196 + */
 197 +struct unicam_fmt {
 198 +       u32     fourcc;
 199 +       u32     code;
 200 +       u8      depth;
 201 +       u8      csi_dt;
 202 +};
 203 +
 204 +static const struct unicam_fmt formats[] = {
 205 +       /* YUV Formats */
 206 +       {
 207 +               .fourcc         = V4L2_PIX_FMT_YUYV,
 208 +               .code           = MEDIA_BUS_FMT_YUYV8_2X8,
 209 +               .depth          = 16,
 210 +               .csi_dt         = 0x1e,
 211 +       }, {
 212 +               .fourcc         = V4L2_PIX_FMT_UYVY,
 213 +               .code           = MEDIA_BUS_FMT_UYVY8_2X8,
 214 +               .depth          = 16,
 215 +               .csi_dt         = 0x1e,
 216 +       }, {
 217 +               .fourcc         = V4L2_PIX_FMT_YVYU,
 218 +               .code           = MEDIA_BUS_FMT_YVYU8_2X8,
 219 +               .depth          = 16,
 220 +               .csi_dt         = 0x1e,
 221 +       }, {
 222 +               .fourcc         = V4L2_PIX_FMT_VYUY,
 223 +               .code           = MEDIA_BUS_FMT_VYUY8_2X8,
 224 +               .depth          = 16,
 225 +               .csi_dt         = 0x1e,
 226 +       }, {
 227 +               .fourcc         = V4L2_PIX_FMT_YUYV,
 228 +               .code           = MEDIA_BUS_FMT_YUYV8_1X16,
 229 +               .depth          = 16,
 230 +               .csi_dt         = 0x1e,
 231 +       }, {
 232 +               .fourcc         = V4L2_PIX_FMT_UYVY,
 233 +               .code           = MEDIA_BUS_FMT_UYVY8_1X16,
 234 +               .depth          = 16,
 235 +               .csi_dt         = 0x1e,
 236 +       }, {
 237 +               .fourcc         = V4L2_PIX_FMT_YVYU,
 238 +               .code           = MEDIA_BUS_FMT_YVYU8_1X16,
 239 +               .depth          = 16,
 240 +               .csi_dt         = 0x1e,
 241 +       }, {
 242 +               .fourcc         = V4L2_PIX_FMT_VYUY,
 243 +               .code           = MEDIA_BUS_FMT_VYUY8_1X16,
 244 +               .depth          = 16,
 245 +               .csi_dt         = 0x1e,
 246 +       }, {
 247 +       /* RGB Formats */
 248 +               .fourcc         = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */
 249 +               .code           = MEDIA_BUS_FMT_RGB565_2X8_LE,
 250 +               .depth          = 16,
 251 +               .csi_dt         = 0x22,
 252 +       }, {
 253 +               .fourcc         = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */
 254 +               .code           = MEDIA_BUS_FMT_RGB565_2X8_BE,
 255 +               .depth          = 16,
 256 +               .csi_dt         = 0x22
 257 +       }, {
 258 +               .fourcc         = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */
 259 +               .code           = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
 260 +               .depth          = 16,
 261 +               .csi_dt         = 0x21,
 262 +       }, {
 263 +               .fourcc         = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */
 264 +               .code           = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
 265 +               .depth          = 16,
 266 +               .csi_dt         = 0x21,
 267 +       }, {
 268 +               .fourcc         = V4L2_PIX_FMT_RGB24, /* rgb */
 269 +               .code           = MEDIA_BUS_FMT_RGB888_1X24,
 270 +               .depth          = 24,
 271 +               .csi_dt         = 0x24,
 272 +       }, {
 273 +               .fourcc         = V4L2_PIX_FMT_BGR24, /* bgr */
 274 +               .code           = MEDIA_BUS_FMT_BGR888_1X24,
 275 +               .depth          = 24,
 276 +               .csi_dt         = 0x24,
 277 +       }, {
 278 +               .fourcc         = V4L2_PIX_FMT_RGB32, /* argb */
 279 +               .code           = MEDIA_BUS_FMT_ARGB8888_1X32,
 280 +               .depth          = 32,
 281 +               .csi_dt         = 0x0,
 282 +       }, {
 283 +       /* Bayer Formats */
 284 +               .fourcc         = V4L2_PIX_FMT_SBGGR8,
 285 +               .code           = MEDIA_BUS_FMT_SBGGR8_1X8,
 286 +               .depth          = 8,
 287 +               .csi_dt         = 0x2a,
 288 +       }, {
 289 +               .fourcc         = V4L2_PIX_FMT_SGBRG8,
 290 +               .code           = MEDIA_BUS_FMT_SGBRG8_1X8,
 291 +               .depth          = 8,
 292 +               .csi_dt         = 0x2a,
 293 +       }, {
 294 +               .fourcc         = V4L2_PIX_FMT_SGRBG8,
 295 +               .code           = MEDIA_BUS_FMT_SGRBG8_1X8,
 296 +               .depth          = 8,
 297 +               .csi_dt         = 0x2a,
 298 +       }, {
 299 +               .fourcc         = V4L2_PIX_FMT_SRGGB8,
 300 +               .code           = MEDIA_BUS_FMT_SRGGB8_1X8,
 301 +               .depth          = 8,
 302 +               .csi_dt         = 0x2a,
 303 +       }, {
 304 +               .fourcc         = V4L2_PIX_FMT_SBGGR10P,
 305 +               .code           = MEDIA_BUS_FMT_SBGGR10_1X10,
 306 +               .depth          = 10,
 307 +               .csi_dt         = 0x2b,
 308 +       }, {
 309 +               .fourcc         = V4L2_PIX_FMT_SGBRG10P,
 310 +               .code           = MEDIA_BUS_FMT_SGBRG10_1X10,
 311 +               .depth          = 10,
 312 +               .csi_dt         = 0x2b,
 313 +       }, {
 314 +               .fourcc         = V4L2_PIX_FMT_SGRBG10P,
 315 +               .code           = MEDIA_BUS_FMT_SGRBG10_1X10,
 316 +               .depth          = 10,
 317 +               .csi_dt         = 0x2b,
 318 +       }, {
 319 +               .fourcc         = V4L2_PIX_FMT_SRGGB10P,
 320 +               .code           = MEDIA_BUS_FMT_SRGGB10_1X10,
 321 +               .depth          = 10,
 322 +               .csi_dt         = 0x2b,
 323 +       }, {
 324 +               .fourcc         = V4L2_PIX_FMT_SBGGR12P,
 325 +               .code           = MEDIA_BUS_FMT_SBGGR12_1X12,
 326 +               .depth          = 12,
 327 +               .csi_dt         = 0x2c,
 328 +       }, {
 329 +               .fourcc         = V4L2_PIX_FMT_SGBRG12P,
 330 +               .code           = MEDIA_BUS_FMT_SGBRG12_1X12,
 331 +               .depth          = 12,
 332 +               .csi_dt         = 0x2c,
 333 +       }, {
 334 +               .fourcc         = V4L2_PIX_FMT_SGRBG12P,
 335 +               .code           = MEDIA_BUS_FMT_SGRBG12_1X12,
 336 +               .depth          = 12,
 337 +               .csi_dt         = 0x2c,
 338 +       }, {
 339 +               .fourcc         = V4L2_PIX_FMT_SRGGB12P,
 340 +               .code           = MEDIA_BUS_FMT_SRGGB12_1X12,
 341 +               .depth          = 12,
 342 +               .csi_dt         = 0x2c,
 343 +       },
 344 +       /*
 345 +        * 14 and 16 bit Bayer formats could be supported, but there are no V4L2
 346 +        * defines for 14bit packed Bayer, and no CSI2 data_type for raw 16.
 347 +        */
 348 +};
 349 +
 350 +struct unicam_dmaqueue {
 351 +       struct list_head        active;
 352 +};
 353 +
 354 +struct unicam_buffer {
 355 +       struct vb2_v4l2_buffer vb;
 356 +       struct list_head list;
 357 +};
 358 +
 359 +struct unicam_cfg {
 360 +       /* peripheral base address */
 361 +       void __iomem *base;
 362 +       /* clock gating base address */
 363 +       void __iomem *clk_gate_base;
 364 +};
 365 +
 366 +#define MAX_POSSIBLE_PIX_FMTS (ARRAY_SIZE(formats))
 367 +
 368 +struct unicam_device {
 369 +       /* V4l2 specific parameters */
 370 +       /* Identifies video device for this channel */
 371 +       struct video_device video_dev;
 372 +       struct v4l2_ctrl_handler ctrl_handler;
 373 +
 374 +       struct v4l2_fwnode_endpoint endpoint;
 375 +
 376 +       struct v4l2_async_subdev asd;
 377 +
 378 +       /* unicam cfg */
 379 +       struct unicam_cfg cfg;
 380 +       /* clock handle */
 381 +       struct clk *clock;
 382 +       /* V4l2 device */
 383 +       struct v4l2_device v4l2_dev;
 384 +       /* parent device */
 385 +       struct platform_device *pdev;
 386 +       /* subdevice async Notifier */
 387 +       struct v4l2_async_notifier notifier;
 388 +       unsigned int sequence;
 389 +
 390 +       /* ptr to  sub device */
 391 +       struct v4l2_subdev *sensor;
 392 +       /* Pad config for the sensor */
 393 +       struct v4l2_subdev_pad_config *sensor_config;
 394 +       /* current input at the sub device */
 395 +       int current_input;
 396 +
 397 +       /* Pointer pointing to current v4l2_buffer */
 398 +       struct unicam_buffer *cur_frm;
 399 +       /* Pointer pointing to next v4l2_buffer */
 400 +       struct unicam_buffer *next_frm;
 401 +
 402 +       /* video capture */
 403 +       const struct unicam_fmt *fmt;
 404 +       /* Used to store current pixel format */
 405 +       struct v4l2_format v_fmt;
 406 +       /* Used to store current mbus frame format */
 407 +       struct v4l2_mbus_framefmt m_fmt;
 408 +
 409 +       struct unicam_fmt active_fmts[MAX_POSSIBLE_PIX_FMTS];
 410 +       int num_active_fmt;
 411 +       unsigned int virtual_channel;
 412 +       enum v4l2_mbus_type bus_type;
 413 +       /*
 414 +        * Stores bus.mipi_csi2.flags for CSI2 sensors, or
 415 +        * bus.mipi_csi1.strobe for CCP2.
 416 +        */
 417 +       unsigned int bus_flags;
 418 +       unsigned int max_data_lanes;
 419 +       unsigned int active_data_lanes;
 420 +
 421 +       struct v4l2_rect crop;
 422 +
 423 +       /* Currently selected input on subdev */
 424 +       int input;
 425 +
 426 +       /* Buffer queue used in video-buf */
 427 +       struct vb2_queue buffer_queue;
 428 +       /* Queue of filled frames */
 429 +       struct unicam_dmaqueue dma_queue;
 430 +       /* IRQ lock for DMA queue */
 431 +       spinlock_t dma_queue_lock;
 432 +       /* lock used to access this structure */
 433 +       struct mutex lock;
 434 +       /* Flag to denote that we are processing buffers */
 435 +       int streaming;
 436 +};
 437 +
 438 +/* Hardware access */
 439 +#define clk_write(dev, val) writel((val) | 0x5a000000, (dev)->clk_gate_base)
 440 +#define clk_read(dev) readl((dev)->clk_gate_base)
 441 +
 442 +#define reg_read(dev, offset) readl((dev)->base + (offset))
 443 +#define reg_write(dev, offset, val) writel(val, (dev)->base + (offset))
 444 +
 445 +#define reg_read_field(dev, offset, mask) get_field(reg_read((dev), (offset), \
 446 +                                                   mask))
 447 +
 448 +static inline int get_field(u32 value, u32 mask)
 449 +{
 450 +       return (value & mask) >> __ffs(mask);
 451 +}
 452 +
 453 +static inline void set_field(u32 *valp, u32 field, u32 mask)
 454 +{
 455 +       u32 val = *valp;
 456 +
 457 +       val &= ~mask;
 458 +       val |= (field << __ffs(mask)) & mask;
 459 +       *valp = val;
 460 +}
 461 +
 462 +static inline void reg_write_field(struct unicam_cfg *dev, u32 offset,
 463 +                                  u32 field, u32 mask)
 464 +{
 465 +       u32 val = reg_read((dev), (offset));
 466 +
 467 +       set_field(&val, field, mask);
 468 +       reg_write((dev), (offset), val);
 469 +}
 470 +
 471 +/* Power management functions */
 472 +static inline int unicam_runtime_get(struct unicam_device *dev)
 473 +{
 474 +       int r;
 475 +
 476 +       r = pm_runtime_get_sync(&dev->pdev->dev);
 477 +
 478 +       return r;
 479 +}
 480 +
 481 +static inline void unicam_runtime_put(struct unicam_device *dev)
 482 +{
 483 +       pm_runtime_put_sync(&dev->pdev->dev);
 484 +}
 485 +
 486 +/* Format setup functions */
 487 +static int find_mbus_depth_by_code(u32 code)
 488 +{
 489 +       const struct unicam_fmt *fmt;
 490 +       unsigned int k;
 491 +
 492 +       for (k = 0; k < ARRAY_SIZE(formats); k++) {
 493 +               fmt = &formats[k];
 494 +               if (fmt->code == code)
 495 +                       return fmt->depth;
 496 +       }
 497 +
 498 +       return 0;
 499 +}
 500 +
 501 +static const struct unicam_fmt *find_format_by_code(struct unicam_device *dev,
 502 +                                                   u32 code)
 503 +{
 504 +       const struct unicam_fmt *fmt;
 505 +       unsigned int k;
 506 +
 507 +       for (k = 0; k < dev->num_active_fmt; k++) {
 508 +               fmt = &dev->active_fmts[k];
 509 +               if (fmt->code == code)
 510 +                       return fmt;
 511 +       }
 512 +
 513 +       return NULL;
 514 +}
 515 +
 516 +static const struct unicam_fmt *find_format_by_pix(struct unicam_device *dev,
 517 +                                                  u32 pixelformat)
 518 +{
 519 +       const struct unicam_fmt *fmt;
 520 +       unsigned int k;
 521 +
 522 +       for (k = 0; k < dev->num_active_fmt; k++) {
 523 +               fmt = &dev->active_fmts[k];
 524 +               if (fmt->fourcc == pixelformat)
 525 +                       return fmt;
 526 +       }
 527 +
 528 +       return NULL;
 529 +}
 530 +
 531 +static void dump_active_formats(struct unicam_device *dev)
 532 +{
 533 +       int i;
 534 +
 535 +       for (i = 0; i < dev->num_active_fmt; i++) {
 536 +               unicam_dbg(3, dev, "active_fmt[%d] (%p) is code %04x, fourcc " V4L2_FOURCC_CONV ", depth %d\n",
 537 +                          i, &dev->active_fmts[i], dev->active_fmts[i].code,
 538 +                          V4L2_FOURCC_CONV_ARGS(dev->active_fmts[i].fourcc),
 539 +                          dev->active_fmts[i].depth);
 540 +       }
 541 +}
 542 +
 543 +static inline unsigned int bytes_per_line(u32 width,
 544 +                                         const struct unicam_fmt *fmt)
 545 +{
 546 +       return ALIGN((width * fmt->depth) >> 3, BPL_ALIGNMENT);
 547 +}
 548 +
 549 +static int __subdev_get_format(struct unicam_device *dev,
 550 +                              struct v4l2_mbus_framefmt *fmt)
 551 +{
 552 +       struct v4l2_subdev_format sd_fmt = {0};
 553 +       struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
 554 +       int ret;
 555 +
 556 +       sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
 557 +       sd_fmt.pad = 0;
 558 +
 559 +       ret = v4l2_subdev_call(dev->sensor, pad, get_fmt, dev->sensor_config,
 560 +                              &sd_fmt);
 561 +       if (ret < 0)
 562 +               return ret;
 563 +
 564 +       *fmt = *mbus_fmt;
 565 +
 566 +       unicam_dbg(1, dev, "%s %dx%d code:%04x\n", __func__,
 567 +                  fmt->width, fmt->height, fmt->code);
 568 +
 569 +       return 0;
 570 +}
 571 +
 572 +static int __subdev_set_format(struct unicam_device *dev,
 573 +                              struct v4l2_mbus_framefmt *fmt)
 574 +{
 575 +       struct v4l2_subdev_format sd_fmt = {
 576 +               .which = V4L2_SUBDEV_FORMAT_ACTIVE,
 577 +       };
 578 +       struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
 579 +       int ret;
 580 +
 581 +       *mbus_fmt = *fmt;
 582 +
 583 +       ret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,
 584 +                              &sd_fmt);
 585 +       if (ret < 0)
 586 +               return ret;
 587 +
 588 +       unicam_dbg(1, dev, "%s %dx%d code:%04x\n", __func__,
 589 +                  fmt->width, fmt->height, fmt->code);
 590 +
 591 +       return 0;
 592 +}
 593 +
 594 +static int unicam_calc_format_size_bpl(struct unicam_device *dev,
 595 +                                      const struct unicam_fmt *fmt,
 596 +                                      struct v4l2_format *f)
 597 +{
 598 +       unsigned int min_bytesperline;
 599 +
 600 +       v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 2,
 601 +                             &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 0,
 602 +                             0);
 603 +
 604 +       min_bytesperline = bytes_per_line(f->fmt.pix.width, fmt);
 605 +
 606 +       if (f->fmt.pix.bytesperline > min_bytesperline &&
 607 +           f->fmt.pix.bytesperline <= MAX_BYTESPERLINE)
 608 +               f->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,
 609 +                                               BPL_ALIGNMENT);
 610 +       else
 611 +               f->fmt.pix.bytesperline = min_bytesperline;
 612 +
 613 +       /* Align height up for compatibility with other hardware blocks */
 614 +       f->fmt.pix.sizeimage = ALIGN(f->fmt.pix.height, HEIGHT_ALIGNMENT) *
 615 +                              f->fmt.pix.bytesperline;
 616 +
 617 +       unicam_dbg(3, dev, "%s: fourcc: " V4L2_FOURCC_CONV " size: %dx%d bpl:%d img_size:%d\n",
 618 +                  __func__,
 619 +                  V4L2_FOURCC_CONV_ARGS(f->fmt.pix.pixelformat),
 620 +                  f->fmt.pix.width, f->fmt.pix.height,
 621 +                  f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
 622 +
 623 +       return 0;
 624 +}
 625 +
 626 +static int unicam_reset_format(struct unicam_device *dev)
 627 +{
 628 +       struct v4l2_mbus_framefmt mbus_fmt;
 629 +       int ret;
 630 +
 631 +       ret = __subdev_get_format(dev, &mbus_fmt);
 632 +       if (ret) {
 633 +               unicam_err(dev, "Failed to get_format - ret %d\n", ret);
 634 +               return ret;
 635 +       }
 636 +
 637 +       if (mbus_fmt.code != dev->fmt->code) {
 638 +               unicam_err(dev, "code mismatch - fmt->code %08x, mbus_fmt.code %08x\n",
 639 +                          dev->fmt->code, mbus_fmt.code);
 640 +               return ret;
 641 +       }
 642 +
 643 +       v4l2_fill_pix_format(&dev->v_fmt.fmt.pix, &mbus_fmt);
 644 +       dev->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
 645 +
 646 +       unicam_calc_format_size_bpl(dev, dev->fmt, &dev->v_fmt);
 647 +
 648 +       dev->m_fmt = mbus_fmt;
 649 +
 650 +       return 0;
 651 +}
 652 +
 653 +static void unicam_wr_dma_addr(struct unicam_device *dev, unsigned int dmaaddr)
 654 +{
 655 +       unicam_dbg(1, dev, "wr_dma_addr %08x-%08x\n",
 656 +                  dmaaddr, dmaaddr + dev->v_fmt.fmt.pix.sizeimage);
 657 +       reg_write(&dev->cfg, UNICAM_IBSA0, dmaaddr);
 658 +       reg_write(&dev->cfg, UNICAM_IBEA0,
 659 +                 dmaaddr + dev->v_fmt.fmt.pix.sizeimage);
 660 +}
 661 +
 662 +static inline void unicam_schedule_next_buffer(struct unicam_device *dev)
 663 +{
 664 +       struct unicam_dmaqueue *dma_q = &dev->dma_queue;
 665 +       struct unicam_buffer *buf;
 666 +       dma_addr_t addr;
 667 +
 668 +       buf = list_entry(dma_q->active.next, struct unicam_buffer, list);
 669 +       dev->next_frm = buf;
 670 +       list_del(&buf->list);
 671 +
 672 +       addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
 673 +       unicam_wr_dma_addr(dev, addr);
 674 +}
 675 +
 676 +static inline void unicam_process_buffer_complete(struct unicam_device *dev)
 677 +{
 678 +       dev->cur_frm->vb.field = dev->m_fmt.field;
 679 +       dev->cur_frm->vb.sequence = dev->sequence++;
 680 +
 681 +       vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
 682 +       dev->cur_frm = dev->next_frm;
 683 +}
 684 +
 685 +/*
 686 + * unicam_isr : ISR handler for unicam capture
 687 + * @irq: irq number
 688 + * @dev_id: dev_id ptr
 689 + *
 690 + * It changes status of the captured buffer, takes next buffer from the queue
 691 + * and sets its address in unicam registers
 692 + */
 693 +static irqreturn_t unicam_isr(int irq, void *dev)
 694 +{
 695 +       struct unicam_device *unicam = (struct unicam_device *)dev;
 696 +       struct unicam_cfg *cfg = &unicam->cfg;
 697 +       struct unicam_dmaqueue *dma_q = &unicam->dma_queue;
 698 +       int ista, sta;
 699 +
 700 +       /*
 701 +        * Don't service interrupts if not streaming.
 702 +        * Avoids issues if the VPU should enable the
 703 +        * peripheral without the kernel knowing (that
 704 +        * shouldn't happen, but causes issues if it does).
 705 +        */
 706 +       if (!unicam->streaming)
 707 +               return IRQ_HANDLED;
 708 +
 709 +       sta = reg_read(cfg, UNICAM_STA);
 710 +       /* Write value back to clear the interrupts */
 711 +       reg_write(cfg, UNICAM_STA, sta);
 712 +
 713 +       ista = reg_read(cfg, UNICAM_ISTA);
 714 +       /* Write value back to clear the interrupts */
 715 +       reg_write(cfg, UNICAM_ISTA, ista);
 716 +
 717 +       if (!(sta && (UNICAM_IS | UNICAM_PI0)))
 718 +               return IRQ_HANDLED;
 719 +
 720 +       if (ista & UNICAM_FSI) {
 721 +               /*
 722 +                * Timestamp is to be when the first data byte was captured,
 723 +                * aka frame start.
 724 +                */
 725 +               if (unicam->cur_frm)
 726 +                       unicam->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();
 727 +       }
 728 +       if (ista & UNICAM_FEI || sta & UNICAM_PI0) {
 729 +               /*
 730 +                * Ensure we have swapped buffers already as we can't
 731 +                * stop the peripheral. Overwrite the frame we've just
 732 +                * captured instead.
 733 +                */
 734 +               if (unicam->cur_frm && unicam->cur_frm != unicam->next_frm)
 735 +                       unicam_process_buffer_complete(unicam);
 736 +       }
 737 +
 738 +       if (ista & (UNICAM_FSI | UNICAM_LCI)) {
 739 +               spin_lock(&unicam->dma_queue_lock);
 740 +               if (!list_empty(&dma_q->active) &&
 741 +                   unicam->cur_frm == unicam->next_frm)
 742 +                       unicam_schedule_next_buffer(unicam);
 743 +               spin_unlock(&unicam->dma_queue_lock);
 744 +       }
 745 +
 746 +       if (reg_read(&unicam->cfg, UNICAM_ICTL) & UNICAM_FCM) {
 747 +               /* Switch out of trigger mode if selected */
 748 +               reg_write_field(&unicam->cfg, UNICAM_ICTL, 1, UNICAM_TFC);
 749 +               reg_write_field(&unicam->cfg, UNICAM_ICTL, 0, UNICAM_FCM);
 750 +       }
 751 +       return IRQ_HANDLED;
 752 +}
 753 +
 754 +static int unicam_querycap(struct file *file, void *priv,
 755 +                          struct v4l2_capability *cap)
 756 +{
 757 +       struct unicam_device *dev = video_drvdata(file);
 758 +
 759 +       strlcpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));
 760 +       strlcpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));
 761 +
 762 +       snprintf(cap->bus_info, sizeof(cap->bus_info),
 763 +                "platform:%s", dev->v4l2_dev.name);
 764 +
 765 +       return 0;
 766 +}
 767 +
 768 +static int unicam_enum_fmt_vid_cap(struct file *file, void  *priv,
 769 +                                  struct v4l2_fmtdesc *f)
 770 +{
 771 +       struct unicam_device *dev = video_drvdata(file);
 772 +       const struct unicam_fmt *fmt = NULL;
 773 +
 774 +       if (f->index >= dev->num_active_fmt)
 775 +               return -EINVAL;
 776 +
 777 +       fmt = &dev->active_fmts[f->index];
 778 +
 779 +       f->pixelformat = fmt->fourcc;
 780 +
 781 +       return 0;
 782 +}
 783 +
 784 +static int unicam_g_fmt_vid_cap(struct file *file, void *priv,
 785 +                               struct v4l2_format *f)
 786 +{
 787 +       struct unicam_device *dev = video_drvdata(file);
 788 +
 789 +       *f = dev->v_fmt;
 790 +
 791 +       return 0;
 792 +}
 793 +
 794 +static int unicam_try_fmt_vid_cap(struct file *file, void *priv,
 795 +                                 struct v4l2_format *f)
 796 +{
 797 +       struct unicam_device *dev = video_drvdata(file);
 798 +       const struct unicam_fmt *fmt;
 799 +       struct v4l2_subdev_format sd_fmt = {
 800 +               .which = V4L2_SUBDEV_FORMAT_TRY,
 801 +       };
 802 +       struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
 803 +       int ret;
 804 +
 805 +       fmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);
 806 +       if (!fmt) {
 807 +               unicam_dbg(3, dev, "Fourcc format (0x%08x) not found. Use default of %08X\n",
 808 +                          f->fmt.pix.pixelformat, dev->active_fmts[0].fourcc);
 809 +
 810 +               /* Just get the first one enumerated */
 811 +               fmt = &dev->active_fmts[0];
 812 +               f->fmt.pix.pixelformat = fmt->fourcc;
 813 +       }
 814 +
 815 +       v4l2_fill_mbus_format(mbus_fmt, &f->fmt.pix, fmt->code);
 816 +       /*
 817 +        * No support for receiving interlaced video, so never
 818 +        * request it from the sensor subdev.
 819 +        */
 820 +       mbus_fmt->field = V4L2_FIELD_NONE;
 821 +
 822 +       ret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,
 823 +                              &sd_fmt);
 824 +       if (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)
 825 +               return ret;
 826 +
 827 +       if (mbus_fmt->field != V4L2_FIELD_NONE)
 828 +               unicam_info(dev, "Sensor trying to send interlaced video - results may be unpredictable\n");
 829 +
 830 +       v4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);
 831 +       /*
 832 +        * Use current colorspace for now, it will get
 833 +        * updated properly during s_fmt
 834 +        */
 835 +       f->fmt.pix.colorspace = dev->v_fmt.fmt.pix.colorspace;
 836 +       return unicam_calc_format_size_bpl(dev, fmt, f);
 837 +}
 838 +
 839 +static int unicam_s_fmt_vid_cap(struct file *file, void *priv,
 840 +                               struct v4l2_format *f)
 841 +{
 842 +       struct unicam_device *dev = video_drvdata(file);
 843 +       struct vb2_queue *q = &dev->buffer_queue;
 844 +       const struct unicam_fmt *fmt;
 845 +       struct v4l2_mbus_framefmt mbus_fmt = {0};
 846 +       int ret;
 847 +
 848 +       if (vb2_is_busy(q))
 849 +               return -EBUSY;
 850 +
 851 +       ret = unicam_try_fmt_vid_cap(file, priv, f);
 852 +       if (ret < 0)
 853 +               return ret;
 854 +
 855 +       fmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);
 856 +       if (!fmt) {
 857 +               /* Unknown pixel format - adopt a default */
 858 +               fmt = &dev->active_fmts[0];
 859 +               f->fmt.pix.pixelformat = fmt->fourcc;
 860 +               return -EINVAL;
 861 +       }
 862 +
 863 +       v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);
 864 +
 865 +       ret = __subdev_set_format(dev, &mbus_fmt);
 866 +       if (ret) {
 867 +               unicam_dbg(3, dev, "%s __subdev_set_format failed %d\n",
 868 +                          __func__, ret);
 869 +               return ret;
 870 +       }
 871 +
 872 +       /* Just double check nothing has gone wrong */
 873 +       if (mbus_fmt.code != fmt->code) {
 874 +               unicam_dbg(3, dev,
 875 +                          "%s subdev changed format on us, this should not happen\n",
 876 +                          __func__);
 877 +               return -EINVAL;
 878 +       }
 879 +
 880 +       dev->fmt = fmt;
 881 +       dev->v_fmt.fmt.pix.pixelformat = f->fmt.pix.pixelformat;
 882 +       dev->v_fmt.fmt.pix.bytesperline = f->fmt.pix.bytesperline;
 883 +       unicam_reset_format(dev);
 884 +
 885 +       unicam_dbg(3, dev, "%s %dx%d, mbus_fmt %08X, V4L2 pix " V4L2_FOURCC_CONV ".\n",
 886 +                  __func__, dev->v_fmt.fmt.pix.width,
 887 +                  dev->v_fmt.fmt.pix.height, mbus_fmt.code,
 888 +                  V4L2_FOURCC_CONV_ARGS(dev->v_fmt.fmt.pix.pixelformat));
 889 +
 890 +       *f = dev->v_fmt;
 891 +
 892 +       return 0;
 893 +}
 894 +
 895 +static int unicam_queue_setup(struct vb2_queue *vq,
 896 +                             unsigned int *nbuffers,
 897 +                             unsigned int *nplanes,
 898 +                             unsigned int sizes[],
 899 +                             struct device *alloc_devs[])
 900 +{
 901 +       struct unicam_device *dev = vb2_get_drv_priv(vq);
 902 +       unsigned int size = dev->v_fmt.fmt.pix.sizeimage;
 903 +
 904 +       if (vq->num_buffers + *nbuffers < 3)
 905 +               *nbuffers = 3 - vq->num_buffers;
 906 +
 907 +       if (*nplanes) {
 908 +               if (sizes[0] < size) {
 909 +                       unicam_err(dev, "sizes[0] %i < size %u\n", sizes[0],
 910 +                                  size);
 911 +                       return -EINVAL;
 912 +               }
 913 +               size = sizes[0];
 914 +       }
 915 +
 916 +       *nplanes = 1;
 917 +       sizes[0] = size;
 918 +
 919 +       return 0;
 920 +}
 921 +
 922 +static int unicam_buffer_prepare(struct vb2_buffer *vb)
 923 +{
 924 +       struct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);
 925 +       struct unicam_buffer *buf = container_of(vb, struct unicam_buffer,
 926 +                                             vb.vb2_buf);
 927 +       unsigned long size;
 928 +
 929 +       if (WARN_ON(!dev->fmt))
 930 +               return -EINVAL;
 931 +
 932 +       size = dev->v_fmt.fmt.pix.sizeimage;
 933 +       if (vb2_plane_size(vb, 0) < size) {
 934 +               unicam_err(dev, "data will not fit into plane (%lu < %lu)\n",
 935 +                          vb2_plane_size(vb, 0), size);
 936 +               return -EINVAL;
 937 +       }
 938 +
 939 +       vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
 940 +       return 0;
 941 +}
 942 +
 943 +static void unicam_buffer_queue(struct vb2_buffer *vb)
 944 +{
 945 +       struct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);
 946 +       struct unicam_buffer *buf = container_of(vb, struct unicam_buffer,
 947 +                                             vb.vb2_buf);
 948 +       struct unicam_dmaqueue *dma_queue = &dev->dma_queue;
 949 +       unsigned long flags = 0;
 950 +
 951 +       /* recheck locking */
 952 +       spin_lock_irqsave(&dev->dma_queue_lock, flags);
 953 +       list_add_tail(&buf->list, &dma_queue->active);
 954 +       spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
 955 +}
 956 +
 957 +static void unicam_wr_dma_config(struct unicam_device *dev,
 958 +                                unsigned int stride)
 959 +{
 960 +       reg_write(&dev->cfg, UNICAM_IBLS, stride);
 961 +}
 962 +
 963 +static void unicam_set_packing_config(struct unicam_device *dev)
 964 +{
 965 +       int mbus_depth = find_mbus_depth_by_code(dev->fmt->code);
 966 +       int v4l2_depth = dev->fmt->depth;
 967 +       int pack, unpack;
 968 +       u32 val;
 969 +
 970 +       if (mbus_depth == v4l2_depth) {
 971 +               unpack = UNICAM_PUM_NONE;
 972 +               pack = UNICAM_PPM_NONE;
 973 +       } else {
 974 +               switch (mbus_depth) {
 975 +               case 8:
 976 +                       unpack = UNICAM_PUM_UNPACK8;
 977 +                       break;
 978 +               case 10:
 979 +                       unpack = UNICAM_PUM_UNPACK10;
 980 +                       break;
 981 +               case 12:
 982 +                       unpack = UNICAM_PUM_UNPACK12;
 983 +                       break;
 984 +               case 14:
 985 +                       unpack = UNICAM_PUM_UNPACK14;
 986 +                       break;
 987 +               case 16:
 988 +                       unpack = UNICAM_PUM_UNPACK16;
 989 +                       break;
 990 +               default:
 991 +                       unpack = UNICAM_PUM_NONE;
 992 +                       break;
 993 +               }
 994 +               switch (v4l2_depth) {
 995 +               case 8:
 996 +                       pack = UNICAM_PPM_PACK8;
 997 +                       break;
 998 +               case 10:
 999 +                       pack = UNICAM_PPM_PACK10;
1000 +                       break;
1001 +               case 12:
1002 +                       pack = UNICAM_PPM_PACK12;
1003 +                       break;
1004 +               case 14:
1005 +                       pack = UNICAM_PPM_PACK14;
1006 +                       break;
1007 +               case 16:
1008 +                       pack = UNICAM_PPM_PACK16;
1009 +                       break;
1010 +               default:
1011 +                       pack = UNICAM_PPM_NONE;
1012 +                       break;
1013 +               }
1014 +       }
1015 +
1016 +       val = 0;
1017 +       set_field(&val, 2, UNICAM_DEBL_MASK);
1018 +       set_field(&val, unpack, UNICAM_PUM_MASK);
1019 +       set_field(&val, pack, UNICAM_PPM_MASK);
1020 +       reg_write(&dev->cfg, UNICAM_IPIPE, val);
1021 +}
1022 +
1023 +static void unicam_cfg_image_id(struct unicam_device *dev)
1024 +{
1025 +       struct unicam_cfg *cfg = &dev->cfg;
1026 +
1027 +       if (dev->bus_type == V4L2_MBUS_CSI2) {
1028 +               /* CSI2 mode */
1029 +               reg_write(cfg, UNICAM_IDI0,
1030 +                         (dev->virtual_channel << 6) | dev->fmt->csi_dt);
1031 +       } else {
1032 +               /* CCP2 mode */
1033 +               reg_write(cfg, UNICAM_IDI0, (0x80 | dev->fmt->csi_dt));
1034 +       }
1035 +}
1036 +
1037 +void unicam_start_rx(struct unicam_device *dev, unsigned long addr)
1038 +{
1039 +       struct unicam_cfg *cfg = &dev->cfg;
1040 +       int line_int_freq = dev->v_fmt.fmt.pix.height >> 2;
1041 +       unsigned int i;
1042 +       u32 val;
1043 +
1044 +       if (line_int_freq < 128)
1045 +               line_int_freq = 128;
1046 +
1047 +       /* Enable lane clocks */
1048 +       val = 1;
1049 +       for (i = 0; i < dev->active_data_lanes; i++)
1050 +               val = val << 2 | 1;
1051 +       clk_write(cfg, val);
1052 +
1053 +       /* Basic init */
1054 +       reg_write(cfg, UNICAM_CTRL, UNICAM_MEM);
1055 +
1056 +       /* Enable analogue control, and leave in reset. */
1057 +       val = UNICAM_AR;
1058 +       set_field(&val, 7, UNICAM_CTATADJ_MASK);
1059 +       set_field(&val, 7, UNICAM_PTATADJ_MASK);
1060 +       reg_write(cfg, UNICAM_ANA, val);
1061 +       usleep_range(1000, 2000);
1062 +
1063 +       /* Come out of reset */
1064 +       reg_write_field(cfg, UNICAM_ANA, 0, UNICAM_AR);
1065 +
1066 +       /* Peripheral reset */
1067 +       reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);
1068 +       reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);
1069 +
1070 +       reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);
1071 +
1072 +       /* Enable Rx control. */
1073 +       val = reg_read(cfg, UNICAM_CTRL);
1074 +       if (dev->bus_type == V4L2_MBUS_CSI2) {
1075 +               set_field(&val, UNICAM_CPM_CSI2, UNICAM_CPM_MASK);
1076 +               set_field(&val, UNICAM_DCM_STROBE, UNICAM_DCM_MASK);
1077 +       } else {
1078 +               set_field(&val, UNICAM_CPM_CCP2, UNICAM_CPM_MASK);
1079 +               set_field(&val, dev->bus_flags, UNICAM_DCM_MASK);
1080 +       }
1081 +       /* Packet framer timeout */
1082 +       set_field(&val, 0xf, UNICAM_PFT_MASK);
1083 +       set_field(&val, 128, UNICAM_OET_MASK);
1084 +       reg_write(cfg, UNICAM_CTRL, val);
1085 +
1086 +       reg_write(cfg, UNICAM_IHWIN, 0);
1087 +       reg_write(cfg, UNICAM_IVWIN, 0);
1088 +
1089 +       /* AXI bus access QoS setup */
1090 +       val = reg_read(&dev->cfg, UNICAM_PRI);
1091 +       set_field(&val, 0, UNICAM_BL_MASK);
1092 +       set_field(&val, 0, UNICAM_BS_MASK);
1093 +       set_field(&val, 0xe, UNICAM_PP_MASK);
1094 +       set_field(&val, 8, UNICAM_NP_MASK);
1095 +       set_field(&val, 2, UNICAM_PT_MASK);
1096 +       set_field(&val, 1, UNICAM_PE);
1097 +       reg_write(cfg, UNICAM_PRI, val);
1098 +
1099 +       reg_write_field(cfg, UNICAM_ANA, 0, UNICAM_DDL);
1100 +
1101 +       /* Always start in trigger frame capture mode (UNICAM_FCM set) */
1102 +       val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM;
1103 +       set_field(&val,  line_int_freq, UNICAM_LCIE_MASK);
1104 +       reg_write(cfg, UNICAM_ICTL, val);
1105 +       reg_write(cfg, UNICAM_STA, UNICAM_STA_MASK_ALL);
1106 +       reg_write(cfg, UNICAM_ISTA, UNICAM_ISTA_MASK_ALL);
1107 +
1108 +       /* tclk_term_en */
1109 +       reg_write_field(cfg, UNICAM_CLT, 2, UNICAM_CLT1_MASK);
1110 +       /* tclk_settle */
1111 +       reg_write_field(cfg, UNICAM_CLT, 6, UNICAM_CLT2_MASK);
1112 +       /* td_term_en */
1113 +       reg_write_field(cfg, UNICAM_DLT, 2, UNICAM_DLT1_MASK);
1114 +       /* ths_settle */
1115 +       reg_write_field(cfg, UNICAM_DLT, 6, UNICAM_DLT2_MASK);
1116 +       /* trx_enable */
1117 +       reg_write_field(cfg, UNICAM_DLT, 0, UNICAM_DLT3_MASK);
1118 +
1119 +       reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_SOE);
1120 +
1121 +       /* Packet compare setup - required to avoid missing frame ends */
1122 +       val = 0;
1123 +       set_field(&val, 1, UNICAM_PCE);
1124 +       set_field(&val, 1, UNICAM_GI);
1125 +       set_field(&val, 1, UNICAM_CPH);
1126 +       set_field(&val, 0, UNICAM_PCVC_MASK);
1127 +       set_field(&val, 1, UNICAM_PCDT_MASK);
1128 +       reg_write(cfg, UNICAM_CMP0, val);
1129 +
1130 +       /* Enable clock lane and set up terminations */
1131 +       val = 0;
1132 +       if (dev->bus_type == V4L2_MBUS_CSI2) {
1133 +               /* CSI2 */
1134 +               set_field(&val, 1, UNICAM_CLE);
1135 +               set_field(&val, 1, UNICAM_CLLPE);
1136 +               if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
1137 +                       set_field(&val, 1, UNICAM_CLTRE);
1138 +                       set_field(&val, 1, UNICAM_CLHSE);
1139 +               }
1140 +       } else {
1141 +               /* CCP2 */
1142 +               set_field(&val, 1, UNICAM_CLE);
1143 +               set_field(&val, 1, UNICAM_CLHSE);
1144 +               set_field(&val, 1, UNICAM_CLTRE);
1145 +       }
1146 +       reg_write(cfg, UNICAM_CLK, val);
1147 +
1148 +       /*
1149 +        * Enable required data lanes with appropriate terminations.
1150 +        * The same value needs to be written to UNICAM_DATn registers for
1151 +        * the active lanes, and 0 for inactive ones.
1152 +        */
1153 +       val = 0;
1154 +       if (dev->bus_type == V4L2_MBUS_CSI2) {
1155 +               /* CSI2 */
1156 +               set_field(&val, 1, UNICAM_DLE);
1157 +               set_field(&val, 1, UNICAM_DLLPE);
1158 +               if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
1159 +                       set_field(&val, 1, UNICAM_DLTRE);
1160 +                       set_field(&val, 1, UNICAM_DLHSE);
1161 +               }
1162 +       } else {
1163 +               /* CCP2 */
1164 +               set_field(&val, 1, UNICAM_DLE);
1165 +               set_field(&val, 1, UNICAM_DLHSE);
1166 +               set_field(&val, 1, UNICAM_DLTRE);
1167 +       }
1168 +       reg_write(cfg, UNICAM_DAT0, val);
1169 +
1170 +       if (dev->active_data_lanes == 1)
1171 +               val = 0;
1172 +       reg_write(cfg, UNICAM_DAT1, val);
1173 +
1174 +       if (dev->max_data_lanes > 2) {
1175 +               /*
1176 +                * Registers UNICAM_DAT2 and UNICAM_DAT3 only valid if the
1177 +                * instance supports more than 2 data lanes.
1178 +                */
1179 +               if (dev->active_data_lanes == 2)
1180 +                       val = 0;
1181 +               reg_write(cfg, UNICAM_DAT2, val);
1182 +
1183 +               if (dev->active_data_lanes == 3)
1184 +                       val = 0;
1185 +               reg_write(cfg, UNICAM_DAT3, val);
1186 +       }
1187 +
1188 +       unicam_wr_dma_config(dev, dev->v_fmt.fmt.pix.bytesperline);
1189 +       unicam_wr_dma_addr(dev, addr);
1190 +       unicam_set_packing_config(dev);
1191 +       unicam_cfg_image_id(dev);
1192 +
1193 +       /* Disabled embedded data */
1194 +       val = 0;
1195 +       set_field(&val, 0, UNICAM_EDL_MASK);
1196 +       reg_write(cfg, UNICAM_DCS, val);
1197 +
1198 +       val = reg_read(cfg, UNICAM_MISC);
1199 +       set_field(&val, 1, UNICAM_FL0);
1200 +       set_field(&val, 1, UNICAM_FL1);
1201 +       reg_write(cfg, UNICAM_MISC, val);
1202 +
1203 +       /* Enable peripheral */
1204 +       reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPE);
1205 +
1206 +       /* Load image pointers */
1207 +       reg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_LIP_MASK);
1208 +
1209 +       /*
1210 +        * Enable trigger only for the first frame to
1211 +        * sync correctly to the FS from the source.
1212 +        */
1213 +       reg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_TFC);
1214 +}
1215 +
1216 +static void unicam_disable(struct unicam_device *dev)
1217 +{
1218 +       struct unicam_cfg *cfg = &dev->cfg;
1219 +
1220 +       /* Analogue lane control disable */
1221 +       reg_write_field(cfg, UNICAM_ANA, 1, UNICAM_DDL);
1222 +
1223 +       /* Stop the output engine */
1224 +       reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_SOE);
1225 +
1226 +       /* Disable the data lanes. */
1227 +       reg_write(cfg, UNICAM_DAT0, 0);
1228 +       reg_write(cfg, UNICAM_DAT1, 0);
1229 +
1230 +       if (dev->max_data_lanes > 2) {
1231 +               reg_write(cfg, UNICAM_DAT2, 0);
1232 +               reg_write(cfg, UNICAM_DAT3, 0);
1233 +       }
1234 +
1235 +       /* Peripheral reset */
1236 +       reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);
1237 +       usleep_range(50, 100);
1238 +       reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);
1239 +
1240 +       /* Disable peripheral */
1241 +       reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);
1242 +
1243 +       /* Disable all lane clocks */
1244 +       clk_write(cfg, 0);
1245 +}
1246 +
1247 +static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)
1248 +{
1249 +       struct unicam_device *dev = vb2_get_drv_priv(vq);
1250 +       struct unicam_dmaqueue *dma_q = &dev->dma_queue;
1251 +       struct unicam_buffer *buf, *tmp;
1252 +       unsigned long addr = 0;
1253 +       unsigned long flags;
1254 +       int ret;
1255 +
1256 +       spin_lock_irqsave(&dev->dma_queue_lock, flags);
1257 +       buf = list_entry(dma_q->active.next, struct unicam_buffer, list);
1258 +       dev->cur_frm = buf;
1259 +       dev->next_frm = buf;
1260 +       list_del(&buf->list);
1261 +       spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
1262 +
1263 +       addr = vb2_dma_contig_plane_dma_addr(&dev->cur_frm->vb.vb2_buf, 0);
1264 +       dev->sequence = 0;
1265 +
1266 +       ret = unicam_runtime_get(dev);
1267 +       if (ret < 0) {
1268 +               unicam_dbg(3, dev, "unicam_runtime_get failed\n");
1269 +               goto err_release_buffers;
1270 +       }
1271 +
1272 +       dev->active_data_lanes = dev->max_data_lanes;
1273 +       if (dev->bus_type == V4L2_MBUS_CSI2 &&
1274 +           v4l2_subdev_has_op(dev->sensor, video, g_mbus_config)) {
1275 +               struct v4l2_mbus_config mbus_config;
1276 +
1277 +               ret = v4l2_subdev_call(dev->sensor, video, g_mbus_config,
1278 +                                      &mbus_config);
1279 +               if (ret < 0) {
1280 +                       unicam_dbg(3, dev, "g_mbus_config failed\n");
1281 +                       goto err_pm_put;
1282 +               }
1283 +
1284 +               dev->active_data_lanes =
1285 +                       (mbus_config.flags & V4L2_MBUS_CSI2_LANE_MASK) >>
1286 +                                       __ffs(V4L2_MBUS_CSI2_LANE_MASK);
1287 +               if (!dev->active_data_lanes)
1288 +                       dev->active_data_lanes = dev->max_data_lanes;
1289 +       }
1290 +       if (dev->active_data_lanes > dev->max_data_lanes) {
1291 +               unicam_err(dev, "Device has requested %u data lanes, which is >%u configured in DT\n",
1292 +                          dev->active_data_lanes, dev->max_data_lanes);
1293 +               ret = -EINVAL;
1294 +               goto err_pm_put;
1295 +       }
1296 +
1297 +       unicam_dbg(1, dev, "Running with %u data lanes\n",
1298 +                  dev->active_data_lanes);
1299 +
1300 +       ret = clk_set_rate(dev->clock, 100 * 1000 * 1000);
1301 +       if (ret) {
1302 +               unicam_err(dev, "failed to set up clock\n");
1303 +               goto err_pm_put;
1304 +       }
1305 +
1306 +       ret = clk_prepare_enable(dev->clock);
1307 +       if (ret) {
1308 +               unicam_err(dev, "Failed to enable CSI clock: %d\n", ret);
1309 +               goto err_pm_put;
1310 +       }
1311 +       ret = v4l2_subdev_call(dev->sensor, core, s_power, 1);
1312 +       if (ret < 0 && ret != -ENOIOCTLCMD) {
1313 +               unicam_err(dev, "power on failed in subdev\n");
1314 +               goto err_clock_unprepare;
1315 +       }
1316 +       dev->streaming = 1;
1317 +
1318 +       unicam_start_rx(dev, addr);
1319 +
1320 +       ret = v4l2_subdev_call(dev->sensor, video, s_stream, 1);
1321 +       if (ret < 0) {
1322 +               unicam_err(dev, "stream on failed in subdev\n");
1323 +               goto err_disable_unicam;
1324 +       }
1325 +
1326 +       return 0;
1327 +
1328 +err_disable_unicam:
1329 +       unicam_disable(dev);
1330 +       v4l2_subdev_call(dev->sensor, core, s_power, 0);
1331 +err_clock_unprepare:
1332 +       clk_disable_unprepare(dev->clock);
1333 +err_pm_put:
1334 +       unicam_runtime_put(dev);
1335 +err_release_buffers:
1336 +       list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1337 +               list_del(&buf->list);
1338 +               vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
1339 +       }
1340 +       if (dev->cur_frm != dev->next_frm)
1341 +               vb2_buffer_done(&dev->next_frm->vb.vb2_buf,
1342 +                               VB2_BUF_STATE_QUEUED);
1343 +       vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
1344 +       dev->next_frm = NULL;
1345 +       dev->cur_frm = NULL;
1346 +
1347 +       return ret;
1348 +}
1349 +
1350 +static void unicam_stop_streaming(struct vb2_queue *vq)
1351 +{
1352 +       struct unicam_device *dev = vb2_get_drv_priv(vq);
1353 +       struct unicam_dmaqueue *dma_q = &dev->dma_queue;
1354 +       struct unicam_buffer *buf, *tmp;
1355 +       unsigned long flags;
1356 +
1357 +       if (v4l2_subdev_call(dev->sensor, video, s_stream, 0) < 0)
1358 +               unicam_err(dev, "stream off failed in subdev\n");
1359 +
1360 +       unicam_disable(dev);
1361 +
1362 +       /* Release all active buffers */
1363 +       spin_lock_irqsave(&dev->dma_queue_lock, flags);
1364 +       list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1365 +               list_del(&buf->list);
1366 +               vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1367 +       }
1368 +
1369 +       if (dev->cur_frm == dev->next_frm) {
1370 +               vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1371 +       } else {
1372 +               vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1373 +               vb2_buffer_done(&dev->next_frm->vb.vb2_buf,
1374 +                               VB2_BUF_STATE_ERROR);
1375 +       }
1376 +       dev->cur_frm = NULL;
1377 +       dev->next_frm = NULL;
1378 +       spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
1379 +
1380 +       if (v4l2_subdev_has_op(dev->sensor, core, s_power)) {
1381 +               if (v4l2_subdev_call(dev->sensor, core, s_power, 0) < 0)
1382 +                       unicam_err(dev, "power off failed in subdev\n");
1383 +       }
1384 +
1385 +       clk_disable_unprepare(dev->clock);
1386 +       unicam_runtime_put(dev);
1387 +}
1388 +
1389 +static int unicam_enum_input(struct file *file, void *priv,
1390 +                            struct v4l2_input *inp)
1391 +{
1392 +       struct unicam_device *dev = video_drvdata(file);
1393 +
1394 +       if (inp->index != 0)
1395 +               return -EINVAL;
1396 +
1397 +       inp->type = V4L2_INPUT_TYPE_CAMERA;
1398 +       if (v4l2_subdev_has_op(dev->sensor, video, s_dv_timings)) {
1399 +               inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
1400 +               inp->std = 0;
1401 +       } else if (v4l2_subdev_has_op(dev->sensor, video, s_std)) {
1402 +               inp->capabilities = V4L2_IN_CAP_STD;
1403 +               if (v4l2_subdev_call(dev->sensor, video, g_tvnorms, &inp->std)
1404 +                                       < 0)
1405 +                       inp->std = V4L2_STD_ALL;
1406 +       } else {
1407 +               inp->capabilities = 0;
1408 +               inp->std = 0;
1409 +       }
1410 +       sprintf(inp->name, "Camera 0");
1411 +       return 0;
1412 +}
1413 +
1414 +static int unicam_g_input(struct file *file, void *priv, unsigned int *i)
1415 +{
1416 +       *i = 0;
1417 +
1418 +       return 0;
1419 +}
1420 +
1421 +static int unicam_s_input(struct file *file, void *priv, unsigned int i)
1422 +{
1423 +       /*
1424 +        * FIXME: Ideally we would like to be able to query the source
1425 +        * subdevice for information over the input connectors it supports,
1426 +        * and map that through in to a call to video_ops->s_routing.
1427 +        * There is no infrastructure support for defining that within
1428 +        * devicetree at present. Until that is implemented we can't
1429 +        * map a user physical connector number to s_routing input number.
1430 +        */
1431 +       if (i > 0)
1432 +               return -EINVAL;
1433 +
1434 +       return 0;
1435 +}
1436 +
1437 +static int unicam_querystd(struct file *file, void *priv,
1438 +                          v4l2_std_id *std)
1439 +{
1440 +       struct unicam_device *dev = video_drvdata(file);
1441 +
1442 +       return v4l2_subdev_call(dev->sensor, video, querystd, std);
1443 +}
1444 +
1445 +static int unicam_g_std(struct file *file, void *priv, v4l2_std_id *std)
1446 +{
1447 +       struct unicam_device *dev = video_drvdata(file);
1448 +
1449 +       return v4l2_subdev_call(dev->sensor, video, g_std, std);
1450 +}
1451 +
1452 +static int unicam_s_std(struct file *file, void *priv, v4l2_std_id std)
1453 +{
1454 +       struct unicam_device *dev = video_drvdata(file);
1455 +       int ret;
1456 +       v4l2_std_id current_std;
1457 +
1458 +       ret = v4l2_subdev_call(dev->sensor, video, g_std, &current_std);
1459 +       if (ret)
1460 +               return ret;
1461 +
1462 +       if (std == current_std)
1463 +               return 0;
1464 +
1465 +       if (vb2_is_busy(&dev->buffer_queue))
1466 +               return -EBUSY;
1467 +
1468 +       ret = v4l2_subdev_call(dev->sensor, video, s_std, std);
1469 +
1470 +       /* Force recomputation of bytesperline */
1471 +       dev->v_fmt.fmt.pix.bytesperline = 0;
1472 +
1473 +       unicam_reset_format(dev);
1474 +
1475 +       return ret;
1476 +}
1477 +
1478 +static int unicam_s_edid(struct file *file, void *priv, struct v4l2_edid *edid)
1479 +{
1480 +       struct unicam_device *dev = video_drvdata(file);
1481 +
1482 +       return v4l2_subdev_call(dev->sensor, pad, set_edid, edid);
1483 +}
1484 +
1485 +static int unicam_g_edid(struct file *file, void *priv, struct v4l2_edid *edid)
1486 +{
1487 +       struct unicam_device *dev = video_drvdata(file);
1488 +
1489 +       return v4l2_subdev_call(dev->sensor, pad, get_edid, edid);
1490 +}
1491 +
1492 +static int unicam_g_dv_timings(struct file *file, void *priv,
1493 +                              struct v4l2_dv_timings *timings)
1494 +{
1495 +       struct unicam_device *dev = video_drvdata(file);
1496 +
1497 +       return v4l2_subdev_call(dev->sensor, video, g_dv_timings, timings);
1498 +}
1499 +
1500 +static int unicam_s_dv_timings(struct file *file, void *priv,
1501 +                              struct v4l2_dv_timings *timings)
1502 +{
1503 +       struct unicam_device *dev = video_drvdata(file);
1504 +       struct v4l2_dv_timings current_timings;
1505 +       int ret;
1506 +
1507 +       ret = v4l2_subdev_call(dev->sensor, video, g_dv_timings,
1508 +                              &current_timings);
1509 +
1510 +       if (v4l2_match_dv_timings(timings, &current_timings, 0, false))
1511 +               return 0;
1512 +
1513 +       if (vb2_is_busy(&dev->buffer_queue))
1514 +               return -EBUSY;
1515 +
1516 +       ret = v4l2_subdev_call(dev->sensor, video, s_dv_timings, timings);
1517 +
1518 +       /* Force recomputation of bytesperline */
1519 +       dev->v_fmt.fmt.pix.bytesperline = 0;
1520 +
1521 +       unicam_reset_format(dev);
1522 +
1523 +       return ret;
1524 +}
1525 +
1526 +static int unicam_query_dv_timings(struct file *file, void *priv,
1527 +                                  struct v4l2_dv_timings *timings)
1528 +{
1529 +       struct unicam_device *dev = video_drvdata(file);
1530 +
1531 +       return v4l2_subdev_call(dev->sensor, video, query_dv_timings, timings);
1532 +}
1533 +
1534 +static int unicam_enum_dv_timings(struct file *file, void *priv,
1535 +                                 struct v4l2_enum_dv_timings *timings)
1536 +{
1537 +       struct unicam_device *dev = video_drvdata(file);
1538 +
1539 +       return v4l2_subdev_call(dev->sensor, pad, enum_dv_timings, timings);
1540 +}
1541 +
1542 +static int unicam_dv_timings_cap(struct file *file, void *priv,
1543 +                                struct v4l2_dv_timings_cap *cap)
1544 +{
1545 +       struct unicam_device *dev = video_drvdata(file);
1546 +
1547 +       return v4l2_subdev_call(dev->sensor, pad, dv_timings_cap, cap);
1548 +}
1549 +
1550 +static int unicam_subscribe_event(struct v4l2_fh *fh,
1551 +                                 const struct v4l2_event_subscription *sub)
1552 +{
1553 +       switch (sub->type) {
1554 +       case V4L2_EVENT_SOURCE_CHANGE:
1555 +               return v4l2_event_subscribe(fh, sub, 4, NULL);
1556 +       }
1557 +
1558 +       return v4l2_ctrl_subscribe_event(fh, sub);
1559 +}
1560 +
1561 +static int unicam_log_status(struct file *file, void *fh)
1562 +{
1563 +       struct unicam_device *dev = video_drvdata(file);
1564 +       struct unicam_cfg *cfg = &dev->cfg;
1565 +       u32 reg;
1566 +
1567 +       /* status for sub devices */
1568 +       v4l2_device_call_all(&dev->v4l2_dev, 0, core, log_status);
1569 +
1570 +       unicam_info(dev, "-----Receiver status-----\n");
1571 +       unicam_info(dev, "V4L2 width/height:   %ux%u\n",
1572 +                   dev->v_fmt.fmt.pix.width, dev->v_fmt.fmt.pix.height);
1573 +       unicam_info(dev, "Mediabus format:     %08x\n", dev->fmt->code);
1574 +       unicam_info(dev, "V4L2 format:         " V4L2_FOURCC_CONV "\n",
1575 +                   V4L2_FOURCC_CONV_ARGS(dev->v_fmt.fmt.pix.pixelformat));
1576 +       reg = reg_read(&dev->cfg, UNICAM_IPIPE);
1577 +       unicam_info(dev, "Unpacking/packing:   %u / %u\n",
1578 +                   get_field(reg, UNICAM_PUM_MASK),
1579 +                   get_field(reg, UNICAM_PPM_MASK));
1580 +       unicam_info(dev, "----Live data----\n");
1581 +       unicam_info(dev, "Programmed stride:   %4u\n",
1582 +                   reg_read(cfg, UNICAM_IBLS));
1583 +       unicam_info(dev, "Detected resolution: %ux%u\n",
1584 +                   reg_read(cfg, UNICAM_IHSTA),
1585 +                   reg_read(cfg, UNICAM_IVSTA));
1586 +       unicam_info(dev, "Write pointer:       %08x\n",
1587 +                   reg_read(cfg, UNICAM_IBWP));
1588 +
1589 +       return 0;
1590 +}
1591 +
1592 +static void unicam_notify(struct v4l2_subdev *sd,
1593 +                         unsigned int notification, void *arg)
1594 +{
1595 +       struct unicam_device *dev =
1596 +               container_of(sd->v4l2_dev, struct unicam_device, v4l2_dev);
1597 +
1598 +       switch (notification) {
1599 +       case V4L2_DEVICE_NOTIFY_EVENT:
1600 +               v4l2_event_queue(&dev->video_dev, arg);
1601 +               break;
1602 +       default:
1603 +               break;
1604 +       }
1605 +}
1606 +
1607 +static const struct vb2_ops unicam_video_qops = {
1608 +       .wait_prepare           = vb2_ops_wait_prepare,
1609 +       .wait_finish            = vb2_ops_wait_finish,
1610 +       .queue_setup            = unicam_queue_setup,
1611 +       .buf_prepare            = unicam_buffer_prepare,
1612 +       .buf_queue              = unicam_buffer_queue,
1613 +       .start_streaming        = unicam_start_streaming,
1614 +       .stop_streaming         = unicam_stop_streaming,
1615 +};
1616 +
1617 +/* unicam capture driver file operations */
1618 +static const struct v4l2_file_operations unicam_fops = {
1619 +       .owner          = THIS_MODULE,
1620 +       .open           = v4l2_fh_open,
1621 +       .release        = vb2_fop_release,
1622 +       .read           = vb2_fop_read,
1623 +       .poll           = vb2_fop_poll,
1624 +       .unlocked_ioctl = video_ioctl2,
1625 +       .mmap           = vb2_fop_mmap,
1626 +};
1627 +
1628 +/* unicam capture ioctl operations */
1629 +static const struct v4l2_ioctl_ops unicam_ioctl_ops = {
1630 +       .vidioc_querycap                = unicam_querycap,
1631 +       .vidioc_enum_fmt_vid_cap        = unicam_enum_fmt_vid_cap,
1632 +       .vidioc_g_fmt_vid_cap           = unicam_g_fmt_vid_cap,
1633 +       .vidioc_s_fmt_vid_cap           = unicam_s_fmt_vid_cap,
1634 +       .vidioc_try_fmt_vid_cap         = unicam_try_fmt_vid_cap,
1635 +
1636 +       .vidioc_enum_input              = unicam_enum_input,
1637 +       .vidioc_g_input                 = unicam_g_input,
1638 +       .vidioc_s_input                 = unicam_s_input,
1639 +
1640 +       .vidioc_querystd                = unicam_querystd,
1641 +       .vidioc_s_std                   = unicam_s_std,
1642 +       .vidioc_g_std                   = unicam_g_std,
1643 +
1644 +       .vidioc_g_edid                  = unicam_g_edid,
1645 +       .vidioc_s_edid                  = unicam_s_edid,
1646 +
1647 +       .vidioc_s_dv_timings            = unicam_s_dv_timings,
1648 +       .vidioc_g_dv_timings            = unicam_g_dv_timings,
1649 +       .vidioc_query_dv_timings        = unicam_query_dv_timings,
1650 +       .vidioc_enum_dv_timings         = unicam_enum_dv_timings,
1651 +       .vidioc_dv_timings_cap          = unicam_dv_timings_cap,
1652 +
1653 +       .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
1654 +       .vidioc_create_bufs             = vb2_ioctl_create_bufs,
1655 +       .vidioc_prepare_buf             = vb2_ioctl_prepare_buf,
1656 +       .vidioc_querybuf                = vb2_ioctl_querybuf,
1657 +       .vidioc_qbuf                    = vb2_ioctl_qbuf,
1658 +       .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
1659 +       .vidioc_expbuf                  = vb2_ioctl_expbuf,
1660 +       .vidioc_streamon                = vb2_ioctl_streamon,
1661 +       .vidioc_streamoff               = vb2_ioctl_streamoff,
1662 +
1663 +       .vidioc_log_status              = unicam_log_status,
1664 +       .vidioc_subscribe_event         = unicam_subscribe_event,
1665 +       .vidioc_unsubscribe_event       = v4l2_event_unsubscribe,
1666 +};
1667 +
1668 +/*
1669 + * Adds an entry to the active_fmts array
1670 + * Returns non-zero if attempting to write off the end of the array.
1671 + */
1672 +static int unicam_add_active_format(struct unicam_device *unicam,
1673 +                                   const struct unicam_fmt *fmt)
1674 +{
1675 +       //Ensure we don't run off the end of the array.
1676 +       if (unicam->num_active_fmt >= MAX_POSSIBLE_PIX_FMTS)
1677 +               return 1;
1678 +
1679 +       unicam->active_fmts[unicam->num_active_fmt] = *fmt;
1680 +       unicam_dbg(2, unicam,
1681 +                  "matched fourcc: " V4L2_FOURCC_CONV ": code: %04x idx: %d\n",
1682 +                  V4L2_FOURCC_CONV_ARGS(fmt->fourcc),
1683 +                  fmt->code, unicam->num_active_fmt);
1684 +       unicam->num_active_fmt++;
1685 +
1686 +       return 0;
1687 +}
1688 +
1689 +static int
1690 +unicam_async_bound(struct v4l2_async_notifier *notifier,
1691 +                  struct v4l2_subdev *subdev,
1692 +                  struct v4l2_async_subdev *asd)
1693 +{
1694 +       struct unicam_device *unicam = container_of(notifier->v4l2_dev,
1695 +                                              struct unicam_device, v4l2_dev);
1696 +       struct v4l2_subdev_mbus_code_enum mbus_code;
1697 +       int ret = 0;
1698 +       int j;
1699 +
1700 +       if (unicam->sensor) {
1701 +               unicam_info(unicam, "Rejecting subdev %s (Already set!!)",
1702 +                           subdev->name);
1703 +               return 0;
1704 +       }
1705 +
1706 +       unicam->sensor = subdev;
1707 +       unicam_dbg(1, unicam, "Using sensor %s for capture\n", subdev->name);
1708 +
1709 +       /* Enumerate sub device formats and enable all matching local formats */
1710 +       unicam->num_active_fmt = 0;
1711 +       unicam_dbg(2, unicam, "Get supported formats...\n");
1712 +       for (j = 0; ret != -EINVAL && ret != -ENOIOCTLCMD; ++j) {
1713 +               const struct unicam_fmt *fmt = NULL;
1714 +               int k;
1715 +
1716 +               memset(&mbus_code, 0, sizeof(mbus_code));
1717 +               mbus_code.index = j;
1718 +               ret = v4l2_subdev_call(subdev, pad, enum_mbus_code,
1719 +                                      NULL, &mbus_code);
1720 +               if (ret < 0) {
1721 +                       unicam_dbg(2, unicam,
1722 +                                  "subdev->enum_mbus_code idx %d returned %d - continue\n",
1723 +                                  j, ret);
1724 +                       continue;
1725 +               }
1726 +
1727 +               unicam_dbg(2, unicam, "subdev %s: code: %04x idx: %d\n",
1728 +                          subdev->name, mbus_code.code, j);
1729 +
1730 +               for (k = 0; k < ARRAY_SIZE(formats); k++) {
1731 +                       if (mbus_code.code == formats[k].code) {
1732 +                               fmt = &formats[k];
1733 +                               break;
1734 +                       }
1735 +               }
1736 +               unicam_dbg(2, unicam, "fmt %04x returned as %p, V4L2 FOURCC %04x, csi_dt %02X\n",
1737 +                          mbus_code.code, fmt, fmt ? fmt->fourcc : 0,
1738 +                          fmt ? fmt->csi_dt : 0);
1739 +               if (fmt) {
1740 +                       if (unicam_add_active_format(unicam, fmt)) {
1741 +                               unicam_dbg(1, unicam, "Active fmt list truncated\n");
1742 +                               break;
1743 +                       }
1744 +               }
1745 +       }
1746 +       unicam_dbg(2, unicam,
1747 +                  "Done all formats\n");
1748 +       dump_active_formats(unicam);
1749 +
1750 +       return 0;
1751 +}
1752 +
1753 +static int unicam_probe_complete(struct unicam_device *unicam)
1754 +{
1755 +       struct video_device *vdev;
1756 +       struct vb2_queue *q;
1757 +       struct v4l2_mbus_framefmt mbus_fmt = {0};
1758 +       const struct unicam_fmt *fmt;
1759 +       int ret;
1760 +
1761 +       v4l2_set_subdev_hostdata(unicam->sensor, unicam);
1762 +
1763 +       unicam->v4l2_dev.notify = unicam_notify;
1764 +
1765 +       unicam->sensor_config = v4l2_subdev_alloc_pad_config(unicam->sensor);
1766 +       if (!unicam->sensor_config)
1767 +               return -ENOMEM;
1768 +
1769 +       ret = __subdev_get_format(unicam, &mbus_fmt);
1770 +       if (ret) {
1771 +               unicam_err(unicam, "Failed to get_format - ret %d\n", ret);
1772 +               return ret;
1773 +       }
1774 +
1775 +       fmt = find_format_by_code(unicam, mbus_fmt.code);
1776 +       if (!fmt) {
1777 +               /* Default image format not valid. Choose first active fmt. */
1778 +               fmt = &unicam->active_fmts[0];
1779 +               mbus_fmt.code = fmt->code;
1780 +               ret = __subdev_set_format(unicam, &mbus_fmt);
1781 +               if (ret)
1782 +                       return -EINVAL;
1783 +       }
1784 +       if (mbus_fmt.field != V4L2_FIELD_NONE) {
1785 +               /* Interlaced not supported - disable it now. */
1786 +               mbus_fmt.field = V4L2_FIELD_NONE;
1787 +               ret = __subdev_set_format(unicam, &mbus_fmt);
1788 +               if (ret)
1789 +                       return -EINVAL;
1790 +       }
1791 +
1792 +       unicam->fmt = fmt;
1793 +       unicam->v_fmt.fmt.pix.pixelformat = fmt->fourcc;
1794 +
1795 +       /* Read current subdev format */
1796 +       unicam_reset_format(unicam);
1797 +
1798 +       if (v4l2_subdev_has_op(unicam->sensor, video, s_std)) {
1799 +               v4l2_std_id tvnorms;
1800 +
1801 +               if (WARN_ON(!v4l2_subdev_has_op(unicam->sensor, video,
1802 +                                               g_tvnorms)))
1803 +                       /*
1804 +                        * Subdevice should not advertise s_std but not
1805 +                        * g_tvnorms
1806 +                        */
1807 +                       return -EINVAL;
1808 +
1809 +               ret = v4l2_subdev_call(unicam->sensor, video,
1810 +                                      g_tvnorms, &tvnorms);
1811 +               if (WARN_ON(ret))
1812 +                       return -EINVAL;
1813 +               unicam->video_dev.tvnorms |= tvnorms;
1814 +       }
1815 +
1816 +       spin_lock_init(&unicam->dma_queue_lock);
1817 +       mutex_init(&unicam->lock);
1818 +
1819 +       /* Add controls from the subdevice */
1820 +       ret = v4l2_ctrl_add_handler(&unicam->ctrl_handler,
1821 +                                   unicam->sensor->ctrl_handler, NULL);
1822 +       if (ret < 0)
1823 +               return ret;
1824 +
1825 +       q = &unicam->buffer_queue;
1826 +       q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1827 +       q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
1828 +       q->drv_priv = unicam;
1829 +       q->ops = &unicam_video_qops;
1830 +       q->mem_ops = &vb2_dma_contig_memops;
1831 +       q->buf_struct_size = sizeof(struct unicam_buffer);
1832 +       q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1833 +       q->lock = &unicam->lock;
1834 +       q->min_buffers_needed = 2;
1835 +       q->dev = &unicam->pdev->dev;
1836 +
1837 +       ret = vb2_queue_init(q);
1838 +       if (ret) {
1839 +               unicam_err(unicam, "vb2_queue_init() failed\n");
1840 +               return ret;
1841 +       }
1842 +
1843 +       INIT_LIST_HEAD(&unicam->dma_queue.active);
1844 +
1845 +       vdev = &unicam->video_dev;
1846 +       strlcpy(vdev->name, UNICAM_MODULE_NAME, sizeof(vdev->name));
1847 +       vdev->release = video_device_release_empty;
1848 +       vdev->fops = &unicam_fops;
1849 +       vdev->ioctl_ops = &unicam_ioctl_ops;
1850 +       vdev->v4l2_dev = &unicam->v4l2_dev;
1851 +       vdev->vfl_dir = VFL_DIR_RX;
1852 +       vdev->queue = q;
1853 +       vdev->lock = &unicam->lock;
1854 +       vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
1855 +                           V4L2_CAP_READWRITE;
1856 +
1857 +       /* If the source has no controls then remove our ctrl handler. */
1858 +       if (list_empty(&unicam->ctrl_handler.ctrls))
1859 +               unicam->v4l2_dev.ctrl_handler = NULL;
1860 +
1861 +       video_set_drvdata(vdev, unicam);
1862 +       ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
1863 +       if (ret) {
1864 +               unicam_err(unicam, "Unable to register video device.\n");
1865 +               return ret;
1866 +       }
1867 +
1868 +       if (!v4l2_subdev_has_op(unicam->sensor, video, s_std)) {
1869 +               v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_STD);
1870 +               v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_STD);
1871 +               v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUMSTD);
1872 +       }
1873 +       if (!v4l2_subdev_has_op(unicam->sensor, video, querystd))
1874 +               v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERYSTD);
1875 +       if (!v4l2_subdev_has_op(unicam->sensor, video, s_dv_timings)) {
1876 +               v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_EDID);
1877 +               v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_EDID);
1878 +               v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_DV_TIMINGS_CAP);
1879 +               v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_DV_TIMINGS);
1880 +               v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_DV_TIMINGS);
1881 +               v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUM_DV_TIMINGS);
1882 +               v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERY_DV_TIMINGS);
1883 +       }
1884 +
1885 +       ret = v4l2_device_register_subdev_nodes(&unicam->v4l2_dev);
1886 +       if (ret) {
1887 +               unicam_err(unicam,
1888 +                          "Unable to register subdev nodes.\n");
1889 +               video_unregister_device(&unicam->video_dev);
1890 +               return ret;
1891 +       }
1892 +
1893 +       return 0;
1894 +}
1895 +
1896 +static int unicam_async_complete(struct v4l2_async_notifier *notifier)
1897 +{
1898 +       struct unicam_device *unicam = container_of(notifier->v4l2_dev,
1899 +                                       struct unicam_device, v4l2_dev);
1900 +
1901 +       return unicam_probe_complete(unicam);
1902 +}
1903 +
1904 +static const struct v4l2_async_notifier_operations unicam_async_ops = {
1905 +       .bound = unicam_async_bound,
1906 +       .complete = unicam_async_complete,
1907 +};
1908 +
1909 +static int of_unicam_connect_subdevs(struct unicam_device *dev)
1910 +{
1911 +       struct platform_device *pdev = dev->pdev;
1912 +       struct device_node *parent, *ep_node = NULL, *remote_ep = NULL,
1913 +                       *sensor_node = NULL;
1914 +       struct v4l2_fwnode_endpoint *ep;
1915 +       struct v4l2_async_subdev *asd;
1916 +       struct v4l2_async_subdev **subdevs = NULL;
1917 +       unsigned int peripheral_data_lanes;
1918 +       int ret = -EINVAL;
1919 +       unsigned int lane;
1920 +
1921 +       parent = pdev->dev.of_node;
1922 +
1923 +       asd = &dev->asd;
1924 +       ep = &dev->endpoint;
1925 +
1926 +       ep_node = of_graph_get_next_endpoint(parent, NULL);
1927 +       if (!ep_node) {
1928 +               unicam_dbg(3, dev, "can't get next endpoint\n");
1929 +               goto cleanup_exit;
1930 +       }
1931 +
1932 +       unicam_dbg(3, dev, "ep_node is %s\n", ep_node->name);
1933 +
1934 +       v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), ep);
1935 +
1936 +       for (lane = 0; lane < ep->bus.mipi_csi2.num_data_lanes; lane++) {
1937 +               if (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {
1938 +                       unicam_err(dev, "Local endpoint - data lane reordering not supported\n");
1939 +                       goto cleanup_exit;
1940 +               }
1941 +       }
1942 +
1943 +       peripheral_data_lanes = ep->bus.mipi_csi2.num_data_lanes;
1944 +
1945 +       sensor_node = of_graph_get_remote_port_parent(ep_node);
1946 +       if (!sensor_node) {
1947 +               unicam_dbg(3, dev, "can't get remote parent\n");
1948 +               goto cleanup_exit;
1949 +       }
1950 +       unicam_dbg(3, dev, "sensor_node is %s\n", sensor_node->name);
1951 +       asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
1952 +       asd->match.fwnode = of_fwnode_handle(sensor_node);
1953 +
1954 +       remote_ep = of_graph_get_remote_endpoint(ep_node);
1955 +       if (!remote_ep) {
1956 +               unicam_dbg(3, dev, "can't get remote-endpoint\n");
1957 +               goto cleanup_exit;
1958 +       }
1959 +       unicam_dbg(3, dev, "remote_ep is %s\n", remote_ep->name);
1960 +       v4l2_fwnode_endpoint_parse(of_fwnode_handle(remote_ep), ep);
1961 +       unicam_dbg(3, dev, "parsed remote_ep to endpoint. nr_of_link_frequencies %u, bus_type %u\n",
1962 +                  ep->nr_of_link_frequencies, ep->bus_type);
1963 +
1964 +       switch (ep->bus_type) {
1965 +       case V4L2_MBUS_CSI2:
1966 +               if (ep->bus.mipi_csi2.num_data_lanes >
1967 +                               peripheral_data_lanes) {
1968 +                       unicam_err(dev, "Subdevice %s wants too many data lanes (%u > %u)\n",
1969 +                                  sensor_node->name,
1970 +                                  ep->bus.mipi_csi2.num_data_lanes,
1971 +                                  peripheral_data_lanes);
1972 +                       goto cleanup_exit;
1973 +               }
1974 +               for (lane = 0;
1975 +                    lane < ep->bus.mipi_csi2.num_data_lanes;
1976 +                    lane++) {
1977 +                       if (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {
1978 +                               unicam_err(dev, "Subdevice %s - incompatible data lane config\n",
1979 +                                          sensor_node->name);
1980 +                               goto cleanup_exit;
1981 +                       }
1982 +               }
1983 +               dev->max_data_lanes = ep->bus.mipi_csi2.num_data_lanes;
1984 +               dev->bus_flags = ep->bus.mipi_csi2.flags;
1985 +               break;
1986 +       case V4L2_MBUS_CCP2:
1987 +               if (ep->bus.mipi_csi1.clock_lane != 0 ||
1988 +                   ep->bus.mipi_csi1.data_lane != 1) {
1989 +                       unicam_err(dev, "Subdevice %s incompatible lane config\n",
1990 +                                  sensor_node->name);
1991 +                       goto cleanup_exit;
1992 +               }
1993 +               dev->max_data_lanes = 1;
1994 +               dev->bus_flags = ep->bus.mipi_csi1.strobe;
1995 +               break;
1996 +       default:
1997 +               /* Unsupported bus type */
1998 +               unicam_err(dev, "sub-device %s is not a CSI2 or CCP2 device %d\n",
1999 +                          sensor_node->name, ep->bus_type);
2000 +               goto cleanup_exit;
2001 +       }
2002 +
2003 +       /* Store bus type - CSI2 or CCP2 */
2004 +       dev->bus_type = ep->bus_type;
2005 +       unicam_dbg(3, dev, "bus_type is %d\n", dev->bus_type);
2006 +
2007 +       /* Store Virtual Channel number */
2008 +       dev->virtual_channel = ep->base.id;
2009 +
2010 +       unicam_dbg(3, dev, "v4l2-endpoint: %s\n",
2011 +                  dev->bus_type == V4L2_MBUS_CSI2 ? "CSI2" : "CCP2");
2012 +       unicam_dbg(3, dev, "Virtual Channel=%d\n", dev->virtual_channel);
2013 +       if (dev->bus_type == V4L2_MBUS_CSI2)
2014 +               unicam_dbg(3, dev, "flags=0x%08x\n", ep->bus.mipi_csi2.flags);
2015 +       unicam_dbg(3, dev, "num_data_lanes=%d\n", dev->max_data_lanes);
2016 +
2017 +       unicam_dbg(1, dev, "found sub-device %s\n", sensor_node->name);
2018 +
2019 +       subdevs = devm_kzalloc(&dev->pdev->dev, sizeof(*subdevs), GFP_KERNEL);
2020 +       if (!subdevs) {
2021 +               ret = -ENOMEM;
2022 +               goto cleanup_exit;
2023 +       }
2024 +       subdevs[0] = asd;
2025 +       dev->notifier.subdevs = subdevs;
2026 +       dev->notifier.num_subdevs = 1;
2027 +       dev->notifier.ops = &unicam_async_ops;
2028 +       ret = v4l2_async_notifier_register(&dev->v4l2_dev,
2029 +                                          &dev->notifier);
2030 +       if (ret) {
2031 +               unicam_err(dev, "Error registering async notifier - ret %d\n",
2032 +                          ret);
2033 +               ret = -EINVAL;
2034 +       }
2035 +
2036 +cleanup_exit:
2037 +       if (remote_ep)
2038 +               of_node_put(remote_ep);
2039 +       if (sensor_node)
2040 +               of_node_put(sensor_node);
2041 +       if (ep_node)
2042 +               of_node_put(ep_node);
2043 +
2044 +       return ret;
2045 +}
2046 +
2047 +static int unicam_probe(struct platform_device *pdev)
2048 +{
2049 +       struct unicam_cfg *unicam_cfg;
2050 +       struct unicam_device *unicam;
2051 +       struct v4l2_ctrl_handler *hdl;
2052 +       struct resource *res;
2053 +       int ret;
2054 +
2055 +       unicam = devm_kzalloc(&pdev->dev, sizeof(*unicam), GFP_KERNEL);
2056 +       if (!unicam)
2057 +               return -ENOMEM;
2058 +
2059 +       unicam->pdev = pdev;
2060 +       unicam_cfg = &unicam->cfg;
2061 +
2062 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2063 +       unicam_cfg->base = devm_ioremap_resource(&pdev->dev, res);
2064 +       if (IS_ERR(unicam_cfg->base)) {
2065 +               unicam_err(unicam, "Failed to get main io block\n");
2066 +               return PTR_ERR(unicam_cfg->base);
2067 +       }
2068 +
2069 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2070 +       unicam_cfg->clk_gate_base = devm_ioremap_resource(&pdev->dev, res);
2071 +       if (IS_ERR(unicam_cfg->clk_gate_base)) {
2072 +               unicam_err(unicam, "Failed to get 2nd io block\n");
2073 +               return PTR_ERR(unicam_cfg->clk_gate_base);
2074 +       }
2075 +
2076 +       unicam->clock = devm_clk_get(&pdev->dev, "lp");
2077 +       if (IS_ERR(unicam->clock)) {
2078 +               unicam_err(unicam, "Failed to get clock\n");
2079 +               return PTR_ERR(unicam->clock);
2080 +       }
2081 +
2082 +       ret = platform_get_irq(pdev, 0);
2083 +       if (ret <= 0) {
2084 +               dev_err(&pdev->dev, "No IRQ resource\n");
2085 +               return -ENODEV;
2086 +       }
2087 +
2088 +       ret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,
2089 +                              "unicam_capture0", unicam);
2090 +       if (ret) {
2091 +               dev_err(&pdev->dev, "Unable to request interrupt\n");
2092 +               return -EINVAL;
2093 +       }
2094 +
2095 +       ret = v4l2_device_register(&pdev->dev, &unicam->v4l2_dev);
2096 +       if (ret) {
2097 +               unicam_err(unicam,
2098 +                          "Unable to register v4l2 device.\n");
2099 +               return ret;
2100 +       }
2101 +
2102 +       /* Reserve space for the controls */
2103 +       hdl = &unicam->ctrl_handler;
2104 +       ret = v4l2_ctrl_handler_init(hdl, 16);
2105 +       if (ret < 0)
2106 +               goto probe_out_v4l2_unregister;
2107 +       unicam->v4l2_dev.ctrl_handler = hdl;
2108 +
2109 +       /* set the driver data in platform device */
2110 +       platform_set_drvdata(pdev, unicam);
2111 +
2112 +       ret = of_unicam_connect_subdevs(unicam);
2113 +       if (ret) {
2114 +               dev_err(&pdev->dev, "Failed to connect subdevs\n");
2115 +               goto free_hdl;
2116 +       }
2117 +
2118 +       /* Enable the block power domain */
2119 +       pm_runtime_enable(&pdev->dev);
2120 +
2121 +       return 0;
2122 +
2123 +free_hdl:
2124 +       v4l2_ctrl_handler_free(hdl);
2125 +probe_out_v4l2_unregister:
2126 +       v4l2_device_unregister(&unicam->v4l2_dev);
2127 +       return ret;
2128 +}
2129 +
2130 +static int unicam_remove(struct platform_device *pdev)
2131 +{
2132 +       struct unicam_device *unicam = platform_get_drvdata(pdev);
2133 +
2134 +       unicam_dbg(2, unicam, "%s\n", __func__);
2135 +
2136 +       pm_runtime_disable(&pdev->dev);
2137 +
2138 +       v4l2_async_notifier_unregister(&unicam->notifier);
2139 +       v4l2_ctrl_handler_free(&unicam->ctrl_handler);
2140 +       v4l2_device_unregister(&unicam->v4l2_dev);
2141 +       video_unregister_device(&unicam->video_dev);
2142 +       if (unicam->sensor_config)
2143 +               v4l2_subdev_free_pad_config(unicam->sensor_config);
2144 +
2145 +       return 0;
2146 +}
2147 +
2148 +static const struct of_device_id unicam_of_match[] = {
2149 +       { .compatible = "brcm,bcm2835-unicam", },
2150 +       { /* sentinel */ },
2151 +};
2152 +MODULE_DEVICE_TABLE(of, unicam_of_match);
2153 +
2154 +static struct platform_driver unicam_driver = {
2155 +       .probe          = unicam_probe,
2156 +       .remove         = unicam_remove,
2157 +       .driver = {
2158 +               .name   = UNICAM_MODULE_NAME,
2159 +               .of_match_table = of_match_ptr(unicam_of_match),
2160 +       },
2161 +};
2162 +
2163 +module_platform_driver(unicam_driver);
2164 +
2165 +MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.org>");
2166 +MODULE_DESCRIPTION("BCM2835 Unicam driver");
2167 +MODULE_LICENSE("GPL");
2168 +MODULE_VERSION(UNICAM_VERSION);
2169 --- /dev/null
2170 +++ b/drivers/media/platform/bcm2835/vc4-regs-unicam.h
2171 @@ -0,0 +1,266 @@
2172 +/* SPDX-License-Identifier: GPL-2.0-only */
2173 +
2174 +/*
2175 + * Copyright (C) 2017 Raspberry Pi Trading.
2176 + * Dave Stevenson <dave.stevenson@raspberrypi.org>
2177 + *
2178 + * This program is free software; you can redistribute it and/or modify
2179 + * it under the terms of the GNU General Public License version 2 as
2180 + * published by the Free Software Foundation.
2181 + *
2182 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2183 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
2184 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2185 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
2186 + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
2187 + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
2188 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
2189 + * SOFTWARE.
2190 + */
2191 +
2192 +#ifndef VC4_REGS_UNICAM_H
2193 +#define VC4_REGS_UNICAM_H
2194 +
2195 +/*
2196 + * The following values are taken from files found within the code drop
2197 + * made by Broadcom for the BCM21553 Graphics Driver, predominantly in
2198 + * brcm_usrlib/dag/vmcsx/vcinclude/hardware_vc4.h.
2199 + * They have been modified to be only the register offset.
2200 + */
2201 +#define UNICAM_CTRL    0x000
2202 +#define UNICAM_STA     0x004
2203 +#define UNICAM_ANA     0x008
2204 +#define UNICAM_PRI     0x00c
2205 +#define UNICAM_CLK     0x010
2206 +#define UNICAM_CLT     0x014
2207 +#define UNICAM_DAT0    0x018
2208 +#define UNICAM_DAT1    0x01c
2209 +#define UNICAM_DAT2    0x020
2210 +#define UNICAM_DAT3    0x024
2211 +#define UNICAM_DLT     0x028
2212 +#define UNICAM_CMP0    0x02c
2213 +#define UNICAM_CMP1    0x030
2214 +#define UNICAM_CAP0    0x034
2215 +#define UNICAM_CAP1    0x038
2216 +#define UNICAM_ICTL    0x100
2217 +#define UNICAM_ISTA    0x104
2218 +#define UNICAM_IDI0    0x108
2219 +#define UNICAM_IPIPE   0x10c
2220 +#define UNICAM_IBSA0   0x110
2221 +#define UNICAM_IBEA0   0x114
2222 +#define UNICAM_IBLS    0x118
2223 +#define UNICAM_IBWP    0x11c
2224 +#define UNICAM_IHWIN   0x120
2225 +#define UNICAM_IHSTA   0x124
2226 +#define UNICAM_IVWIN   0x128
2227 +#define UNICAM_IVSTA   0x12c
2228 +#define UNICAM_ICC     0x130
2229 +#define UNICAM_ICS     0x134
2230 +#define UNICAM_IDC     0x138
2231 +#define UNICAM_IDPO    0x13c
2232 +#define UNICAM_IDCA    0x140
2233 +#define UNICAM_IDCD    0x144
2234 +#define UNICAM_IDS     0x148
2235 +#define UNICAM_DCS     0x200
2236 +#define UNICAM_DBSA0   0x204
2237 +#define UNICAM_DBEA0   0x208
2238 +#define UNICAM_DBWP    0x20c
2239 +#define UNICAM_DBCTL   0x300
2240 +#define UNICAM_IBSA1   0x304
2241 +#define UNICAM_IBEA1   0x308
2242 +#define UNICAM_IDI1    0x30c
2243 +#define UNICAM_DBSA1   0x310
2244 +#define UNICAM_DBEA1   0x314
2245 +#define UNICAM_MISC    0x400
2246 +
2247 +/*
2248 + * The following bitmasks are from the kernel released by Broadcom
2249 + * for Android - https://android.googlesource.com/kernel/bcm/
2250 + * The Rhea, Hawaii, and Java chips all contain the same VideoCore4
2251 + * Unicam block as BCM2835, as defined in eg
2252 + * arch/arm/mach-rhea/include/mach/rdb_A0/brcm_rdb_cam.h and similar.
2253 + * Values reworked to use the kernel BIT and GENMASK macros.
2254 + *
2255 + * Some of the bit mnenomics have been amended to match the datasheet.
2256 + */
2257 +/* UNICAM_CTRL Register */
2258 +#define UNICAM_CPE             BIT(0)
2259 +#define UNICAM_MEM             BIT(1)
2260 +#define UNICAM_CPR             BIT(2)
2261 +#define UNICAM_CPM_MASK                GENMASK(3, 3)
2262 +#define UNICAM_CPM_CSI2                0
2263 +#define UNICAM_CPM_CCP2                1
2264 +#define UNICAM_SOE             BIT(4)
2265 +#define UNICAM_DCM_MASK                GENMASK(5, 5)
2266 +#define UNICAM_DCM_STROBE      0
2267 +#define UNICAM_DCM_DATA                1
2268 +#define UNICAM_SLS             BIT(6)
2269 +#define UNICAM_PFT_MASK                GENMASK(11, 8)
2270 +#define UNICAM_OET_MASK                GENMASK(20, 12)
2271 +
2272 +/* UNICAM_STA Register */
2273 +#define UNICAM_SYN             BIT(0)
2274 +#define UNICAM_CS              BIT(1)
2275 +#define UNICAM_SBE             BIT(2)
2276 +#define UNICAM_PBE             BIT(3)
2277 +#define UNICAM_HOE             BIT(4)
2278 +#define UNICAM_PLE             BIT(5)
2279 +#define UNICAM_SSC             BIT(6)
2280 +#define UNICAM_CRCE            BIT(7)
2281 +#define UNICAM_OES             BIT(8)
2282 +#define UNICAM_IFO             BIT(9)
2283 +#define UNICAM_OFO             BIT(10)
2284 +#define UNICAM_BFO             BIT(11)
2285 +#define UNICAM_DL              BIT(12)
2286 +#define UNICAM_PS              BIT(13)
2287 +#define UNICAM_IS              BIT(14)
2288 +#define UNICAM_PI0             BIT(15)
2289 +#define UNICAM_PI1             BIT(16)
2290 +#define UNICAM_FSI_S           BIT(17)
2291 +#define UNICAM_FEI_S           BIT(18)
2292 +#define UNICAM_LCI_S           BIT(19)
2293 +#define UNICAM_BUF0_RDY                BIT(20)
2294 +#define UNICAM_BUF0_NO         BIT(21)
2295 +#define UNICAM_BUF1_RDY                BIT(22)
2296 +#define UNICAM_BUF1_NO         BIT(23)
2297 +#define UNICAM_DI              BIT(24)
2298 +
2299 +#define UNICAM_STA_MASK_ALL \
2300 +               (UNICAM_DL + \
2301 +               UNICAM_SBE + \
2302 +               UNICAM_PBE + \
2303 +               UNICAM_HOE + \
2304 +               UNICAM_PLE + \
2305 +               UNICAM_SSC + \
2306 +               UNICAM_CRCE + \
2307 +               UNICAM_IFO + \
2308 +               UNICAM_OFO + \
2309 +               UNICAM_PS + \
2310 +               UNICAM_PI0 + \
2311 +               UNICAM_PI1)
2312 +
2313 +/* UNICAM_ANA Register */
2314 +#define UNICAM_APD             BIT(0)
2315 +#define UNICAM_BPD             BIT(1)
2316 +#define UNICAM_AR              BIT(2)
2317 +#define UNICAM_DDL             BIT(3)
2318 +#define UNICAM_CTATADJ_MASK    GENMASK(7, 4)
2319 +#define UNICAM_PTATADJ_MASK    GENMASK(11, 8)
2320 +
2321 +/* UNICAM_PRI Register */
2322 +#define UNICAM_PE              BIT(0)
2323 +#define UNICAM_PT_MASK         GENMASK(2, 1)
2324 +#define UNICAM_NP_MASK         GENMASK(7, 4)
2325 +#define UNICAM_PP_MASK         GENMASK(11, 8)
2326 +#define UNICAM_BS_MASK         GENMASK(15, 12)
2327 +#define UNICAM_BL_MASK         GENMASK(17, 16)
2328 +
2329 +/* UNICAM_CLK Register */
2330 +#define UNICAM_CLE             BIT(0)
2331 +#define UNICAM_CLPD            BIT(1)
2332 +#define UNICAM_CLLPE           BIT(2)
2333 +#define UNICAM_CLHSE           BIT(3)
2334 +#define UNICAM_CLTRE           BIT(4)
2335 +#define UNICAM_CLAC_MASK       GENMASK(8, 5)
2336 +#define UNICAM_CLSTE           BIT(29)
2337 +
2338 +/* UNICAM_CLT Register */
2339 +#define UNICAM_CLT1_MASK       GENMASK(7, 0)
2340 +#define UNICAM_CLT2_MASK       GENMASK(15, 8)
2341 +
2342 +/* UNICAM_DATn Registers */
2343 +#define UNICAM_DLE             BIT(0)
2344 +#define UNICAM_DLPD            BIT(1)
2345 +#define UNICAM_DLLPE           BIT(2)
2346 +#define UNICAM_DLHSE           BIT(3)
2347 +#define UNICAM_DLTRE           BIT(4)
2348 +#define UNICAM_DLSM            BIT(5)
2349 +#define UNICAM_DLFO            BIT(28)
2350 +#define UNICAM_DLSTE           BIT(29)
2351 +
2352 +#define UNICAM_DAT_MASK_ALL (UNICAM_DLSTE + UNICAM_DLFO)
2353 +
2354 +/* UNICAM_DLT Register */
2355 +#define UNICAM_DLT1_MASK       GENMASK(7, 0)
2356 +#define UNICAM_DLT2_MASK       GENMASK(15, 8)
2357 +#define UNICAM_DLT3_MASK       GENMASK(23, 16)
2358 +
2359 +/* UNICAM_ICTL Register */
2360 +#define UNICAM_FSIE            BIT(0)
2361 +#define UNICAM_FEIE            BIT(1)
2362 +#define UNICAM_IBOB            BIT(2)
2363 +#define UNICAM_FCM             BIT(3)
2364 +#define UNICAM_TFC             BIT(4)
2365 +#define UNICAM_LIP_MASK                GENMASK(6, 5)
2366 +#define UNICAM_LCIE_MASK       GENMASK(28, 16)
2367 +
2368 +/* UNICAM_IDI0/1 Register */
2369 +#define UNICAM_ID0_MASK                GENMASK(7, 0)
2370 +#define UNICAM_ID1_MASK                GENMASK(15, 8)
2371 +#define UNICAM_ID2_MASK                GENMASK(23, 16)
2372 +#define UNICAM_ID3_MASK                GENMASK(31, 24)
2373 +
2374 +/* UNICAM_ISTA Register */
2375 +#define UNICAM_FSI             BIT(0)
2376 +#define UNICAM_FEI             BIT(1)
2377 +#define UNICAM_LCI             BIT(2)
2378 +
2379 +#define UNICAM_ISTA_MASK_ALL (UNICAM_FSI + UNICAM_FEI + UNICAM_LCI)
2380 +
2381 +/* UNICAM_IPIPE Register */
2382 +#define UNICAM_PUM_MASK                GENMASK(2, 0)
2383 +               /* Unpacking modes */
2384 +               #define UNICAM_PUM_NONE         0
2385 +               #define UNICAM_PUM_UNPACK6      1
2386 +               #define UNICAM_PUM_UNPACK7      2
2387 +               #define UNICAM_PUM_UNPACK8      3
2388 +               #define UNICAM_PUM_UNPACK10     4
2389 +               #define UNICAM_PUM_UNPACK12     5
2390 +               #define UNICAM_PUM_UNPACK14     6
2391 +               #define UNICAM_PUM_UNPACK16     7
2392 +#define UNICAM_DDM_MASK                GENMASK(6, 3)
2393 +#define UNICAM_PPM_MASK                GENMASK(9, 7)
2394 +               /* Packing modes */
2395 +               #define UNICAM_PPM_NONE         0
2396 +               #define UNICAM_PPM_PACK8        1
2397 +               #define UNICAM_PPM_PACK10       2
2398 +               #define UNICAM_PPM_PACK12       3
2399 +               #define UNICAM_PPM_PACK14       4
2400 +               #define UNICAM_PPM_PACK16       5
2401 +#define UNICAM_DEM_MASK                GENMASK(11, 10)
2402 +#define UNICAM_DEBL_MASK       GENMASK(14, 12)
2403 +#define UNICAM_ICM_MASK                GENMASK(16, 15)
2404 +#define UNICAM_IDM_MASK                GENMASK(17, 17)
2405 +
2406 +/* UNICAM_ICC Register */
2407 +#define UNICAM_ICFL_MASK       GENMASK(4, 0)
2408 +#define UNICAM_ICFH_MASK       GENMASK(9, 5)
2409 +#define UNICAM_ICST_MASK       GENMASK(12, 10)
2410 +#define UNICAM_ICLT_MASK       GENMASK(15, 13)
2411 +#define UNICAM_ICLL_MASK       GENMASK(31, 16)
2412 +
2413 +/* UNICAM_DCS Register */
2414 +#define UNICAM_DIE             BIT(0)
2415 +#define UNICAM_DIM             BIT(1)
2416 +#define UNICAM_DBOB            BIT(3)
2417 +#define UNICAM_FDE             BIT(4)
2418 +#define UNICAM_LDP             BIT(5)
2419 +#define UNICAM_EDL_MASK                GENMASK(15, 8)
2420 +
2421 +/* UNICAM_DBCTL Register */
2422 +#define UNICAM_DBEN            BIT(0)
2423 +#define UNICAM_BUF0_IE         BIT(1)
2424 +#define UNICAM_BUF1_IE         BIT(2)
2425 +
2426 +/* UNICAM_CMP[0,1] register */
2427 +#define UNICAM_PCE             BIT(31)
2428 +#define UNICAM_GI              BIT(9)
2429 +#define UNICAM_CPH             BIT(8)
2430 +#define UNICAM_PCVC_MASK       GENMASK(7, 6)
2431 +#define UNICAM_PCDT_MASK       GENMASK(5, 0)
2432 +
2433 +/* UNICAM_MISC register */
2434 +#define UNICAM_FL0             BIT(6)
2435 +#define UNICAM_FL1             BIT(9)
2436 +
2437 +#endif