1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Allied Telesis Labs
12 #include <linux/mbus.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/soc.h>
16 #include "../common/gpio_hog.h"
18 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
19 #include <../serdes/a38x/high_speed_env_spec.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 #define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
25 #define CONFIG_NVS_LOCATION 0xf4800000
26 #define CONFIG_NVS_SIZE (512 << 10)
28 static struct serdes_map board_serdes_map[] = {
29 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
30 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
31 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
32 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
33 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
34 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
37 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
39 *serdes_map_array = board_serdes_map;
40 *count = ARRAY_SIZE(board_serdes_map);
45 * Define the DDR layout / topology here in the board file. This will
46 * be used by the DDR3 init code in the SPL U-Boot version to configure
47 * the DDR3 controller.
49 static struct mv_ddr_topology_map board_topology_map = {
51 0x1, /* active interfaces */
52 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
58 SPEED_BIN_DDR_1866M, /* speed_bin */
59 MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
60 MV_DDR_DIE_CAP_4GBIT, /* die capacity */
61 MV_DDR_FREQ_SAR, /* frequency */
62 0, 0, /* cas_l cas_wl */
63 MV_DDR_TEMP_LOW, /* temperature */
64 MV_DDR_TIM_2T} }, /* timing */
65 BUS_MASK_32BIT_ECC, /* subphys mask */
66 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
67 { {0} }, /* raw spd data */
68 {0} /* timing parameters */
71 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
73 /* Return the board topology as defined in the board code */
74 return &board_topology_map;
77 int board_early_init_f(void)
80 writel(0x00001111, MVEBU_MPP_BASE + 0x00);
81 writel(0x00000000, MVEBU_MPP_BASE + 0x04);
82 writel(0x55000000, MVEBU_MPP_BASE + 0x08);
83 writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
84 writel(0x55555555, MVEBU_MPP_BASE + 0x10);
85 writel(0x00100565, MVEBU_MPP_BASE + 0x14);
86 writel(0x40000000, MVEBU_MPP_BASE + 0x18);
87 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
92 void spl_board_init(void)
98 /* address of boot parameters */
99 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
102 mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
103 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
105 /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
106 writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
113 void arch_preboot_os(void)
115 #ifdef CONFIG_WATCHDOG
116 wdt_stop(gd->watchdog_dev);
120 static int led_7seg_init(unsigned int segments)
125 struct gpio_desc desc[8];
127 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
132 ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
133 "segment-gpios", desc,
134 ARRAY_SIZE(desc), GPIOD_IS_OUT);
138 for (i = 0; i < ARRAY_SIZE(desc); i++) {
139 ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
147 #ifdef CONFIG_MISC_INIT_R
148 int misc_init_r(void)
150 static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
153 gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
154 gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
155 gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
156 gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
158 #ifdef MTDPARTS_MTDOOPS
159 env_set("mtdoops", MTDPARTS_MTDOOPS);
168 #ifdef CONFIG_DISPLAY_BOARDINFO
171 puts("Board: " CONFIG_SYS_BOARD "\n");