2 * Qualcomm/Atheros Wireless SOC common registers definitions
4 * Copyright (C) 2014 Piotr Dymacz <piotr@dymacz.pl>
5 * Copyright (C) 2008-2010 Atheros Communications Inc.
8 * Linux/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
10 * SPDX-License-Identifier:GPL-2.0
13 #ifndef _QCA_SOC_COMMON_H_
14 #define _QCA_SOC_COMMON_H_
16 #include <soc/soc_common.h>
21 #define QCA_APB_BASE_REG 0x18000000
22 #define QCA_FLASH_BASE_REG 0x1F000000
27 #define QCA_DDR_CTRL_BASE_REG QCA_APB_BASE_REG + 0x00000000
29 #if (SOC_TYPE & QCA_AR933X_SOC)
30 #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000
32 #define QCA_LSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000
33 #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00500000
36 #define QCA_USB_CFG_BASE_REG QCA_APB_BASE_REG + 0x00030000
37 #define QCA_GPIO_BASE_REG QCA_APB_BASE_REG + 0x00040000
38 #define QCA_PLL_BASE_REG QCA_APB_BASE_REG + 0x00050000
39 #define QCA_RST_BASE_REG QCA_APB_BASE_REG + 0x00060000
40 #define QCA_GMAC_BASE_REG QCA_APB_BASE_REG + 0x00070000
41 #define QCA_RTC_BASE_REG QCA_APB_BASE_REG + 0x00107000
42 #define QCA_PLL_SRIF_BASE_REG QCA_APB_BASE_REG + 0x00116000
44 #if (SOC_TYPE & QCA_AR933X_SOC)
45 #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x00090000
46 #elif (SOC_TYPE & QCA_AR934X_SOC) | \
47 (SOC_TYPE & QCA_AR955X_SOC)
48 #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x000A9000
54 #define QCA_DDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x000
55 #define QCA_DDR_CFG2_REG QCA_DDR_CTRL_BASE_REG + 0x004
56 #define QCA_DDR_MR_REG QCA_DDR_CTRL_BASE_REG + 0x008
57 #define QCA_DDR_EMR_REG QCA_DDR_CTRL_BASE_REG + 0x00C
58 #define QCA_DDR_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x010
59 #define QCA_DDR_REFRESH_REG QCA_DDR_CTRL_BASE_REG + 0x014
60 #define QCA_DDR_RD_DATA_THIS_CYCLE_REG QCA_DDR_CTRL_BASE_REG + 0x018
61 #define QCA_DDR_TAP_CTRL_0_REG QCA_DDR_CTRL_BASE_REG + 0x01C
62 #define QCA_DDR_TAP_CTRL_1_REG QCA_DDR_CTRL_BASE_REG + 0x020
63 #define QCA_DDR_TAP_CTRL_2_REG QCA_DDR_CTRL_BASE_REG + 0x024
64 #define QCA_DDR_TAP_CTRL_3_REG QCA_DDR_CTRL_BASE_REG + 0x028
66 #if (SOC_TYPE & QCA_AR933X_SOC)
67 #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x07C
68 #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x080
69 #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x084
71 #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x09C
72 #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x0A0
73 #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x0A4
74 #define QCA_DDR_WB_FLUSH_PCIE_REG QCA_DDR_CTRL_BASE_REG + 0x0A8
75 #define QCA_DDR_WB_FLUSH_WMAC_REG QCA_DDR_CTRL_BASE_REG + 0x0AC
76 #define QCA_DDR_WB_FLUSH_SRC1_REG QCA_DDR_CTRL_BASE_REG + 0x0B0
77 #define QCA_DDR_WB_FLUSH_SRC2_REG QCA_DDR_CTRL_BASE_REG + 0x0B4
80 #if (SOC_TYPE & QCA_AR933X_SOC)
81 #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x08C
82 #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x090
83 #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x094
84 #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x098
85 #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x09C
86 #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0A0
87 #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0A4
88 #define QCA_SDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0D8
90 #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0B8
91 #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x0BC
92 #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x0C0
93 #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x0C4
94 #define QCA_DDR_BURST2_REG QCA_DDR_CTRL_BASE_REG + 0x0C8
95 #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x0CC
96 #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0D0
97 #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0D4
98 #define QCA_DDR_CTRL_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x108
99 #define QCA_DDR_SELF_REFRESH_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x110
100 #define QCA_DDR_SELF_REFRESH_TIMER_REG QCA_DDR_CTRL_BASE_REG + 0x114
101 #define QCA_DDR_WMAC_FLUSH_REG QCA_DDR_CTRL_BASE_REG + 0x128
102 #define QCA_DDR_CFG3_REG QCA_DDR_CTRL_BASE_REG + 0x15C
106 * DDR registers BIT fields
109 /* DDR_CONFIG register (DDR DRAM configuration) */
110 #define QCA_DDR_CFG_TRAS_SHIFT 0
111 #define QCA_DDR_CFG_TRAS_MASK BITS(QCA_DDR_CFG_TRAS_SHIFT, 5)
112 #define QCA_DDR_CFG_TRCD_SHIFT 5
113 #define QCA_DDR_CFG_TRCD_MASK BITS(QCA_DDR_CFG_TRCD_SHIFT, 4)
114 #define QCA_DDR_CFG_TRP_SHIFT 9
115 #define QCA_DDR_CFG_TRP_MASK BITS(QCA_DDR_CFG_TRP_SHIFT, 4)
116 #define QCA_DDR_CFG_TRRD_SHIFT 13
117 #define QCA_DDR_CFG_TRRD_MASK BITS(QCA_DDR_CFG_TRRD_SHIFT, 4)
118 #define QCA_DDR_CFG_TRFC_SHIFT 17
119 #define QCA_DDR_CFG_TRFC_MASK BITS(QCA_DDR_CFG_TRFC_SHIFT, 6)
120 #define QCA_DDR_CFG_TMRD_SHIFT 23
121 #define QCA_DDR_CFG_TMRD_MASK BITS(QCA_DDR_CFG_TMRD_SHIFT, 4)
122 #define QCA_DDR_CFG_CAS_3LSB_SHIFT 27
123 #define QCA_DDR_CFG_CAS_3LSB_MASK BITS(QCA_DDR_CFG_CAS_3LSB_SHIFT, 3)
124 #define QCA_DDR_CFG_OPEN_PAGE_SHIFT 30
125 #define QCA_DDR_CFG_OPEN_PAGE_MASK 1 << QCA_DDR_CFG_OPEN_PAGE_SHIFT
126 #define QCA_DDR_CFG_CAS_MSB_SHIFT 31
127 #define QCA_DDR_CFG_CAS_MSB_MASK 1 << QCA_DDR_CFG_CAS_MSB_SHIFT
129 /* DDR_CONFIG2 register (DDR DRAM configuration 2) */
130 #define QCA_DDR_CFG2_BURST_LEN_SHIFT 0
131 #define QCA_DDR_CFG2_BURST_LEN_MASK BITS(QCA_DDR_CFG2_BURST_LEN_SHIFT, 4)
132 #define QCA_DDR_CFG2_BURST_TYPE_SHIFT 4
133 #define QCA_DDR_CFG2_BURST_TYPE_MASK 1 << QCA_DDR_CFG2_BURST_TYPE_SHIFT
134 #define QCA_DDR_CFG2_CTRL_OE_EN_SHIFT 5
135 #define QCA_DDR_CFG2_CTRL_OE_EN_MASK 1 << QCA_DDR_CFG2_CTRL_OE_EN_SHIFT
136 #define QCA_DDR_CFG2_PHASE_SEL_SHIFT 6
137 #define QCA_DDR_CFG2_PHASE_SEL_MASK 1 << QCA_DDR_CFG2_PHASE_SEL_SHIFT
138 #define QCA_DDR_CFG2_CKE_SHIFT 7
139 #define QCA_DDR_CFG2_CKE_MASK 1 << QCA_DDR_CFG2_CKE_SHIFT
140 #define QCA_DDR_CFG2_TWR_SHIFT 8
141 #define QCA_DDR_CFG2_TWR_MASK BITS(QCA_DDR_CFG2_TWR_SHIFT, 4)
142 #define QCA_DDR_CFG2_TRTW_SHIFT 12
143 #define QCA_DDR_CFG2_TRTW_MASK BITS(QCA_DDR_CFG2_TRTW_SHIFT, 5)
144 #define QCA_DDR_CFG2_TRTP_SHIFT 17
145 #define QCA_DDR_CFG2_TRTP_MASK BITS(QCA_DDR_CFG2_TRTP_SHIFT, 4)
146 #define QCA_DDR_CFG2_TWTR_SHIFT 21
147 #define QCA_DDR_CFG2_TWTR_MASK BITS(QCA_DDR_CFG2_TWTR_SHIFT, 5)
148 #define QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT 26
149 #define QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK BITS(QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT, 4)
150 #define QCA_DDR_CFG2_SWAP_A26_A27_SHIFT 30
151 #define QCA_DDR_CFG2_SWAP_A26_A27_MASK 1 << QCA_DDR_CFG2_SWAP_A26_A27_SHIFT
152 #define QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT 31
153 #define QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK 1 << QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT
155 /* DDR_MODE register (DDR mode register value) */
156 #define QCA_DDR_MR_VALUE_SHIFT 0
157 #define QCA_DDR_MR_VALUE_MASK BITS(QCA_DDR_MR_VALUE_SHIFT, 14)
160 /* DDR_EMR registers (DDR extended mode register 1/2/3 values) */
161 #define QCA_DDR_EMR_VALUE_SHIFT 0
162 #define QCA_DDR_EMR_VALUE_MASK BITS(QCA_DDR_EMR_VALUE_SHIFT, 14)
164 /* DDR_CONTROL register (DDR control) */
165 #define QCA_DDR_CTRL_FORCE_MRS_SHIFT 0
166 #define QCA_DDR_CTRL_FORCE_MRS_MASK 1 << QCA_DDR_CTRL_FORCE_MRS_SHIFT
167 #define QCA_DDR_CTRL_FORCE_EMRS_SHIFT 1
168 #define QCA_DDR_CTRL_FORCE_EMRS_MASK 1 << QCA_DDR_CTRL_FORCE_EMRS_SHIFT
169 #define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT 2
170 #define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK 1 << QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT
171 #define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT 3
172 #define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK 1 << QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT
173 #define QCA_DDR_CTRL_FORCE_EMR2S_SHIFT 4
174 #define QCA_DDR_CTRL_FORCE_EMR2S_MASK 1 << QCA_DDR_CTRL_FORCE_EMR2S_SHIFT
175 #define QCA_DDR_CTRL_FORCE_EMR3S_SHIFT 5
176 #define QCA_DDR_CTRL_FORCE_EMR3S_MASK 1 << QCA_DDR_CTRL_FORCE_EMR3S_SHIFT
178 /* DDR_REFRESH register (DDR refresh control and configuration) */
179 #define QCA_DDR_REFRESH_PERIOD_SHIFT 0
180 #define QCA_DDR_REFRESH_PERIOD_MASK BITS(QCA_DDR_REFRESH_PERIOD_SHIFT, 14)
181 #define QCA_DDR_REFRESH_EN_SHIFT 14
182 #define QCA_DDR_REFRESH_EN_MASK 1 << QCA_DDR_REFRESH_EN_SHIFT
184 /* DDR_RD_DATA_THIS_CYCLE register (DDR read data capture bit mask) */
185 #define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT 0
186 #define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_MASK BITS(QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT, 32)
188 /* TAP_CONTROL_X registers (DQS delay tap control for byte X) */
189 #if (SOC_TYPE & QCA_AR933X_SOC) | \
190 (SOC_TYPE & QCA_AR934X_SOC)
191 #define QCA_DDR_TAP_CTRL_TAP_L_SHIFT 0
192 #define QCA_DDR_TAP_CTRL_TAP_L_MASK BITS(QCA_DDR_TAP_CTRL_TAP_L_SHIFT, 5)
193 #define QCA_DDR_TAP_CTRL_TAP_H_SHIFT 8
194 #define QCA_DDR_TAP_CTRL_TAP_H_MASK BITS(QCA_DDR_TAP_CTRL_TAP_H_SHIFT, 2)
195 #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT 16
196 #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_MASK QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT
198 #define QCA_DDR_TAP_CTRL_TAP_SHIFT 0
199 #define QCA_DDR_TAP_CTRL_TAP_MASK BITS(QCA_DDR_TAP_CTRL_TAP_SHIFT, 6)
202 /* DDR_DDR2_CONFIG register (DDR2 configuration) */
203 #define QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT 0
204 #define QCA_DDR_DDR2_CFG_DDR2_EN_MASK 1 << QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT
205 #define QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT 2
206 #define QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT, 6)
207 #if (SOC_TYPE & QCA_AR933X_SOC)
208 #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT 10
209 #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 3)
211 #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT 10
212 #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 4)
216 * Low-Speed UART registers
218 #define QCA_LSUART_RBR_REG QCA_LSUART_BASE_REG + 0x00
219 #define QCA_LSUART_THR_REG QCA_LSUART_BASE_REG + 0x00
220 #define QCA_LSUART_DLL_REG QCA_LSUART_BASE_REG + 0x00
221 #define QCA_LSUART_DLH_REG QCA_LSUART_BASE_REG + 0x04
222 #define QCA_LSUART_IER_REG QCA_LSUART_BASE_REG + 0x04
223 #define QCA_LSUART_IIR_REG QCA_LSUART_BASE_REG + 0x08
224 #define QCA_LSUART_FCR_REG QCA_LSUART_BASE_REG + 0x08
225 #define QCA_LSUART_LCR_REG QCA_LSUART_BASE_REG + 0x0C
226 #define QCA_LSUART_MCR_REG QCA_LSUART_BASE_REG + 0x10
227 #define QCA_LSUART_LSR_REG QCA_LSUART_BASE_REG + 0x14
228 #define QCA_LSUART_MSR_REG QCA_LSUART_BASE_REG + 0x18
231 * Low-Speed UART registers BIT fields
234 /* RBR register (Receive buffer) */
235 #define QCA_LSUART_RBR_RBR_SHIFT 0
236 #define QCA_LSUART_RBR_RBR_MASK BITS(QCA_LSUART_RBR_RBR_SHIFT, 8)
238 /* THR register (Transmit holding) */
239 #define QCA_LSUART_THR_THR_SHIFT 0
240 #define QCA_LSUART_THR_THR_MASK BITS(QCA_LSUART_THR_THR_SHIFT, 8)
242 /* DLL register (Divisor latch low) */
243 #define QCA_LSUART_DLL_DLL_SHIFT 0
244 #define QCA_LSUART_DLL_DLL_MASK BITS(QCA_LSUART_DLL_DLL_SHIFT, 8)
246 /* DLH register (Divisor latch high) */
247 #define QCA_LSUART_DLH_DLH_SHIFT 0
248 #define QCA_LSUART_DLH_DLH_MASK BITS(QCA_LSUART_DLH_DLH_SHIFT, 8)
250 /* IER register (Interrupt enable) */
251 #define QCA_LSUART_IER_ERBFI_SHIFT 0
252 #define QCA_LSUART_IER_ERBFI_MASK (1 << QCA_LSUART_IER_ERBFI_SHIFT)
253 #define QCA_LSUART_IER_ETBEI_SHIFT 1
254 #define QCA_LSUART_IER_ETBEI_MASK (1 << QCA_LSUART_IER_ETBEI_SHIFT)
255 #define QCA_LSUART_IER_ELSI_SHIFT 2
256 #define QCA_LSUART_IER_ELSI_MASK (1 << QCA_LSUART_IER_ELSI_SHIFT)
257 #define QCA_LSUART_IER_EDDSI_SHIFT 3
258 #define QCA_LSUART_IER_EDDSI_MASK (1 << QCA_LSUART_IER_EDDSI_SHIFT)
260 /* IIR register (Interrupt identity) */
261 #define QCA_LSUART_IIR_IID_SHIFT 0
262 #define QCA_LSUART_IIR_IID_MASK BITS(QCA_LSUART_IIR_IID_SHIFT, 4)
263 #define QCA_LSUART_IIR_FIFO_STATUS_SHIFT 6
264 #define QCA_LSUART_IIR_FIFO_STATUS_MASK BITS(QCA_LSUART_IIR_FIFO_STATUS_SHIFT, 2)
266 /* FCR register (FIFO control) */
267 #define QCA_LSUART_FCR_FIFO_EN_SHIFT 0
268 #define QCA_LSUART_FCR_EDDSI_MASK (1 << QCA_LSUART_FCR_FIFO_EN_SHIFT)
269 #define QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT 1
270 #define QCA_LSUART_FCR_RCVR_FIFO_RST_MASK (1 << QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT)
271 #define QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT 2
272 #define QCA_LSUART_FCR_XMIT_FIFO_RST_MASK (1 << QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT)
273 #define QCA_LSUART_FCR_DMA_MODE_SHIFT 3
274 #define QCA_LSUART_FCR_DMA_MODE_MASK (1 << QCA_LSUART_FCR_DMA_MODE_SHIFT)
275 #define QCA_LSUART_FCR_RCVR_TRIG_SHIFT 6
276 #define QCA_LSUART_FCR_RCVR_TRIG_MASK BITS(QCA_LSUART_FCR_RCVR_TRIG_SHIFT, 2)
278 /* LCR register (Line control) */
279 #define QCA_LSUART_LCR_CLS_SHIFT 0
280 #define QCA_LSUART_LCR_CLS_MASK BITS(QCA_LSUART_LCR_CLS_SHIFT, 2)
281 #define QCA_LSUART_LCR_CLS_5BIT_VAL 0x0
282 #define QCA_LSUART_LCR_CLS_6BIT_VAL 0x1
283 #define QCA_LSUART_LCR_CLS_7BIT_VAL 0x2
284 #define QCA_LSUART_LCR_CLS_8BIT_VAL 0x3
285 #define QCA_LSUART_LCR_STOP_SHIFT 2
286 #define QCA_LSUART_LCR_STOP_MASK (1 << QCA_LSUART_LCR_STOP_SHIFT)
287 #define QCA_LSUART_LCR_PEN_SHIFT 3
288 #define QCA_LSUART_LCR_PEN_MASK (1 << QCA_LSUART_LCR_PEN_SHIFT)
289 #define QCA_LSUART_LCR_EPS_SHIFT 4
290 #define QCA_LSUART_LCR_EPS_MASK (1 << QCA_LSUART_LCR_EPS_SHIFT)
291 #define QCA_LSUART_LCR_BREAK_SHIFT 6
292 #define QCA_LSUART_LCR_BREAK_MASK (1 << QCA_LSUART_LCR_BREAK_SHIFT)
293 #define QCA_LSUART_LCR_DLAB_SHIFT 7
294 #define QCA_LSUART_LCR_DLAB_MASK (1 << QCA_LSUART_LCR_DLAB_SHIFT)
296 /* MCR register (Modem control) */
297 #define QCA_LSUART_MCR_DTR_SHIFT 0
298 #define QCA_LSUART_MCR_DTR_MASK (1 << QCA_LSUART_MCR_DTR_SHIFT)
299 #define QCA_LSUART_MCR_RTS_SHIFT 1
300 #define QCA_LSUART_MCR_RTS_MASK (1 << QCA_LSUART_MCR_RTS_SHIFT)
301 #define QCA_LSUART_MCR_OUT1_SHIFT 2
302 #define QCA_LSUART_MCR_OUT1_MASK (1 << QCA_LSUART_MCR_OUT1_SHIFT)
303 #define QCA_LSUART_MCR_OUT2_SHIFT 3
304 #define QCA_LSUART_MCR_OUT2_MASK (1 << QCA_LSUART_MCR_OUT2_SHIFT)
305 #define QCA_LSUART_MCR_LOOPBACK_SHIFT 5
306 #define QCA_LSUART_MCR_LOOPBACK_MASK (1 << QCA_LSUART_MCR_LOOPBACK_SHIFT)
308 /* LSR register (Line status) */
309 #define QCA_LSUART_LSR_DR_SHIFT 0
310 #define QCA_LSUART_LSR_DR_MASK (1 << QCA_LSUART_LSR_DR_SHIFT)
311 #define QCA_LSUART_LSR_OE_SHIFT 1
312 #define QCA_LSUART_LSR_OE_MASK (1 << QCA_LSUART_LSR_OE_SHIFT)
313 #define QCA_LSUART_LSR_PE_SHIFT 2
314 #define QCA_LSUART_LSR_PE_MASK (1 << QCA_LSUART_LSR_PE_SHIFT)
315 #define QCA_LSUART_LSR_FE_SHIFT 3
316 #define QCA_LSUART_LSR_FE_MASK (1 << QCA_LSUART_LSR_FE_SHIFT)
317 #define QCA_LSUART_LSR_BI_SHIFT 4
318 #define QCA_LSUART_LSR_BI_MASK (1 << QCA_LSUART_LSR_BI_SHIFT)
319 #define QCA_LSUART_LSR_THRE_SHIFT 5
320 #define QCA_LSUART_LSR_THRE_MASK (1 << QCA_LSUART_LSR_THRE_SHIFT)
321 #define QCA_LSUART_LSR_TEMT_SHIFT 6
322 #define QCA_LSUART_LSR_TEMT_MASK (1 << QCA_LSUART_LSR_TEMT_SHIFT)
323 #define QCA_LSUART_LSR_FERR_SHIFT 7
324 #define QCA_LSUART_LSR_FERR_MASK (1 << QCA_LSUART_LSR_FERR_SHIFT)
326 /* MCR register (Modem status) */
327 #define QCA_LSUART_MCR_DCTS_SHIFT 0
328 #define QCA_LSUART_MCR_DCTS_MASK (1 << QCA_LSUART_MCR_DCTS_SHIFT)
329 #define QCA_LSUART_MCR_DDSR_SHIFT 1
330 #define QCA_LSUART_MCR_DDSR_MASK (1 << QCA_LSUART_MCR_DDSR_SHIFT)
331 #define QCA_LSUART_MCR_TERI_SHIFT 2
332 #define QCA_LSUART_MCR_TERI_MASK (1 << QCA_LSUART_MCR_TERI_SHIFT)
333 #define QCA_LSUART_MCR_DDCD_SHIFT 3
334 #define QCA_LSUART_MCR_DDCD_MASK (1 << QCA_LSUART_MCR_DDCD_SHIFT)
335 #define QCA_LSUART_MCR_CTS_SHIFT 4
336 #define QCA_LSUART_MCR_CTS_MASK (1 << QCA_LSUART_MCR_CTS_SHIFT)
337 #define QCA_LSUART_MCR_DSR_SHIFT 5
338 #define QCA_LSUART_MCR_DSR_MASK (1 << QCA_LSUART_MCR_DSR_SHIFT)
339 #define QCA_LSUART_MCR_RI_SHIFT 6
340 #define QCA_LSUART_MCR_RI_MASK (1 << QCA_LSUART_MCR_RI_SHIFT)
341 #define QCA_LSUART_MCR_DCD_SHIFT 7
342 #define QCA_LSUART_MCR_DCD_MASK (1 << QCA_LSUART_MCR_DCD_SHIFT)
345 * High-Speed UART registers
347 #define QCA_HSUART_DATA_REG QCA_HSUART_BASE_REG + 0x00
348 #define QCA_HSUART_CS_REG QCA_HSUART_BASE_REG + 0x04
349 #define QCA_HSUART_CLK_REG QCA_HSUART_BASE_REG + 0x08
350 #define QCA_HSUART_INT_REG QCA_HSUART_BASE_REG + 0x0C
351 #define QCA_HSUART_INT_EN_REG QCA_HSUART_BASE_REG + 0x10
354 * High-Speed UART registers BIT fields
357 /* UART_DATA register (UART transmit and RX FIFO interface ) */
358 #define QCA_HSUART_DATA_TX_RX_DATA_SHIFT 0
359 #define QCA_HSUART_DATA_TX_RX_DATA_MASK BITS(QCA_HSUART_DATA_TX_RX_DATA_SHIFT, 8)
360 #define QCA_HSUART_DATA_RX_CSR_SHIFT 8
361 #define QCA_HSUART_DATA_RX_CSR_MASK (1 << QCA_HSUART_DATA_RX_CSR_SHIFT)
362 #define QCA_HSUART_DATA_TX_CSR_SHIFT 9
363 #define QCA_HSUART_DATA_TX_CSR_MASK (1 << QCA_HSUART_DATA_TX_CSR_SHIFT)
365 /* UART_CS register (UART configuration and status) */
366 #define QCA_HSUART_CS_PAR_MODE_SHIFT 0
367 #define QCA_HSUART_CS_PAR_MODE_MASK BITS(QCA_HSUART_CS_PAR_MODE_SHIFT, 2)
368 #define QCA_HSUART_CS_PAR_MODE_NO_VAL 0x0
369 #define QCA_HSUART_CS_PAR_MODE_ODD_VAL 0x2
370 #define QCA_HSUART_CS_PAR_MODE_OVEN_VAL 0x3
371 #define QCA_HSUART_CS_IFACE_MODE_SHIFT 2
372 #define QCA_HSUART_CS_IFACE_MODE_MASK BITS(QCA_HSUART_CS_IFACE_MODE_SHIFT, 2)
373 #define QCA_HSUART_CS_IFACE_MODE_DISABLE_VAL 0x0
374 #define QCA_HSUART_CS_IFACE_MODE_DTE_VAL 0x1
375 #define QCA_HSUART_CS_IFACE_MODE_DCE_VAL 0x2
376 #define QCA_HSUART_CS_FLOW_MODE_SHIFT 4
377 #define QCA_HSUART_CS_FLOW_MODE_MASK BITS(QCA_HSUART_CS_FLOW_MODE_SHIFT, 2)
378 #define QCA_HSUART_CS_FLOW_MODE_NO_VAL 0x0
379 #define QCA_HSUART_CS_FLOW_MODE_HW_VAL 0x2
380 #define QCA_HSUART_CS_FLOW_MODE_INV_VAL 0x3
381 #define QCA_HSUART_CS_DMA_EN_SHIFT 6
382 #define QCA_HSUART_CS_DMA_EN_MASK (1 << QCA_HSUART_CS_DMA_EN_SHIFT)
383 #define QCA_HSUART_CS_RX_READY_ORIDE_SHIFT 7
384 #define QCA_HSUART_CS_RX_READY_ORIDE_MASK (1 << QCA_HSUART_CS_RX_READY_ORIDE_SHIFT)
385 #define QCA_HSUART_CS_TX_READY_ORIDE_SHIFT 8
386 #define QCA_HSUART_CS_TX_READY_ORIDE_MASK (1 << QCA_HSUART_CS_TX_READY_ORIDE_SHIFT)
387 #define QCA_HSUART_CS_TX_READY_SHIFT 9
388 #define QCA_HSUART_CS_TX_READY_MASK (1 << QCA_HSUART_CS_TX_READY_SHIFT)
389 #define QCA_HSUART_CS_RX_BREAK_SHIFT 10
390 #define QCA_HSUART_CS_RX_BREAK_MASK (1 << QCA_HSUART_CS_RX_BREAK_SHIFT)
391 #define QCA_HSUART_CS_TX_BREAK_SHIFT 11
392 #define QCA_HSUART_CS_TX_BREAK_MASK (1 << QCA_HSUART_CS_TX_BREAK_SHIFT)
393 #define QCA_HSUART_CS_HOST_INT_SHIFT 12
394 #define QCA_HSUART_CS_HOST_INT_MASK (1 << QCA_HSUART_CS_HOST_INT_SHIFT)
395 #define QCA_HSUART_CS_HOST_INT_EN_SHIFT 13
396 #define QCA_HSUART_CS_HOST_INT_EN_MASK (1 << QCA_HSUART_CS_HOST_INT_EN_SHIFT)
397 #define QCA_HSUART_CS_TX_BUSY_SHIFT 14
398 #define QCA_HSUART_CS_TX_BUSY_MASK (1 << QCA_HSUART_CS_TX_BUSY_SHIFT)
399 #define QCA_HSUART_CS_RX_BUSY_SHIFT 15
400 #define QCA_HSUART_CS_RX_BUSY_MASK (1 << QCA_HSUART_CS_RX_BUSY_SHIFT)
402 /* UART_CLOCK register (UART clock) */
403 #define QCA_HSUART_CLK_STEP_SHIFT 0
404 #define QCA_HSUART_CLK_STEP_MASK BITS(QCA_HSUART_CLK_STEP_SHIFT, 16)
405 #define QCA_HSUART_CLK_STEP_MAX_VAL 0x3333
406 #define QCA_HSUART_CLK_SCALE_SHIFT 16
407 #define QCA_HSUART_CLK_SCALE_MASK BITS(QCA_HSUART_CLK_SCALE_SHIFT, 8)
408 #define QCA_HSUART_CLK_SCALE_MAX_VAL 0xFF
410 /* UART_INT register (UART interrupt/control status) */
411 #define QCA_HSUART_INT_RX_VALID_SHIFT 0
412 #define QCA_HSUART_INT_RX_VALID_MASK (1 << QCA_HSUART_INT_RX_VALID_SHIFT)
413 #define QCA_HSUART_INT_TX_READY_SHIFT 1
414 #define QCA_HSUART_INT_TX_READY_MASK (1 << QCA_HSUART_INT_TX_READY_SHIFT)
415 #define QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT 2
416 #define QCA_HSUART_INT_RX_FRAMING_ERR_MASK (1 << QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT)
417 #define QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT 3
418 #define QCA_HSUART_INT_RX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT)
419 #define QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT 4
420 #define QCA_HSUART_INT_TX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT)
421 #define QCA_HSUART_INT_RX_PARITY_ERR_SHIFT 5
422 #define QCA_HSUART_INT_RX_PARITY_ERR_MASK (1 << QCA_HSUART_INT_RX_PARITY_ERR_SHIFT)
423 #define QCA_HSUART_INT_RX_BREAK_ON_SHIFT 6
424 #define QCA_HSUART_INT_RX_BREAK_ON_MASK (1 << QCA_HSUART_INT_RX_BREAK_ON_SHIFT)
425 #define QCA_HSUART_INT_RX_BREAK_OFF_SHIFT 7
426 #define QCA_HSUART_INT_RX_BREAK_OFF_MASK (1 << QCA_HSUART_INT_RX_BREAK_OFF_SHIFT)
427 #define QCA_HSUART_INT_RX_FULL_SHIFT 8
428 #define QCA_HSUART_INT_RX_FULL_MASK (1 << QCA_HSUART_INT_RX_FULL_SHIFT)
429 #define QCA_HSUART_INT_TX_EMPTY_SHIFT 9
430 #define QCA_HSUART_INT_TX_EMPTY_MASK (1 << QCA_HSUART_INT_TX_EMPTY_SHIFT)
432 /* UART_INT_EN register (UART interrupt enable) */
433 #define QCA_HSUART_INT_EN_RX_VALID_SHIFT 0
434 #define QCA_HSUART_INT_EN_RX_VALID_MASK (1 << QCA_HSUART_INT_EN_RX_VALID_SHIFT)
435 #define QCA_HSUART_INT_EN_TX_READY_SHIFT 1
436 #define QCA_HSUART_INT_EN_TX_READY_MASK (1 << QCA_HSUART_INT_EN_TX_READY_SHIFT)
437 #define QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT 2
438 #define QCA_HSUART_INT_EN_RX_FRAMING_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT)
439 #define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT 3
440 #define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT)
441 #define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT 4
442 #define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT)
443 #define QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT 5
444 #define QCA_HSUART_INT_EN_RX_PARITY_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT)
445 #define QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT 6
446 #define QCA_HSUART_INT_EN_RX_BREAK_ON_MASK (1 << QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT)
447 #define QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT 7
448 #define QCA_HSUART_INT_EN_RX_BREAK_OFF_MASK (1 << QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT)
449 #define QCA_HSUART_INT_EN_RX_FULL_SHIFT 8
450 #define QCA_HSUART_INT_EN_RX_FULL_MASK (1 << QCA_HSUART_INT_EN_RX_FULL_SHIFT)
451 #define QCA_HSUART_INT_EN_TX_EMPTY_SHIFT 9
452 #define QCA_HSUART_INT_EN_TX_EMPTY_MASK (1 << QCA_HSUART_INT_EN_TX_EMPTY_SHIFT)
458 #if (SOC_TYPE & QCA_AR933X_SOC)
459 #define QCA_GPIO_COUNT 30
460 #elif (SOC_TYPE & QCA_AR934X_SOC)
461 #define QCA_GPIO_COUNT 23
462 #elif (SOC_TYPE & QCA_QCA953X_SOC)
463 #define QCA_GPIO_COUNT 18
464 #elif (SOC_TYPE & QCA_QCA955X_SOC)
465 #define QCA_GPIO_COUNT 24
468 #define QCA_GPIO_OE_REG QCA_GPIO_BASE_REG + 0x00
469 #define QCA_GPIO_IN_REG QCA_GPIO_BASE_REG + 0x04
470 #define QCA_GPIO_OUT_REG QCA_GPIO_BASE_REG + 0x08
471 #define QCA_GPIO_SET_REG QCA_GPIO_BASE_REG + 0x0C
472 #define QCA_GPIO_CLEAR_REG QCA_GPIO_BASE_REG + 0x10
473 #define QCA_GPIO_INT_EN_REG QCA_GPIO_BASE_REG + 0x14
474 #define QCA_GPIO_INT_TYPE_REG QCA_GPIO_BASE_REG + 0x18
475 #define QCA_GPIO_INT_POLARITY_REG QCA_GPIO_BASE_REG + 0x1C
476 #define QCA_GPIO_INT_PENDING_REG QCA_GPIO_BASE_REG + 0x20
477 #define QCA_GPIO_INT_MASK_REG QCA_GPIO_BASE_REG + 0x24
479 #if (SOC_TYPE & QCA_AR933X_SOC)
480 #define QCA_GPIO_FUNC_1_REG QCA_GPIO_BASE_REG + 0x28
481 #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x2C
482 #define QCA_GPIO_FUNC_2_REG QCA_GPIO_BASE_REG + 0x30
483 #define QCA_GPIO_WLAN_MUX_SET0_REG QCA_GPIO_BASE_REG + 0x34
484 #define QCA_GPIO_WLAN_MUX_SET1_REG QCA_GPIO_BASE_REG + 0x38
485 #define QCA_GPIO_WLAN_MUX_SET2_REG QCA_GPIO_BASE_REG + 0x3C
486 #define QCA_GPIO_WLAN_MUX_SET3_REG QCA_GPIO_BASE_REG + 0x40
488 #if (SOC_TYPE & QCA_QCA955X_SOC)
489 #define QCA_GPIO_SPARE_BITS_REG QCA_GPIO_BASE_REG + 0x28
491 #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x28
494 #define QCA_GPIO_OUT_FUNC0_REG QCA_GPIO_BASE_REG + 0x2C
495 #define QCA_GPIO_OUT_FUNC1_REG QCA_GPIO_BASE_REG + 0x30
496 #define QCA_GPIO_OUT_FUNC2_REG QCA_GPIO_BASE_REG + 0x34
497 #define QCA_GPIO_OUT_FUNC3_REG QCA_GPIO_BASE_REG + 0x38
498 #define QCA_GPIO_OUT_FUNC4_REG QCA_GPIO_BASE_REG + 0x3C
499 #define QCA_GPIO_OUT_FUNC5_REG QCA_GPIO_BASE_REG + 0x40
500 #define QCA_GPIO_IN_EN0_REG QCA_GPIO_BASE_REG + 0x44
501 #define QCA_GPIO_IN_EN1_REG QCA_GPIO_BASE_REG + 0x48
502 #define QCA_GPIO_IN_EN2_REG QCA_GPIO_BASE_REG + 0x4C
503 #define QCA_GPIO_IN_EN3_REG QCA_GPIO_BASE_REG + 0x50
504 #define QCA_GPIO_IN_EN4_REG QCA_GPIO_BASE_REG + 0x54
505 #define QCA_GPIO_IN_EN9_REG QCA_GPIO_BASE_REG + 0x68
506 #define QCA_GPIO_FUNC_REG QCA_GPIO_BASE_REG + 0x6C
510 * GPIO registers BIT fields
513 /* GPIO_FUNCTION_1/2 register (GPIO function) */
514 #if (SOC_TYPE & QCA_AR933X_SOC)
515 #define QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT 0
516 #define QCA_GPIO_FUNC_1_JTAG_DIS_MASK (1 << QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT)
517 #define QCA_GPIO_FUNC_1_UART_EN_SHIFT 1
518 #define QCA_GPIO_FUNC_1_UART_EN_MASK (1 << QCA_GPIO_FUNC_1_UART_EN_SHIFT)
519 #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT 2
520 #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_MASK (1 << QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT)
521 #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT 3
522 #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT)
523 #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT 4
524 #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT)
525 #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT 5
526 #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT)
527 #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT 6
528 #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT)
529 #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT 7
530 #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT)
531 #define QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT 13
532 #define QCA_GPIO_FUNC_1_SPI_CS_EN1_MASK (1 << QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT)
533 #define QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT 14
534 #define QCA_GPIO_FUNC_1_SPI_CS_EN2_MASK (1 << QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT)
535 #define QCA_GPIO_FUNC_1_SPI_EN_SHIFT 18
536 #define QCA_GPIO_FUNC_1_SPI_EN_MASK (1 << QCA_GPIO_FUNC_1_SPI_EN_SHIFT)
537 #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT 23
538 #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT)
539 #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT 24
540 #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT)
541 #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT 25
542 #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT)
543 #define QCA_GPIO_FUNC_1_I2S_EN_SHIFT 26
544 #define QCA_GPIO_FUNC_1_I2S_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_EN_SHIFT)
545 #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT 27
546 #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT)
547 #define QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT 29
548 #define QCA_GPIO_FUNC_1_I2S_22_18_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT)
549 #define QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT 30
550 #define QCA_GPIO_FUNC_1_SPDIF_EN_MASK (1 << QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT)
551 #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT 31
552 #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_MASK (1 << QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT)
554 #define QCA_GPIO_FUNC_2_MIC_DIS_SHIFT 0
555 #define QCA_GPIO_FUNC_2_MIC_DIS_MASK (1 << QCA_GPIO_FUNC_2_MIC_DIS_SHIFT)
556 #define QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT 1
557 #define QCA_GPIO_FUNC_2_I2S_ON_LED_MASK (1 << QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT)
558 #define QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT 2
559 #define QCA_GPIO_FUNC_2_SPDIF_ON23_MASK (1 << QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT)
560 #define QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT 3
561 #define QCA_GPIO_FUNC_2_I2SCK_ON1_MASK (1 << QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT)
562 #define QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT 4
563 #define QCA_GPIO_FUNC_2_I2SWS_ON0_MASK (1 << QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT)
564 #define QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT 5
565 #define QCA_GPIO_FUNC_2_I2SSD_ON12_MASK (1 << QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT)
566 #define QCA_GPIO_FUNC_2_WPS_DIS_SHIFT 8
567 #define QCA_GPIO_FUNC_2_WPS_DIS_MASK (1 << QCA_GPIO_FUNC_2_WPS_DIS_SHIFT)
568 #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT 9
569 #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_MASK (1 << QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT)
570 #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT 10
571 #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_MASK (1 << QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT)
572 #define QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT 11
573 #define QCA_GPIO_FUNC_2_USB_LED_ON1_MASK (1 << QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT)
574 #define QCA_GPIO_FUNC_2_LNA_ON28_SHIFT 12
575 #define QCA_GPIO_FUNC_2_LNA_ON28_MASK (1 << QCA_GPIO_FUNC_2_LNA_ON28_SHIFT)
576 #define QCA_GPIO_FUNC_2_SLIC_EN_SHIFT 13
577 #define QCA_GPIO_FUNC_2_SLIC_EN_MASK (1 << QCA_GPIO_FUNC_2_SLIC_EN_SHIFT)
578 #define QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT 14
579 #define QCA_GPIO_FUNC_2_SLIC_ON18_22_MASK (1 << QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT)
580 #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT 15
581 #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_MASK (1 << QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT)
582 #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT 16
583 #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_MASK BITS(QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT, 3)
589 #define QCA_GPIO_OUT_FUNCX_GPIOX_EN_SHIFT(_gpio) ((_gpio % 4) * 8)
590 #define QCA_GPIO_OUT_FUNCX_GPIOX_EN_MASK(_gpio) BIT(((_gpio % 4) * 8), 8)
592 #define QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT 0
593 #define QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT 0
594 #define QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT 0
595 #define QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT 0
596 #define QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT 0
597 #define QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT 0
598 #define QCA_GPIO_OUT_FUNCX_GPIO0_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT, 8)
599 #define QCA_GPIO_OUT_FUNCX_GPIO4_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT, 8)
600 #define QCA_GPIO_OUT_FUNCX_GPIO8_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT, 8)
601 #define QCA_GPIO_OUT_FUNCX_GPIO12_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT, 8)
602 #define QCA_GPIO_OUT_FUNCX_GPIO16_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT, 8)
603 #define QCA_GPIO_OUT_FUNCX_GPIO20_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT, 8)
605 #define QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT 8
606 #define QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT 8
607 #define QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT 8
608 #define QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT 8
609 #define QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT 8
610 #define QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT 8
611 #define QCA_GPIO_OUT_FUNCX_GPIO1_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT, 8)
612 #define QCA_GPIO_OUT_FUNCX_GPIO5_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT, 8)
613 #define QCA_GPIO_OUT_FUNCX_GPIO9_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT, 8)
614 #define QCA_GPIO_OUT_FUNCX_GPIO13_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT, 8)
615 #define QCA_GPIO_OUT_FUNCX_GPIO17_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT, 8)
616 #define QCA_GPIO_OUT_FUNCX_GPIO21_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT, 8)
618 #define QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT 16
619 #define QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT 16
620 #define QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT 16
621 #define QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT 16
622 #define QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT 16
623 #define QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT 16
624 #define QCA_GPIO_OUT_FUNCX_GPIO2_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT, 8)
625 #define QCA_GPIO_OUT_FUNCX_GPIO6_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT, 8)
626 #define QCA_GPIO_OUT_FUNCX_GPIO10_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT, 8)
627 #define QCA_GPIO_OUT_FUNCX_GPIO14_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT, 8)
628 #define QCA_GPIO_OUT_FUNCX_GPIO18_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT, 8)
629 #define QCA_GPIO_OUT_FUNCX_GPIO22_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT, 8)
631 #define QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT 24
632 #define QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT 24
633 #define QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT 24
634 #define QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT 24
635 #define QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT 24
636 #define QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT 24
637 #define QCA_GPIO_OUT_FUNCX_GPIO3_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT, 8)
638 #define QCA_GPIO_OUT_FUNCX_GPIO7_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT, 8)
639 #define QCA_GPIO_OUT_FUNCX_GPIO11_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT, 8)
640 #define QCA_GPIO_OUT_FUNCX_GPIO15_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT, 8)
641 #define QCA_GPIO_OUT_FUNCX_GPIO19_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT, 8)
642 #define QCA_GPIO_OUT_FUNCX_GPIO23_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT, 8)
644 /* GPIO output select values (for MUX) */
645 #define QCA_GPIO_OUT_MUX_GPIO_VAL 0
646 #define QCA_GPIO_OUT_MUX_MII_EXT_MDI_VAL 1
647 #define QCA_GPIO_OUT_MUX_SYS_RST_L_VAL 1
648 #define QCA_GPIO_OUT_MUX_NAND_CS0_VAL 1
649 #define QCA_GPIO_OUT_MUX_BOOT_RXT_MDI_VAL 2
650 #define QCA_GPIO_OUT_MUX_SPI_CS0_VAL 9
652 /* 5-port ethernet switch activity LEDs */
653 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN1_VAL 26
654 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN2_VAL 27
655 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN3_VAL 28
656 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN4_VAL 29
657 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN5_VAL 30
659 /* 5-port ethernet switch collision detect LEDs */
660 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN1_VAL 31
661 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN2_VAL 32
662 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN3_VAL 33
663 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN4_VAL 34
664 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN5_VAL 35
666 /* 5-port ethernet switch full/half duplex LEDs */
667 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN1_VAL 36
668 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN2_VAL 37
669 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN3_VAL 38
670 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN4_VAL 39
671 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN5_VAL 40
673 /* 5-port ethernet switch link indicator LEDs */
674 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK1_VAL 41
675 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK2_VAL 42
676 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK3_VAL 43
677 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK4_VAL 44
678 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK5_VAL 45
680 #if (SOC_TYPE & QCA_AR934X_SOC)
681 #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL 4
682 #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL 5
683 #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL 6
684 #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL 7
685 #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL 8
686 #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL 10
687 #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL 11
688 #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL 12
689 #define QCA_GPIO_OUT_MUX_I2S_WS_VAL 13
690 #define QCA_GPIO_OUT_MUX_I2S_SD_VAL 14
691 #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL 15
692 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 16
693 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 17
694 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 18
695 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 19
696 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 20
697 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 21
698 #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL 22
699 #define QCA_GPIO_OUT_MUX_CLK_OBS7_VAL 23
700 #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL 24
701 #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL 25
702 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 46
703 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 47
704 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 48
705 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL 49
706 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 50
707 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 51
708 #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL 72
709 #define QCA_GPIO_OUT_MUX_BT_ANT_VAL 73
710 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 74
711 #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL 78
712 #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL_VAL 79
713 #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL_VAL 80
714 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 84
715 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 87
717 #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL 3
718 #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL 4
719 #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL 5
720 #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL 8
721 #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL 10
722 #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL 11
723 #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL 12
724 #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL 13
725 #define QCA_GPIO_OUT_MUX_I2S_WS_VAL 14
726 #define QCA_GPIO_OUT_MUX_I2S_SD_VAL 15
727 #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL 16
728 #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL 17
729 #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL 18
730 #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL 19
731 #define QCA_GPIO_OUT_MUX_HSUART_RXD_VAL 20 /* TODO: RXD is INPUT, mistake in QCA9558 datasheet? */
732 #define QCA_GPIO_OUT_MUX_HSUART_CTS_VAL 21 /* TODO: CTS is INPUT, mistake in QCA9558 datasheet? */
733 #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL 22
734 #define QCA_GPIO_OUT_MUX_SRIF_OUT_VAL 23
736 #if (SOC_TYPE & QCA_QCA955X_SOC)
737 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_VAL 24
738 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_VAL 25
739 #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_VAL 26
740 #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_VAL 27
741 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_INV_VAL 28
742 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_INV_VAL 29
743 #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_INV_VAL 30
744 #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_INV_VAL 31
745 #define QCA_GPIO_OUT_MUX_GE1_MII_MDO_VAL 32
746 #define QCA_GPIO_OUT_MUX_GE1_MII_MDC_VAL 33
747 #define QCA_GPIO_OUT_MUX_SWCOM2_VAL 38
748 #define QCA_GPIO_OUT_MUX_SWCOM3_VAL 39
749 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL 40
750 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL 41
751 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 42
752 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 43
753 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 44
754 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL 45
755 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 46
756 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 47
757 #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL 68
758 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 70
759 #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_STROBE_VAL 71
760 #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_DATA_VAL 72
761 #define QCA_GPIO_OUT_MUX_NAND_CS1_VAL 73
762 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 74
763 #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL 75
764 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 76
765 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_EP_VAL 77
766 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL 78
767 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 79
768 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 80
769 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 81
770 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 82
771 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 83
772 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 84
775 #if (SOC_TYPE & QCA_QCA953X_SOC)
776 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL 48
777 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL 49
778 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 50
779 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 51
780 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 52
781 #define QCA_GPIO_OUT_MUX_RX_CLEAR_INT_VAL 53
782 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 54
783 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 55
784 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 78
785 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 86
786 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 88
787 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL 89
788 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 90
789 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 91
790 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 92
791 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 93
792 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 94
793 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 95
794 #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL 96
798 /* GPIO_IN_ENABLE0 register (GPIO in signals 0) */
799 #define QCA_GPIO_IN_EN0_SPI_MISO_SHIFT 0
800 #define QCA_GPIO_IN_EN0_SPI_MISO_MASK BITS(QCA_GPIO_IN_EN0_SPI_MISO_SHIFT, 8)
801 #define QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT 8
802 #define QCA_GPIO_IN_EN0_LSUART_RXD_MASK BITS(QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT ,8)
804 /* GPIO_IN_ENABLE1 register (GPIO in signals 1) */
805 #define QCA_GPIO_IN_EN1_I2S_WS_SHIFT 0
806 #define QCA_GPIO_IN_EN1_I2S_WS_MASK BITS(QCA_GPIO_IN_EN1_I2S_WS_SHIFT ,8)
807 #define QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT 8
808 #define QCA_GPIO_IN_EN1_I2S_MIC_SD_MASK BITS(QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT ,8)
809 #define QCA_GPIO_IN_EN1_I2S_CLK_SHIFT 16
810 #define QCA_GPIO_IN_EN1_I2S_CLK_MASK BITS(QCA_GPIO_IN_EN1_I2S_CLK_SHIFT ,8)
811 #define QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT 24
812 #define QCA_GPIO_IN_EN1_I2S_MCLK_MASK BITS(QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT ,8)
814 /* GPIO_IN_ENABLE9 register (GPIO in signals 9) */
815 #define QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT 16
816 #define QCA_GPIO_IN_EN9_HSUART_RXD_MASK BITS(QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT ,8)
817 #define QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT 24
818 #define QCA_GPIO_IN_EN9_HSUART_CTS_MASK BITS(QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT ,8)
820 /* GPIO_FUNCTION register (GPIO function) */
821 #define QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT 0
822 #define QCA_GPIO_FUNC_GPIO_SRIF_EN_MASK (1 << QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT)
823 #define QCA_GPIO_FUNC_JTAG_DIS_SHIFT 1
824 #define QCA_GPIO_FUNC_JTAG_DIS_MASK (1 << QCA_GPIO_FUNC_JTAG_DIS_SHIFT)
825 #define QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT 2
826 #define QCA_GPIO_FUNC_CLK_OBS0_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT)
827 #define QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT 3
828 #define QCA_GPIO_FUNC_CLK_OBS1_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT)
829 #define QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT 4
830 #define QCA_GPIO_FUNC_CLK_OBS2_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT)
831 #define QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT 5
832 #define QCA_GPIO_FUNC_CLK_OBS3_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT)
833 #define QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT 6
834 #define QCA_GPIO_FUNC_CLK_OBS4_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT)
835 #define QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT 7
836 #define QCA_GPIO_FUNC_CLK_OBS5_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT)
837 #define QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT 8
838 #define QCA_GPIO_FUNC_CLK_OBS6_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT)
839 #define QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT 9
840 #define QCA_GPIO_FUNC_CLK_OBS7_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT)
843 * PLL control registers
845 #define QCA_PLL_CPU_PLL_CFG_REG QCA_PLL_BASE_REG + 0x00
847 #if (SOC_TYPE & QCA_AR933X_SOC)
848 #define QCA_PLL_CPU_PLL_CFG2_REG QCA_PLL_BASE_REG + 0x04
849 #define QCA_PLL_CPU_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08
850 #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG QCA_PLL_BASE_REG + 0x10
851 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x14
852 #define QCA_PLL_ETHSW_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24
853 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C
854 #define QCA_PLL_USB_SUSPEND_REG QCA_PLL_BASE_REG + 0x40
855 #define QCA_PLL_WLAN_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x44
857 #define QCA_PLL_DDR_PLL_CFG_REG QCA_PLL_BASE_REG + 0x04
858 #define QCA_PLL_CPU_DDR_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08
860 #if (SOC_TYPE & QCA_QCA955X_SOC)
861 #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x0C
862 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x10
863 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x14
864 #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x18
865 #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x1C
866 #define QCA_PLL_SWITCH_CLK_SPARE_REG QCA_PLL_BASE_REG + 0x20
867 #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x24
868 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x28
869 #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x2C
870 #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x30
871 #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x34
872 #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x38
873 #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x40
874 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44
875 #define QCA_PLL_ETH_SGMII_CTRL_REG QCA_PLL_BASE_REG + 0x48
876 #define QCA_PLL_ETH_SGMII_SERDES_REG QCA_PLL_BASE_REG + 0x4C
877 #define QCA_PLL_SLIC_PWM_DIV_REG QCA_PLL_BASE_REG + 0x50
879 #define QCA_PLL_CPU_SYNC_REG QCA_PLL_BASE_REG + 0x0C
880 #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x10
881 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x14
882 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x18
883 #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x1C
884 #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x20
885 #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24
887 #if (SOC_TYPE & QCA_AR9344_SOC)
888 #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28
890 #define QCA_PLL_CURR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28
893 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C
894 #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x30
895 #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x34
896 #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x38
897 #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x3C
898 #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x40
899 #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44
900 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x48
905 * PLL control registers BIT fields
908 /* CPU_PLL_CONFIG register (CPU phase lock loop configuration) */
909 #if (SOC_TYPE & QCA_AR933X_SOC)
910 #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0
911 #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 10)
912 #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 10
913 #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
914 #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 16
915 #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
916 #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 21
917 #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK (1 << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)
918 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 23
919 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
921 #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0
922 #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 6)
923 #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 6
924 #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
925 #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 12
926 #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
927 #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 17
928 #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK BITS(QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT, 2)
929 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 19
930 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
933 #define QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT 30
934 #define QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK (1 << QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT)
935 #define QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT 31
936 #define QCA_PLL_CPU_PLL_CFG_UPDATING_MASK (1 << QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT)
938 /* CPU_PLL_CONFIG2 register (CPU phase lock loop configuration, AR933x only) */
939 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT 0
940 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_MASK BITS(QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT, 12)
942 /* CPU_CLOCK_CONTROL register (CPU clock control, AR933x only) */
943 #define QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT 2
944 #define QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK (1 << QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT)
945 #define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT 5
946 #define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT, 2)
947 #define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT 10
948 #define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT, 2)
949 #define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT 15
950 #define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT, 2)
952 /* ETHSW_CLOCK_CONTROL register (Ethernet switch clock control, AR933x only) */
953 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT 3
954 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_MASK (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT)
955 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT 4
956 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_MASK (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT)
958 /* ETH_XMII_CONTROL register (Ethernet XMII control) */
959 #define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT 0
960 #define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT, 8)
961 #define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT 8
962 #define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT, 8)
963 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT 16
964 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT, 8)
965 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT 24
966 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_MASK (1 << QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT)
967 #define QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT 25
968 #define QCA_PLL_ETH_XMII_CTRL_GIGE_MASK (1 << QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT)
969 #define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT 26
970 #define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT, 2)
971 #define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT 28
972 #define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT, 2)
973 #define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT 30
974 #define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_MASK (1 << QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT)
975 #define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT 31
976 #define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_MASK (1 << QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT)
978 /* SUSPEND register (USB suspend, AR933x only) */
979 #define QCA_PLL_USB_SUSPEND_EN_SHIFT 0
980 #define QCA_PLL_USB_SUSPEND_EN_MASK (1 << QCA_PLL_USB_SUSPEND_EN_SHIFT)
981 #define QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT 8
982 #define QCA_PLL_USB_SUSPEND_RESTART_TIME_MASK BITS(QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT, 20)
984 /* WLAN_CLOCK_CONTROL register (WLAN clock control, AR933x only) */
985 #define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT 0
986 #define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT)
987 #define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT 1
988 #define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT)
989 #define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT 2
990 #define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT)
991 #define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT 3
992 #define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT)
993 #define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT 4
994 #define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT)
995 #define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT 8
996 #define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT)
997 #define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT 9
998 #define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT)
999 #define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT 10
1000 #define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT)
1001 #define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT 12
1002 #define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT)
1004 /* DDR_PLL_CONFIG register (DDR PLL configuration) */
1005 #define QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT 0
1006 #define QCA_PLL_DDR_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT, 10)
1007 #define QCA_PLL_DDR_PLL_CFG_NINT_SHIFT 10
1008 #define QCA_PLL_DDR_PLL_CFG_NINT_MASK BITS(QCA_PLL_DDR_PLL_CFG_NINT_SHIFT, 6)
1009 #define QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT 16
1010 #define QCA_PLL_DDR_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT, 5)
1011 #define QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT 21
1012 #define QCA_PLL_DDR_PLL_CFG_RANGE_MASK BITS(QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT, 2)
1013 #define QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT 23
1014 #define QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT, 3)
1015 #define QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT 30
1016 #define QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK (1 << QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT)
1017 #define QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT 31
1018 #define QCA_PLL_DDR_PLL_CFG_UPDATING_MASK (1 << QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT)
1020 /* CPU_DDR_CLOCK_CONTROL register (CPU DDR clock control) */
1021 #define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT 1
1022 #define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT)
1023 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT 2
1024 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT)
1025 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT 3
1026 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT)
1027 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT 4
1028 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT)
1029 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
1030 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT, 5)
1031 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
1032 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT, 5)
1033 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
1034 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT, 5)
1035 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT 20
1036 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT)
1037 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT 21
1038 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT)
1039 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT 22
1040 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT)
1041 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT 23
1042 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT)
1043 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT 24
1044 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT)
1046 /* DDR_PLL_DITHER register (DDR PLL dither parameter) */
1047 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT 0
1048 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT, 10)
1049 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT 10
1050 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 10)
1051 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_SHIFT 20
1052 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 7)
1053 #define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT 27
1054 #define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT, 4)
1055 #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT 31
1056 #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT)
1058 #if (SOC_TYPE & QCA_AR933X_SOC)
1059 /* PLL_DITHER_FRAC register (CPU PLL dither FRAC) */
1060 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT 0
1061 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT, 10)
1062 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT 10
1063 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT, 10)
1064 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT 20
1065 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT, 10)
1067 /* PLL_DITHER register (CPU PLL dither) */
1068 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 0
1069 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 14)
1070 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31
1071 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT)
1073 /* CPU_PLL_DITHER register (CPU PLL dither parameter) */
1074 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT 0
1075 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 6)
1076 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT 6
1077 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
1078 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 12
1079 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
1080 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 18
1081 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6)
1082 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31
1083 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT)
1087 * PLL SRIF registers (not available in AR933x)
1089 #define QCA_PLL_SRIF_CPU_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x1C0
1090 #define QCA_PLL_SRIF_CPU_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x1C4
1091 #define QCA_PLL_SRIF_CPU_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x1C8
1092 #define QCA_PLL_SRIF_AUD_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x200
1093 #define QCA_PLL_SRIF_AUD_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x204
1094 #define QCA_PLL_SRIF_AUD_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x208
1095 #define QCA_PLL_SRIF_DDR_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x240
1096 #define QCA_PLL_SRIF_DDR_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x244
1097 #define QCA_PLL_SRIF_DDR_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x248
1098 #define QCA_PLL_SRIF_PCIE_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0xC00
1099 #define QCA_PLL_SRIF_PCIE_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0xC04
1100 #define QCA_PLL_SRIF_PCIE_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0xC08
1103 * PLL SRIF registers BIT fields (not available in AR933x)
1106 /* DPLL1 (common for CPU, AUD, DDR and PCIE) */
1107 #define QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT 0
1108 #define QCA_PLL_SRIF_DPLL1_NFRAC_MASK BITS(QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT, 18)
1109 #define QCA_PLL_SRIF_DPLL1_NINT_SHIFT 18
1110 #define QCA_PLL_SRIF_DPLL1_NINT_MASK BITS(QCA_PLL_SRIF_DPLL1_NINT_SHIFT, 9)
1111 #define QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT 27
1112 #define QCA_PLL_SRIF_DPLL1_REFDIV_MASK BITS(QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT, 5)
1114 /* DPLL2 (common for CPU, AUD, DDR and PCIE) */
1115 #if (SOC_TYPE & QCA_QCA953X_SOC)
1116 #define QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT 0
1117 #define QCA_PLL_SRIF_DPLL2_RST_TEST_MASK (1 << QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT)
1118 #define QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT 1
1119 #define QCA_PLL_SRIF_DPLL2_SEL_CNT_MASK (1 << QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT)
1120 #define QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT 2
1121 #define QCA_PLL_SRIF_DPLL2_TEST_IN_MASK BITS(QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT, 10)
1122 #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT 12
1123 #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_MASK BITS(QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT, 7)
1124 #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 19
1125 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 3)
1126 #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 22
1127 #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
1128 #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT 23
1129 #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_MASK (1 << QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT)
1130 #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT 24
1131 #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_MASK (1 << QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT)
1132 #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 25
1133 #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 4)
1134 #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 29
1135 #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 2)
1136 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 31
1137 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
1139 #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 13
1140 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2)
1141 #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 16
1142 #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
1143 #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 19
1144 #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7)
1145 #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 26
1146 #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KI_SHIFT, 4)
1147 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 30
1148 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
1149 #define QCA_PLL_SRIF_DPLL2_RANGE_SHIFT 31
1150 #define QCA_PLL_SRIF_DPLL2_RANGE_MASK (1 << QCA_PLL_SRIF_DPLL2_RANGE_SHIFT)
1153 /* DPLL3 (common for CPU, AUD, DDR and PCIE) */
1154 #define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT 23
1155 #define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_MASK BITS(QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT, 7)
1158 * Reset control registers
1160 #define QCA_RST_GENERAL_TIMER1_REG QCA_RST_BASE_REG + 0x00
1161 #define QCA_RST_GENERAL_TIMER1_RELOAD_REG QCA_RST_BASE_REG + 0x04
1162 #define QCA_RST_WATCHDOG_TIMER_CTRL_REG QCA_RST_BASE_REG + 0x08
1163 #define QCA_RST_WATCHDOG_TIMER_REG QCA_RST_BASE_REG + 0x0C
1164 #define QCA_RST_MISC_INTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x10
1165 #define QCA_RST_MISC_INTERRUPT_MASK_REG QCA_RST_BASE_REG + 0x14
1166 #define QCA_RST_GLOBALINTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x18
1167 #define QCA_RST_RST_REG QCA_RST_BASE_REG + 0x1C
1168 #define QCA_RST_REVISION_ID_REG QCA_RST_BASE_REG + 0x90
1169 #define QCA_RST_GENERAL_TIMER2_REG QCA_RST_BASE_REG + 0x94
1170 #define QCA_RST_GENERAL_TIMER2_RELOAD_REG QCA_RST_BASE_REG + 0x98
1171 #define QCA_RST_GENERAL_TIMER3_REG QCA_RST_BASE_REG + 0x9C
1172 #define QCA_RST_GENERAL_TIMER3_RELOAD_REG QCA_RST_BASE_REG + 0xA0
1173 #define QCA_RST_GENERAL_TIMER4_REG QCA_RST_BASE_REG + 0xA4
1174 #define QCA_RST_GENERAL_TIMER4_RELOAD_REG QCA_RST_BASE_REG + 0xA8
1176 #if (SOC_TYPE & QCA_AR933X_SOC)
1177 #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xAC
1179 #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xB0
1183 * Reset control registers BIT fields
1186 /* RST_BOOTSTRAP (Reset bootstrap) */
1187 #if (SOC_TYPE & QCA_AR933X_SOC)
1188 #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 0
1190 #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 4
1192 #define QCA_RST_BOOTSTRAP_REF_CLK_MASK (1 << QCA_RST_BOOTSTRAP_REF_CLK_SHIFT)
1193 #define QCA_RST_BOOTSTRAP_REF_CLK_25M_VAL 0x0
1194 #define QCA_RST_BOOTSTRAP_REF_CLK_40M_VAL 0x1
1196 #if (SOC_TYPE & QCA_AR933X_SOC)
1197 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 12
1198 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
1199 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 0
1200 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1
1201 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 2
1202 #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT 16
1203 #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK (1 << QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT)
1204 #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT 17
1205 #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_MASK (1 << QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT)
1206 #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT 18
1207 #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_MASK (1 << QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT)
1209 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 0
1211 /* v2 does not support SDR, but we can read reserved bit and make it universal */
1212 #if (SOC_TYPE & QCA_QCA953X_SOC)
1213 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
1215 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK (1 << QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT)
1218 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 3
1219 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1
1220 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 0
1224 #define QCA_RST_RESET_I2C_RST_SHIFT 0
1225 #define QCA_RST_RESET_I2C_RST_MASK (1 << QCA_RST_RESET_I2C_RST_SHIFT)
1226 #define QCA_RST_RESET_MBOX_RST_SHIFT 1
1227 #define QCA_RST_RESET_MBOX_RST_MASK (1 << QCA_RST_RESET_MBOX_RST_SHIFT)
1228 #define QCA_RST_RESET_LUT_RST_SHIFT 2
1229 #define QCA_RST_RESET_LUT_RST_MASK (1 << QCA_RST_RESET_LUT_RST_SHIFT)
1230 #define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT 3
1231 #define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_MASK (1 << QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT)
1232 #define QCA_RST_RESET_USB_PHY_RST_SHIFT 4
1233 #define QCA_RST_RESET_USB_PHY_RST_MASK (1 << QCA_RST_RESET_USB_PHY_RST_SHIFT)
1234 #define QCA_RST_RESET_USB_HOST_RST_SHIFT 5
1235 #define QCA_RST_RESET_USB_HOST_RST_MASK (1 << QCA_RST_RESET_USB_HOST_RST_SHIFT)
1237 #if (SOC_TYPE & QCA_AR933X_SOC)
1238 #define QCA_RST_RESET_SLIC_RST_SHIFT 6
1239 #define QCA_RST_RESET_SLIC_RST_MASK (1 << QCA_RST_RESET_SLIC_RST_SHIFT)
1241 #define QCA_RST_RESET_PCIE_RST_SHIFT 6
1242 #define QCA_RST_RESET_PCIE_RST_MASK (1 << QCA_RST_RESET_PCIE_RST_SHIFT)
1243 #define QCA_RST_RESET_SLIC_RST_SHIFT 30
1244 #define QCA_RST_RESET_SLIC_RST_MASK (1 << QCA_RST_RESET_SLIC_RST_SHIFT)
1247 #define QCA_RST_RESET_PCIE_PHY_RST_SHIFT 7
1248 #define QCA_RST_RESET_PCIE_PHY_RST_MASK (1 << QCA_RST_RESET_PCIE_PHY_RST_SHIFT)
1250 #if (SOC_TYPE & QCA_QCA955X_SOC)
1251 #define QCA_RST_RESET_ETH_SGMII_RST_SHIFT 8
1252 #define QCA_RST_RESET_ETH_SGMII_RST_MASK (1 << QCA_RST_RESET_ETH_SGMII_RST_SHIFT)
1254 #define QCA_RST_RESET_ETH_SWITCH_RST_SHIFT 8
1255 #define QCA_RST_RESET_ETH_SWITCH_RST_MASK (1 << QCA_RST_RESET_ETH_SWITCH_RST_SHIFT)
1258 #define QCA_RST_RESET_GE0_MAC_RST_SHIFT 9
1259 #define QCA_RST_RESET_GE0_MAC_RST_MASK (1 << QCA_RST_RESET_GE0_MAC_RST_SHIFT)
1260 #define QCA_RST_RESET_HOST_DMA_INT_SHIFT 10
1261 #define QCA_RST_RESET_HOST_DMA_INT_MASK (1 << QCA_RST_RESET_HOST_DMA_INT_SHIFT)
1263 #if (SOC_TYPE & QCA_AR933X_SOC)
1264 #define QCA_RST_RESET_WLAN_RST_SHIFT 11
1265 #define QCA_RST_RESET_WLAN_RST_MASK (1 << QCA_RST_RESET_WLAN_RST_SHIFT)
1267 #define QCA_RST_RESET_USB_PHY_ARST_SHIFT 11
1268 #define QCA_RST_RESET_USB_PHY_ARST_MASK (1 << QCA_RST_RESET_USB_PHY_ARST_SHIFT)
1271 #if (SOC_TYPE & QCA_AR933X_SOC)
1272 #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 14
1273 #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK (1 << QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
1275 #if (SOC_TYPE & QCA_QCA955X_SOC)
1276 #define QCA_RST_RESET_ETH_SGMII_ARST_SHIFT 12
1277 #define QCA_RST_RESET_ETH_SGMII_ARST_MASK (1 << QCA_RST_RESET_ETH_SGMII_ARST_SHIFT)
1279 #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 12
1280 #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK (1 << QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
1283 #define QCA_RST_RESET_NANDF_RST_SHIFT 14
1284 #define QCA_RST_RESET_NANDF_RST_MASK (1 << QCA_RST_RESET_NANDF_RST_SHIFT)
1287 #define QCA_RST_RESET_GE1_MAC_RST_SHIFT 13
1288 #define QCA_RST_RESET_GE1_MAC_RST_MASK (1 << QCA_RST_RESET_GE1_MAC_RST_SHIFT)
1289 #define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT 15
1290 #define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_MASK (1 << QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT)
1291 #define QCA_RST_RESET_DDR_RST_SHIFT 16
1292 #define QCA_RST_RESET_DDR_RST_MASK (1 << QCA_RST_RESET_DDR_RST_SHIFT)
1293 #define QCA_RST_RESET_HSUART_RST_SHIFT 17
1294 #define QCA_RST_RESET_HSUART_RST_MASK (1 << QCA_RST_RESET_HSUART_RST_SHIFT)
1295 #define QCA_RST_RESET_PCIEEP_RST_SHIFT 18
1296 #define QCA_RST_RESET_PCIEEP_RST_MASK (1 << QCA_RST_RESET_PCIEEP_RST_SHIFT)
1297 #define QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT 19
1298 #define QCA_RST_RESET_HOST_DMA_RST_INT_MASK (1 << QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT)
1299 #define QCA_RST_RESET_CPU_COLD_RST_SHIFT 20
1300 #define QCA_RST_RESET_CPU_COLD_RST_MASK (1 << QCA_RST_RESET_CPU_COLD_RST_SHIFT)
1301 #define QCA_RST_RESET_CPU_NMI_SHIFT 21
1302 #define QCA_RST_RESET_CPU_NMI_MASK (1 << QCA_RST_RESET_CPU_NMI_SHIFT)
1303 #define QCA_RST_RESET_GE0_MDIO_RST_SHIFT 22
1304 #define QCA_RST_RESET_GE0_MDIO_RST_MASK (1 << QCA_RST_RESET_GE0_MDIO_RST_SHIFT)
1305 #define QCA_RST_RESET_GE1_MDIO_RST_SHIFT 23
1306 #define QCA_RST_RESET_GE1_MDIO_RST_MASK (1 << QCA_RST_RESET_GE1_MDIO_RST_SHIFT)
1307 #define QCA_RST_RESET_FULL_CHIP_RST_SHIFT 24
1308 #define QCA_RST_RESET_FULL_CHIP_RST_MASK (1 << QCA_RST_RESET_FULL_CHIP_RST_SHIFT)
1309 #define QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT 25
1310 #define QCA_RST_RESET_CHECKSUM_ACC_RST_MASK (1 << QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT)
1311 #define QCA_RST_RESET_PCIEEP_RST_INT_SHIFT 26
1312 #define QCA_RST_RESET_PCIEEP_RST_INT_MASK (1 << QCA_RST_RESET_PCIEEP_RST_INT_SHIFT)
1313 #define QCA_RST_RESET_RTC_RST_SHIFT 27
1314 #define QCA_RST_RESET_RTC_RST_MASK (1 << QCA_RST_RESET_RTC_RST_SHIFT)
1315 #define QCA_RST_RESET_EXT_RST_SHIFT 28
1316 #define QCA_RST_RESET_EXT_RST_MASK (1 << QCA_RST_RESET_EXT_RST_SHIFT)
1318 #if (SOC_TYPE & QCA_AR934X_SOC) | \
1319 (SOC_TYPE & QCA_QCA955X_SOC)
1320 #define QCA_RST_RESET_HOST_DMA_RST_SHIFT 29
1321 #define QCA_RST_RESET_HOST_DMA_RST_MASK (1 << QCA_RST_RESET_HOST_DMA_RST_SHIFT)
1323 #define QCA_RST_RESET_USB_EXT_PWR_SHIFT 29
1324 #define QCA_RST_RESET_USB_EXT_PWR_MASK (1 << QCA_RST_RESET_USB_EXT_PWR_SHIFT)
1327 #define QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT 31
1328 #define QCA_RST_RESET_HOST_DMA_RST_STATUS_MASK (1 << QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT)
1330 /* RST_REVISION_ID (Chip revision ID) */
1331 #define QCA_RST_REVISION_ID_MAJOR_SHIFT 4
1332 #define QCA_RST_REVISION_ID_MAJOR_MASK BITS(QCA_RST_REVISION_ID_MAJOR_SHIFT, 12)
1334 #if (SOC_TYPE & QCA_AR933X_SOC)
1335 #define QCA_RST_REVISION_ID_REV_SHIFT 0
1336 #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 2)
1338 #define QCA_RST_REVISION_ID_REV_SHIFT 0
1339 #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 4)
1342 #define QCA_RST_REVISION_ID_MAJOR_AR9330_VAL 0x0110
1343 #define QCA_RST_REVISION_ID_MAJOR_AR9331_VAL 0x1110
1344 #define QCA_RST_REVISION_ID_MAJOR_AR9341_VAL 0x0120
1345 #define QCA_RST_REVISION_ID_MAJOR_AR9344_VAL 0x2120
1346 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL 0x0140
1347 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL 0x0160
1348 #define QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL 0x1130
1353 #define QCA_RTC_RST_CTRL_REG QCA_RTC_BASE_REG + 0x00
1354 #define QCA_RTC_XTAL_CTRL_REG QCA_RTC_BASE_REG + 0x04
1355 #define QCA_RTC_WLAN_PLL_CTRL_REG QCA_RTC_BASE_REG + 0x14
1356 #define QCA_RTC_PLL_SETTLE_REG QCA_RTC_BASE_REG + 0x18
1357 #define QCA_RTC_XTAL_SETTLE_REG QCA_RTC_BASE_REG + 0x1C
1358 #define QCA_RTC_CLK_OUT_REG QCA_RTC_BASE_REG + 0x20
1359 #define QCA_RTC_RST_CAUSE_REG QCA_RTC_BASE_REG + 0x28
1360 #define QCA_RTC_SYS_SLEEP_REG QCA_RTC_BASE_REG + 0x2C
1361 #define QCA_RTC_KEEP_AWAKE_REG QCA_RTC_BASE_REG + 0x34
1362 #define QCA_RTC_DERIVED_RTC_CLK_REG QCA_RTC_BASE_REG + 0x38
1363 #define QCA_RTC_PLL_CTRL2_REG QCA_RTC_BASE_REG + 0x3C
1364 #define QCA_RTC_SYNC_RST_REG QCA_RTC_BASE_REG + 0x40
1365 #define QCA_RTC_SYNC_STATUS_REG QCA_RTC_BASE_REG + 0x44
1366 #define QCA_RTC_SYNC_DERIVED_REG QCA_RTC_BASE_REG + 0x48
1367 #define QCA_RTC_SYNC_FORCE_WAKE_REG QCA_RTC_BASE_REG + 0x4C
1368 #define QCA_RTC_INTERRUPT_CAUSE_REG QCA_RTC_BASE_REG + 0x50
1369 #define QCA_RTC_INTERRUPT_EN_REG QCA_RTC_BASE_REG + 0x54
1370 #define QCA_RTC_INTERRUPT_MASK_REG QCA_RTC_BASE_REG + 0x58
1373 * RTC registers BIT fields
1376 /* RESET_CONTROL register (RTC reset control) */
1377 #define QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT 0
1378 #define QCA_RTC_RST_CTRL_MAC_WARM_RST_MASK (1 << QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT)
1379 #define QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT 1
1380 #define QCA_RTC_RST_CTRL_MAC_COLD_RST_MASK (1 << QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT)
1381 #define QCA_RTC_RST_CTRL_WARM_RST_SHIFT 2
1382 #define QCA_RTC_RST_CTRL_WARM_RST_MASK (1 << QCA_RTC_RST_CTRL_WARM_RST_SHIFT)
1383 #define QCA_RTC_RST_CTRL_COLD_RST_SHIFT 3
1384 #define QCA_RTC_RST_CTRL_COLD_RST_MASK (1 << QCA_RTC_RST_CTRL_COLD_RST_SHIFT)
1386 /* RESET_CAUSE register (Reset cause) */
1387 #define QCA_RTC_RST_CAUSE_LAST_SHIFT 0
1388 #define QCA_RTC_RST_CAUSE_LAST_MASK BITS(QCA_RTC_RST_CAUSE_LAST_SHIFT, 2)
1390 #define QCA_RTC_RST_CAUSE_LAST_HARD_VAL 0
1391 #define QCA_RTC_RST_CAUSE_LAST_COLD_VAL 1
1392 #define QCA_RTC_RST_CAUSE_LAST_WARM_VAL 2
1394 /* RTC_SYNC_REGISTER register (RTC reset, force sleep and force wakeup) */
1395 #define QCA_RTC_SYNC_RST_RESET_SHIFT 0
1396 #define QCA_RTC_SYNC_RST_RESET_MASK (1 << QCA_RTC_SYNC_RST_RESET_SHIFT)
1398 /* RTC_SYNC_STATUS register (RTC sync/sleep status) */
1399 #define QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT 0
1400 #define QCA_RTC_SYNC_STATUS_SHUTDOWN_MASK (1 << QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT)
1401 #define QCA_RTC_SYNC_STATUS_ON_SHIFT 1
1402 #define QCA_RTC_SYNC_STATUS_ON_MASK (1 << QCA_RTC_SYNC_STATUS_ON_SHIFT)
1403 #define QCA_RTC_SYNC_STATUS_SLEEP_SHIFT 2
1404 #define QCA_RTC_SYNC_STATUS_SLEEP_MASK (1 << QCA_RTC_SYNC_STATUS_SLEEP_SHIFT)
1405 #define QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT 3
1406 #define QCA_RTC_SYNC_STATUS_WAKEUP_MASK (1 << QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT)
1407 #define QCA_RTC_SYNC_STATUS_WRESET_SHIFT 4
1408 #define QCA_RTC_SYNC_STATUS_WRESET_MASK (1 << QCA_RTC_SYNC_STATUS_WRESET_SHIFT)
1409 #define QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT 5
1410 #define QCA_RTC_SYNC_STATUS_PLL_CHANGING_MASK (1 << QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT)
1412 /* RTC_SYNC_FORCE_WAKE register (RTC force wake) */
1413 #define QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT 0
1414 #define QCA_RTC_SYNC_FORCE_WAKE_EN_MASK (1 << QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT)
1415 #define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT 1
1416 #define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_MASK (1 << QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT)
1419 * SPI serial flash registers
1421 #define QCA_SPI_FUNC_SEL_REG QCA_FLASH_BASE_REG + 0x00
1422 #define QCA_SPI_CTRL_REG QCA_FLASH_BASE_REG + 0x04
1423 #define QCA_SPI_IO_CTRL_REG QCA_FLASH_BASE_REG + 0x08
1424 #define QCA_SPI_READ_DATA_REG QCA_FLASH_BASE_REG + 0x0C
1425 #define QCA_SPI_SHIFT_DATAOUT_REG QCA_FLASH_BASE_REG + 0x10
1426 #define QCA_SPI_SHIFT_CNT_REG QCA_FLASH_BASE_REG + 0x14
1427 #define QCA_SPI_SHIFT_DATAIN_REG QCA_FLASH_BASE_REG + 0x18
1430 * SPI serial flash registers BIT fields
1433 /* SPI_FUNC_SELECT register (SPI function select) */
1434 #define QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT 0
1435 #define QCA_SPI_FUNC_SEL_FUNC_SEL_MASK (1 << QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT)
1437 /* SPI_CONTROL register (SPI control) */
1438 #define QCA_SPI_CTRL_CLK_DIV_SHIFT 0
1439 #define QCA_SPI_CTRL_CLK_DIV_MASK BITS(QCA_SPI_CTRL_CLK_DIV_SHIFT, 6)
1440 #define QCA_SPI_CTRL_REMAP_DIS_SHIFT 6
1441 #define QCA_SPI_CTRL_REMAP_DIS_MASK (1 << QCA_SPI_CTRL_REMAP_DIS_SHIFT)
1442 #define QCA_SPI_CTRL_SPI_RELOCATE_SHIFT 7
1443 #define QCA_SPI_CTRL_SPI_RELOCATE_MASK (1 << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT)
1444 #define QCA_SPI_CTRL_TSHSL_CNT_SHIFT 8
1445 #define QCA_SPI_CTRL_TSHSL_CNT_MASK BITS(QCA_SPI_CTRL_TSHSL_CNT_SHIFT, 6)
1447 /* SPI_IO_CONTROL register (SPI I/O control) */
1448 #define QCA_SPI_IO_CTRL_IO_DO_SHIFT 0
1449 #define QCA_SPI_IO_CTRL_IO_DO_MASK (1 << QCA_SPI_IO_CTRL_IO_DO_SHIFT)
1450 #define QCA_SPI_IO_CTRL_IO_CLK_SHIFT 8
1451 #define QCA_SPI_IO_CTRL_IO_CLK_MASK (1 << QCA_SPI_IO_CTRL_IO_CLK_SHIFT)
1452 #define QCA_SPI_IO_CTRL_IO_CS0_SHIFT 16
1453 #define QCA_SPI_IO_CTRL_IO_CS0_MASK (1 << QCA_SPI_IO_CTRL_IO_CS0_SHIFT)
1454 #define QCA_SPI_IO_CTRL_IO_CS1_SHIFT 17
1455 #define QCA_SPI_IO_CTRL_IO_CS1_MASK (1 << QCA_SPI_IO_CTRL_IO_CS1_SHIFT)
1456 #define QCA_SPI_IO_CTRL_IO_CS2_SHIFT 18
1457 #define QCA_SPI_IO_CTRL_IO_CS2_MASK (1 << QCA_SPI_IO_CTRL_IO_CS2_SHIFT)
1459 /* SPI_SHIFT_CNT_ADDR register (SPI content to shift out or in) */
1460 #define QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT 0
1461 #define QCA_SPI_SHIFT_CNT_BITS_CNT_MASK BITS(QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT, 7)
1462 #define QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT 26
1463 #define QCA_SPI_SHIFT_CNT_TERMINATE_MASK (1 << QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT)
1464 #define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT 27
1465 #define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_MASK (1 << QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT)
1466 #define QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT 28
1467 #define QCA_SPI_SHIFT_CNT_CHNL_CS0_MASK (1 << QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT)
1468 #define QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT 29
1469 #define QCA_SPI_SHIFT_CNT_CHNL_CS1_MASK (1 << QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT)
1470 #define QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT 30
1471 #define QCA_SPI_SHIFT_CNT_CHNL_CS2_MASK (1 << QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT)
1472 #define QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT 31
1473 #define QCA_SPI_SHIFT_CNT_SHIFT_EN_MASK (1 << QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT)
1476 * Other useful defines
1479 /* Magic flag for indication that PLL/clocks config is stored in FLASH */
1480 #define QCA_PLL_IN_FLASH_MAGIC 0x504C4C73
1482 /* Maximum DRAM size: 256 MB */
1483 #define QCA_DRAM_MAX_SIZE_VAL (256 * 1024 * 1024)
1488 #ifndef __ASSEMBLY__
1489 inline u32 qca_xtal_is_40mhz(void);
1490 void qca_soc_name_rev(char *buf);
1491 void qca_full_chip_reset(void);
1492 void qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk, u32 *spi_clk, u32 *ref_clk);
1493 void qca_sf_bulk_erase(u32 bank);
1494 void qca_sf_write_page(u32 bank, u32 address, u32 length, u8 *data);
1495 u32 qca_sf_sect_erase(u32 bank, u32 address, u32 sect_size, u8 erase_cmd);
1496 u32 qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_cmd);
1497 u32 qca_sf_jedec_id(u32 bank);
1498 u32 qca_dram_type(void);
1499 u32 qca_dram_size(void);
1500 void qca_dram_init(void);
1501 #endif /* !__ASSEMBLY__ */
1504 * Read, write, set and clear macros
1506 #define qca_soc_reg_read(_addr) *(volatile unsigned int *)(KSEG1ADDR(_addr))
1507 #define qca_soc_reg_write(_addr, _val) ((*(volatile unsigned int *)KSEG1ADDR(_addr)) = (_val))
1509 #define qca_soc_reg_read_set(_addr, _mask) \
1510 qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) | (_mask)))
1512 #define qca_soc_reg_read_clear(_addr, _mask) \
1513 qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) & ~(_mask)))
1515 #endif /* _QCA_SOC_COMMON_H_ */