2 * Qualcomm/Atheros Wireless SOC common registers definitions
4 * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
5 * Copyright (C) 2014 Qualcomm Atheros, Inc.
6 * Copyright (C) 2008-2010 Atheros Communications Inc.
9 * Linux/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
11 * SPDX-License-Identifier: GPL-2.0
14 #ifndef _QCA_SOC_COMMON_H_
15 #define _QCA_SOC_COMMON_H_
17 #include <soc/soc_common.h>
22 #define QCA_APB_BASE_REG 0x18000000
23 #define QCA_FLASH_BASE_REG 0x1F000000
24 #define QCA_PCIE_BASE_REG 0x10000000
29 #define QCA_DDR_CTRL_BASE_REG QCA_APB_BASE_REG + 0x00000000
31 #if (SOC_TYPE & QCA_AR933X_SOC)
32 #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000
34 #define QCA_LSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000
35 #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00500000
38 #define QCA_USB_CFG_BASE_REG QCA_APB_BASE_REG + 0x00030000
39 #define QCA_GPIO_BASE_REG QCA_APB_BASE_REG + 0x00040000
40 #define QCA_PLL_BASE_REG QCA_APB_BASE_REG + 0x00050000
41 #define QCA_RST_BASE_REG QCA_APB_BASE_REG + 0x00060000
42 #define QCA_GMAC_BASE_REG QCA_APB_BASE_REG + 0x00070000
43 #define QCA_RTC_BASE_REG QCA_APB_BASE_REG + 0x00107000
44 #define QCA_PLL_SRIF_BASE_REG QCA_APB_BASE_REG + 0x00116000
45 #define QCA_PCIE_RC0_CTRL_BASE_REG QCA_APB_BASE_REG + 0x000F0000
46 #define QCA_PCIE_RC1_CTRL_BASE_REG QCA_APB_BASE_REG + 0x00280000
48 #if (SOC_TYPE & QCA_AR933X_SOC)
49 #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x00090000
50 #elif (SOC_TYPE & QCA_AR934X_SOC) |\
51 (SOC_TYPE & QCA_AR955X_SOC)
52 #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x000A9000
56 * PCIE bridge address space
58 #define QCA_PCIE_RC0_SLAVE_CFG_BASE_REG QCA_PCIE_BASE_REG + 0x04000000
59 #define QCA_PCIE_RC1_SLAVE_CFG_BASE_REG QCA_PCIE_BASE_REG + 0x06000000
64 #define QCA_DDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x000
65 #define QCA_DDR_CFG2_REG QCA_DDR_CTRL_BASE_REG + 0x004
66 #define QCA_DDR_MR_REG QCA_DDR_CTRL_BASE_REG + 0x008
67 #define QCA_DDR_EMR_REG QCA_DDR_CTRL_BASE_REG + 0x00C
68 #define QCA_DDR_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x010
69 #define QCA_DDR_REFRESH_REG QCA_DDR_CTRL_BASE_REG + 0x014
70 #define QCA_DDR_RD_DATA_THIS_CYCLE_REG QCA_DDR_CTRL_BASE_REG + 0x018
71 #define QCA_DDR_TAP_CTRL_0_REG QCA_DDR_CTRL_BASE_REG + 0x01C
72 #define QCA_DDR_TAP_CTRL_1_REG QCA_DDR_CTRL_BASE_REG + 0x020
73 #define QCA_DDR_TAP_CTRL_2_REG QCA_DDR_CTRL_BASE_REG + 0x024
74 #define QCA_DDR_TAP_CTRL_3_REG QCA_DDR_CTRL_BASE_REG + 0x028
76 #if (SOC_TYPE & QCA_AR933X_SOC)
77 #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x07C
78 #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x080
79 #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x084
80 #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x08C
81 #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x090
82 #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x094
83 #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x098
84 #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x09C
85 #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0A0
86 #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0A4
87 #define QCA_SDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0D8
89 #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x09C
90 #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x0A0
91 #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x0A4
92 #define QCA_DDR_WB_FLUSH_PCIE_REG QCA_DDR_CTRL_BASE_REG + 0x0A8
93 #define QCA_DDR_WB_FLUSH_WMAC_REG QCA_DDR_CTRL_BASE_REG + 0x0AC
94 #define QCA_DDR_WB_FLUSH_SRC1_REG QCA_DDR_CTRL_BASE_REG + 0x0B0
95 #define QCA_DDR_WB_FLUSH_SRC2_REG QCA_DDR_CTRL_BASE_REG + 0x0B4
96 #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0B8
97 #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x0BC
98 #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x0C0
99 #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x0C4
100 #define QCA_DDR_BURST2_REG QCA_DDR_CTRL_BASE_REG + 0x0C8
101 #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x0CC
102 #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0D0
103 #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0D4
104 #define QCA_DDR_FSM_WAIT_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x0E4
105 #define QCA_DDR_CTRL_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x108
106 #define QCA_DDR_SELF_REFRESH_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x110
107 #define QCA_DDR_SELF_REFRESH_TIMER_REG QCA_DDR_CTRL_BASE_REG + 0x114
108 #define QCA_DDR_WMAC_FLUSH_REG QCA_DDR_CTRL_BASE_REG + 0x128
109 #define QCA_DDR_CFG3_REG QCA_DDR_CTRL_BASE_REG + 0x15C
112 * Below register addresses and names come directly form Atheros (Q)SDK code:
113 * tap-955x.S/tap-953x.S/tap-956x.S, as they do not exist in any datasheet
115 #define QCA_DDR_PERF_MASK_ADDR_0_REG QCA_DDR_CTRL_BASE_REG + 0x02C
116 #define QCA_DDR_PERF_MASK_AHB_GE0_0_REG QCA_DDR_CTRL_BASE_REG + 0x034
117 #define QCA_DDR_PERF_COMP_AHB_GE0_0_REG QCA_DDR_CTRL_BASE_REG + 0x038
118 #define QCA_DDR_PERF_MASK_AHB_GE1_0_REG QCA_DDR_CTRL_BASE_REG + 0x03C
119 #define QCA_DDR_PERF_COMP_AHB_GE1_0_REG QCA_DDR_CTRL_BASE_REG + 0x040
120 #define QCA_DDR_PERF_COMP_ADDR_1_REG QCA_DDR_CTRL_BASE_REG + 0x068
121 #define QCA_DDR_PERF_MASK_AHB_GE0_1_REG QCA_DDR_CTRL_BASE_REG + 0x06C
122 #define QCA_DDR_PERF_COMP_AHB_GE0_1_REG QCA_DDR_CTRL_BASE_REG + 0x070
123 #define QCA_DDR_PERF_MASK_AHB_GE1_1_REG QCA_DDR_CTRL_BASE_REG + 0x074
124 #define QCA_DDR_PERF_COMP_AHB_GE1_1_REG QCA_DDR_CTRL_BASE_REG + 0x078
125 #define QCA_DDR_BIST_REG QCA_DDR_CTRL_BASE_REG + 0x11C
126 #define QCA_DDR_BIST_STATUS_REG QCA_DDR_CTRL_BASE_REG + 0x120
130 * DDR registers BIT fields
133 /* DDR_CONFIG register (DDR DRAM configuration) */
134 #define QCA_DDR_CFG_TRAS_SHIFT 0
135 #define QCA_DDR_CFG_TRAS_MASK BITS(QCA_DDR_CFG_TRAS_SHIFT, 5)
136 #define QCA_DDR_CFG_TRCD_SHIFT 5
137 #define QCA_DDR_CFG_TRCD_MASK BITS(QCA_DDR_CFG_TRCD_SHIFT, 4)
138 #define QCA_DDR_CFG_TRP_SHIFT 9
139 #define QCA_DDR_CFG_TRP_MASK BITS(QCA_DDR_CFG_TRP_SHIFT, 4)
140 #define QCA_DDR_CFG_TRRD_SHIFT 13
141 #define QCA_DDR_CFG_TRRD_MASK BITS(QCA_DDR_CFG_TRRD_SHIFT, 4)
142 #define QCA_DDR_CFG_TRFC_SHIFT 17
143 #define QCA_DDR_CFG_TRFC_MASK BITS(QCA_DDR_CFG_TRFC_SHIFT, 6)
144 #define QCA_DDR_CFG_TMRD_SHIFT 23
145 #define QCA_DDR_CFG_TMRD_MASK BITS(QCA_DDR_CFG_TMRD_SHIFT, 4)
146 #define QCA_DDR_CFG_CAS_3LSB_SHIFT 27
147 #define QCA_DDR_CFG_CAS_3LSB_MASK BITS(QCA_DDR_CFG_CAS_3LSB_SHIFT, 3)
148 #define QCA_DDR_CFG_PAGE_CLOSE_SHIFT 30
149 #define QCA_DDR_CFG_PAGE_CLOSE_MASK BIT(QCA_DDR_CFG_PAGE_CLOSE_SHIFT)
150 #define QCA_DDR_CFG_CAS_MSB_SHIFT 31
151 #define QCA_DDR_CFG_CAS_MSB_MASK BIT(QCA_DDR_CFG_CAS_MSB_SHIFT)
153 /* DDR_CONFIG2 register (DDR DRAM configuration 2) */
154 #define QCA_DDR_CFG2_BURST_LEN_SHIFT 0
155 #define QCA_DDR_CFG2_BURST_LEN_MASK BITS(QCA_DDR_CFG2_BURST_LEN_SHIFT, 4)
156 #define QCA_DDR_CFG2_BURST_TYPE_SHIFT 4
157 #define QCA_DDR_CFG2_BURST_TYPE_MASK BIT(QCA_DDR_CFG2_BURST_TYPE_SHIFT)
158 #define QCA_DDR_CFG2_CTRL_OE_EN_SHIFT 5
159 #define QCA_DDR_CFG2_CTRL_OE_EN_MASK BIT(QCA_DDR_CFG2_CTRL_OE_EN_SHIFT)
160 #define QCA_DDR_CFG2_PHASE_SEL_SHIFT 6
161 #define QCA_DDR_CFG2_PHASE_SEL_MASK BIT(QCA_DDR_CFG2_PHASE_SEL_SHIFT)
162 #define QCA_DDR_CFG2_CKE_SHIFT 7
163 #define QCA_DDR_CFG2_CKE_MASK BIT(QCA_DDR_CFG2_CKE_SHIFT)
164 #define QCA_DDR_CFG2_TWR_SHIFT 8
165 #define QCA_DDR_CFG2_TWR_MASK BITS(QCA_DDR_CFG2_TWR_SHIFT, 4)
166 #define QCA_DDR_CFG2_TRTW_SHIFT 12
167 #define QCA_DDR_CFG2_TRTW_MASK BITS(QCA_DDR_CFG2_TRTW_SHIFT, 5)
168 #define QCA_DDR_CFG2_TRTP_SHIFT 17
169 #define QCA_DDR_CFG2_TRTP_MASK BITS(QCA_DDR_CFG2_TRTP_SHIFT, 4)
170 #define QCA_DDR_CFG2_TWTR_SHIFT 21
171 #define QCA_DDR_CFG2_TWTR_MASK BITS(QCA_DDR_CFG2_TWTR_SHIFT, 5)
172 #define QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT 26
173 #define QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK BITS(QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT, 4)
174 #define QCA_DDR_CFG2_SWAP_A26_A27_SHIFT 30
175 #define QCA_DDR_CFG2_SWAP_A26_A27_MASK BIT(QCA_DDR_CFG2_SWAP_A26_A27_SHIFT)
176 #define QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT 31
177 #define QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK BIT(QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT)
179 /* DDR_MODE register (DDR mode register value) */
180 #define QCA_DDR_MR_VALUE_SHIFT 0
181 #define QCA_DDR_MR_VALUE_MASK BITS(QCA_DDR_MR_VALUE_SHIFT, 14)
183 /* DDR_EMR registers (DDR extended mode register 1/2/3 values) */
184 #define QCA_DDR_EMR_VALUE_SHIFT 0
185 #define QCA_DDR_EMR_VALUE_MASK BITS(QCA_DDR_EMR_VALUE_SHIFT, 14)
187 /* DDR_CONTROL register (DDR control) */
188 #define QCA_DDR_CTRL_FORCE_MRS_SHIFT 0
189 #define QCA_DDR_CTRL_FORCE_MRS_MASK BIT(QCA_DDR_CTRL_FORCE_MRS_SHIFT)
190 #define QCA_DDR_CTRL_FORCE_EMRS_SHIFT 1
191 #define QCA_DDR_CTRL_FORCE_EMRS_MASK BIT(QCA_DDR_CTRL_FORCE_EMRS_SHIFT)
192 #define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT 2
193 #define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK BIT(QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT)
194 #define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT 3
195 #define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK BIT(QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT)
196 #define QCA_DDR_CTRL_FORCE_EMR2S_SHIFT 4
197 #define QCA_DDR_CTRL_FORCE_EMR2S_MASK BIT(QCA_DDR_CTRL_FORCE_EMR2S_SHIFT)
198 #define QCA_DDR_CTRL_FORCE_EMR3S_SHIFT 5
199 #define QCA_DDR_CTRL_FORCE_EMR3S_MASK BIT(QCA_DDR_CTRL_FORCE_EMR3S_SHIFT)
201 /* DDR_REFRESH register (DDR refresh control and configuration) */
202 #define QCA_DDR_REFRESH_PERIOD_SHIFT 0
203 #define QCA_DDR_REFRESH_PERIOD_MASK BITS(QCA_DDR_REFRESH_PERIOD_SHIFT, 14)
204 #define QCA_DDR_REFRESH_EN_SHIFT 14
205 #define QCA_DDR_REFRESH_EN_MASK BIT(QCA_DDR_REFRESH_EN_SHIFT)
207 /* DDR_RD_DATA_THIS_CYCLE register (DDR read data capture bit mask) */
208 #define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT 0
209 #define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_MASK BITS(QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT, 32)
211 /* TAP_CONTROL_X registers (DQS delay tap control for byte X) */
212 #if (SOC_TYPE & QCA_AR933X_SOC) |\
213 (SOC_TYPE & QCA_AR934X_SOC)
214 #define QCA_DDR_TAP_CTRL_TAP_L_SHIFT 0
215 #define QCA_DDR_TAP_CTRL_TAP_L_MASK BITS(QCA_DDR_TAP_CTRL_TAP_L_SHIFT, 5)
216 #define QCA_DDR_TAP_CTRL_TAP_H_SHIFT 8
217 #define QCA_DDR_TAP_CTRL_TAP_H_MASK BITS(QCA_DDR_TAP_CTRL_TAP_H_SHIFT, 5)
218 #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT 16
219 #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_MASK BIT(QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT)
221 #define QCA_DDR_TAP_CTRL_TAP_SHIFT 0
222 #define QCA_DDR_TAP_CTRL_TAP_MASK BITS(QCA_DDR_TAP_CTRL_TAP_SHIFT, 6)
225 /* DDR_DDR2_CONFIG register (DDR2 configuration) */
226 #define QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT 0
227 #define QCA_DDR_DDR2_CFG_DDR2_EN_MASK BIT(QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT)
228 #define QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT 2
229 #define QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT, 6)
230 #if (SOC_TYPE & QCA_AR933X_SOC)
231 #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT 10
232 #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 3)
234 #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT 10
235 #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 4)
238 /* DDR_BURST (DDR bank arbiter per client burst size) */
239 #define QCA_DDR_BURST_GE0_MAX_BL_SHIFT 0
240 #define QCA_DDR_BURST_GE0_MAX_BL_MASK BITS(QCA_DDR_BURST_GE0_MAX_BL_SHIFT, 4)
241 #define QCA_DDR_BURST_GE1_MAX_BL_SHIFT 4
242 #define QCA_DDR_BURST_GE1_MAX_BL_MASK BITS(QCA_DDR_BURST_GE1_MAX_BL_SHIFT, 4)
243 #define QCA_DDR_BURST_PCIE_MAX_BL_SHIFT 8
244 #define QCA_DDR_BURST_PCIE_MAX_BL_MASK BITS(QCA_DDR_BURST_PCIE_MAX_BL_SHIFT, 4)
245 #define QCA_DDR_BURST_USB_MAX_BL_SHIFT 12
246 #define QCA_DDR_BURST_USB_MAX_BL_MASK BITS(QCA_DDR_BURST_USB_MAX_BL_SHIFT, 4)
247 #define QCA_DDR_BURST_CPU_MAX_BL_SHIFT 16
248 #define QCA_DDR_BURST_CPU_MAX_BL_MASK BITS(QCA_DDR_BURST_CPU_MAX_BL_SHIFT, 4)
249 #define QCA_DDR_BURST_MAX_READ_BURST_SHIFT 20
250 #define QCA_DDR_BURST_MAX_READ_BURST_MASK BITS(QCA_DDR_BURST_MAX_READ_BURST_SHIFT, 4)
251 #define QCA_DDR_BURST_MAX_WRITE_BURST_SHIFT 24
252 #define QCA_DDR_BURST_MAX_WRITE_BURST_MASK BITS(QCA_DDR_BURST_MAX_WRITE_BURST_SHIFT, 4)
253 #define QCA_DDR_BURST_RWP_MASK_EN_SHIFT 28
254 #define QCA_DDR_BURST_RWP_MASK_EN_MASK BITS(QCA_DDR_BURST_RWP_MASK_EN_SHIFT, 2)
255 #define QCA_DDR_BURST_CPU_PRIO_BE_SHIFT 30
256 #define QCA_DDR_BURST_CPU_PRIO_BE_MASK BIT(QCA_DDR_BURST_CPU_PRIO_BE_SHIFT)
257 #define QCA_DDR_BURST_CPU_PRIO_SHIFT 31
258 #define QCA_DDR_BURST_CPU_PRIO_MASK BIT(QCA_DDR_BURST_CPU_PRIO_SHIFT)
260 /* DDR_BURST2 (DDR bank arbiter per client burst size 2) */
261 #define QCA_DDR_BURST2_WMAC_MAX_BL_SHIFT 0
262 #define QCA_DDR_BURST2_WMAC_MAX_BL_MASK BITS(QCA_DDR_BURST2_WMAC_MAX_BL_SHIFT, 4)
263 #define QCA_DDR_BURST2_MISC_SRC1_MAX_BL_SHIFT 4
264 #define QCA_DDR_BURST2_MISC_SRC1_MAX_BL_MASK BITS(QCA_DDR_BURST2_MISC_SRC1_MAX_BL_SHIFT, 4)
265 #define QCA_DDR_BURST2_MISC_SRC2_MAX_BL_SHIFT 8
266 #define QCA_DDR_BURST2_MISC_SRC2_MAX_BL_MASK BITS(QCA_DDR_BURST2_MISC_SRC2_MAX_BL_SHIFT, 4)
268 /* DDR_CTRL_CFG (DDR controller configuration) */
269 #define QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT 0
270 #define QCA_DDR_CTRL_CFG_SDRAM_EN_MASK BIT(QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT)
271 #define QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT 1
272 #define QCA_DDR_CTRL_CFG_HALF_WIDTH_MASK BIT(QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT)
273 #define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT 2
274 #define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_MASK BIT(QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT)
275 #define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT 3
276 #define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_MASK BIT(QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT)
277 #define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT 4
278 #define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_MASK BIT(QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT)
279 #define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT 6
280 #define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_MASK BIT(QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT)
282 /* DDR_CONFIG3 register (DDR DRAM configuration 3) */
283 #define QCA_DDR_CFG3_TRFC_LSB_SHIFT 0
284 #define QCA_DDR_CFG3_TRFC_LSB_MASK BITS(QCA_DDR_CFG3_TRFC_LSB_SHIFT, 2)
285 #define QCA_DDR_CFG3_TRAS_MSB_SHIFT 2
286 #define QCA_DDR_CFG3_TRAS_MSB_MASK BIT(QCA_DDR_CFG3_TRAS_MSB_SHIFT)
287 #define QCA_DDR_CFG3_TWR_MSB_SHIFT 3
288 #define QCA_DDR_CFG3_TWR_MSB_MASK BIT(QCA_DDR_CFG3_TWR_MSB_SHIFT)
290 /* DDR_BIST (unknown, not described in datasheet, based on code only) */
291 #define QCA_DDR_BIST_TEST_EN_SHIFT 0
292 #define QCA_DDR_BIST_TEST_EN_MASK BIT(QCA_DDR_BIST_TEST_EN_SHIFT)
294 /* DDR_BIST_STATUS (unknown, not described in datasheet, based on code only) */
295 #define QCA_DDR_BIST_STATUS_DONE_SHIFT 0
296 #define QCA_DDR_BIST_STATUS_DONE_MASK BIT(QCA_DDR_BIST_STATUS_DONE_SHIFT)
297 #define QCA_DDR_BIST_STATUS_PASS_CNT_SHIFT 1
298 #define QCA_DDR_BIST_STATUS_PASS_CNT_MASK BITS(QCA_DDR_BIST_STATUS_PASS_CNT_SHIFT, 8)
299 #define QCA_DDR_BIST_STATUS_FAIL_CNT_SHIFT 9
300 #define QCA_DDR_BIST_STATUS_FAIL_CNT_MASK BITS(QCA_DDR_BIST_STATUS_FAIL_CNT_SHIFT, 8)
302 /* DDR_PERF_COMP_ADDR_1 (unknown, not described in datasheet, based on code only) */
303 #define QCA_DDR_PERF_COMP_ADDR_1_TEST_CNT_SHIFT 1
304 #define QCA_DDR_PERF_COMP_ADDR_1_TEST_CNT_MASK BITS(QCA_DDR_PERF_COMP_ADDR_1_TEST_CNT_SHIFT, 8)
307 * Low-Speed UART registers
309 #define QCA_LSUART_RBR_REG QCA_LSUART_BASE_REG + 0x00
310 #define QCA_LSUART_THR_REG QCA_LSUART_BASE_REG + 0x00
311 #define QCA_LSUART_DLL_REG QCA_LSUART_BASE_REG + 0x00
312 #define QCA_LSUART_DLH_REG QCA_LSUART_BASE_REG + 0x04
313 #define QCA_LSUART_IER_REG QCA_LSUART_BASE_REG + 0x04
314 #define QCA_LSUART_IIR_REG QCA_LSUART_BASE_REG + 0x08
315 #define QCA_LSUART_FCR_REG QCA_LSUART_BASE_REG + 0x08
316 #define QCA_LSUART_LCR_REG QCA_LSUART_BASE_REG + 0x0C
317 #define QCA_LSUART_MCR_REG QCA_LSUART_BASE_REG + 0x10
318 #define QCA_LSUART_LSR_REG QCA_LSUART_BASE_REG + 0x14
319 #define QCA_LSUART_MSR_REG QCA_LSUART_BASE_REG + 0x18
322 * Low-Speed UART registers BIT fields
325 /* RBR register (Receive buffer) */
326 #define QCA_LSUART_RBR_RBR_SHIFT 0
327 #define QCA_LSUART_RBR_RBR_MASK BITS(QCA_LSUART_RBR_RBR_SHIFT, 8)
329 /* THR register (Transmit holding) */
330 #define QCA_LSUART_THR_THR_SHIFT 0
331 #define QCA_LSUART_THR_THR_MASK BITS(QCA_LSUART_THR_THR_SHIFT, 8)
333 /* DLL register (Divisor latch low) */
334 #define QCA_LSUART_DLL_DLL_SHIFT 0
335 #define QCA_LSUART_DLL_DLL_MASK BITS(QCA_LSUART_DLL_DLL_SHIFT, 8)
337 /* DLH register (Divisor latch high) */
338 #define QCA_LSUART_DLH_DLH_SHIFT 0
339 #define QCA_LSUART_DLH_DLH_MASK BITS(QCA_LSUART_DLH_DLH_SHIFT, 8)
341 /* IER register (Interrupt enable) */
342 #define QCA_LSUART_IER_ERBFI_SHIFT 0
343 #define QCA_LSUART_IER_ERBFI_MASK BIT(QCA_LSUART_IER_ERBFI_SHIFT)
344 #define QCA_LSUART_IER_ETBEI_SHIFT 1
345 #define QCA_LSUART_IER_ETBEI_MASK BIT(QCA_LSUART_IER_ETBEI_SHIFT)
346 #define QCA_LSUART_IER_ELSI_SHIFT 2
347 #define QCA_LSUART_IER_ELSI_MASK BIT(QCA_LSUART_IER_ELSI_SHIFT)
348 #define QCA_LSUART_IER_EDDSI_SHIFT 3
349 #define QCA_LSUART_IER_EDDSI_MASK BIT(QCA_LSUART_IER_EDDSI_SHIFT)
351 /* IIR register (Interrupt identity) */
352 #define QCA_LSUART_IIR_IID_SHIFT 0
353 #define QCA_LSUART_IIR_IID_MASK BITS(QCA_LSUART_IIR_IID_SHIFT, 4)
354 #define QCA_LSUART_IIR_FIFO_STATUS_SHIFT 6
355 #define QCA_LSUART_IIR_FIFO_STATUS_MASK BITS(QCA_LSUART_IIR_FIFO_STATUS_SHIFT, 2)
357 /* FCR register (FIFO control) */
358 #define QCA_LSUART_FCR_FIFO_EN_SHIFT 0
359 #define QCA_LSUART_FCR_EDDSI_MASK BIT(QCA_LSUART_FCR_FIFO_EN_SHIFT)
360 #define QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT 1
361 #define QCA_LSUART_FCR_RCVR_FIFO_RST_MASK BIT(QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT)
362 #define QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT 2
363 #define QCA_LSUART_FCR_XMIT_FIFO_RST_MASK BIT(QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT)
364 #define QCA_LSUART_FCR_DMA_MODE_SHIFT 3
365 #define QCA_LSUART_FCR_DMA_MODE_MASK BIT(QCA_LSUART_FCR_DMA_MODE_SHIFT)
366 #define QCA_LSUART_FCR_RCVR_TRIG_SHIFT 6
367 #define QCA_LSUART_FCR_RCVR_TRIG_MASK BITS(QCA_LSUART_FCR_RCVR_TRIG_SHIFT, 2)
369 /* LCR register (Line control) */
370 #define QCA_LSUART_LCR_CLS_SHIFT 0
371 #define QCA_LSUART_LCR_CLS_MASK BITS(QCA_LSUART_LCR_CLS_SHIFT, 2)
372 #define QCA_LSUART_LCR_CLS_5BIT_VAL 0x0
373 #define QCA_LSUART_LCR_CLS_6BIT_VAL 0x1
374 #define QCA_LSUART_LCR_CLS_7BIT_VAL 0x2
375 #define QCA_LSUART_LCR_CLS_8BIT_VAL 0x3
376 #define QCA_LSUART_LCR_STOP_SHIFT 2
377 #define QCA_LSUART_LCR_STOP_MASK BIT(QCA_LSUART_LCR_STOP_SHIFT)
378 #define QCA_LSUART_LCR_PEN_SHIFT 3
379 #define QCA_LSUART_LCR_PEN_MASK BIT(QCA_LSUART_LCR_PEN_SHIFT)
380 #define QCA_LSUART_LCR_EPS_SHIFT 4
381 #define QCA_LSUART_LCR_EPS_MASK BIT(QCA_LSUART_LCR_EPS_SHIFT)
382 #define QCA_LSUART_LCR_BREAK_SHIFT 6
383 #define QCA_LSUART_LCR_BREAK_MASK BIT(QCA_LSUART_LCR_BREAK_SHIFT)
384 #define QCA_LSUART_LCR_DLAB_SHIFT 7
385 #define QCA_LSUART_LCR_DLAB_MASK BIT(QCA_LSUART_LCR_DLAB_SHIFT)
387 /* MCR register (Modem control) */
388 #define QCA_LSUART_MCR_DTR_SHIFT 0
389 #define QCA_LSUART_MCR_DTR_MASK BIT(QCA_LSUART_MCR_DTR_SHIFT)
390 #define QCA_LSUART_MCR_RTS_SHIFT 1
391 #define QCA_LSUART_MCR_RTS_MASK BIT(QCA_LSUART_MCR_RTS_SHIFT)
392 #define QCA_LSUART_MCR_OUT1_SHIFT 2
393 #define QCA_LSUART_MCR_OUT1_MASK BIT(QCA_LSUART_MCR_OUT1_SHIFT)
394 #define QCA_LSUART_MCR_OUT2_SHIFT 3
395 #define QCA_LSUART_MCR_OUT2_MASK BIT(QCA_LSUART_MCR_OUT2_SHIFT)
396 #define QCA_LSUART_MCR_LOOPBACK_SHIFT 5
397 #define QCA_LSUART_MCR_LOOPBACK_MASK BIT(QCA_LSUART_MCR_LOOPBACK_SHIFT)
399 /* LSR register (Line status) */
400 #define QCA_LSUART_LSR_DR_SHIFT 0
401 #define QCA_LSUART_LSR_DR_MASK BIT(QCA_LSUART_LSR_DR_SHIFT)
402 #define QCA_LSUART_LSR_OE_SHIFT 1
403 #define QCA_LSUART_LSR_OE_MASK BIT(QCA_LSUART_LSR_OE_SHIFT)
404 #define QCA_LSUART_LSR_PE_SHIFT 2
405 #define QCA_LSUART_LSR_PE_MASK BIT(QCA_LSUART_LSR_PE_SHIFT)
406 #define QCA_LSUART_LSR_FE_SHIFT 3
407 #define QCA_LSUART_LSR_FE_MASK BIT(QCA_LSUART_LSR_FE_SHIFT)
408 #define QCA_LSUART_LSR_BI_SHIFT 4
409 #define QCA_LSUART_LSR_BI_MASK BIT(QCA_LSUART_LSR_BI_SHIFT)
410 #define QCA_LSUART_LSR_THRE_SHIFT 5
411 #define QCA_LSUART_LSR_THRE_MASK BIT(QCA_LSUART_LSR_THRE_SHIFT)
412 #define QCA_LSUART_LSR_TEMT_SHIFT 6
413 #define QCA_LSUART_LSR_TEMT_MASK BIT(QCA_LSUART_LSR_TEMT_SHIFT)
414 #define QCA_LSUART_LSR_FERR_SHIFT 7
415 #define QCA_LSUART_LSR_FERR_MASK BIT(QCA_LSUART_LSR_FERR_SHIFT)
417 /* MCR register (Modem status) */
418 #define QCA_LSUART_MCR_DCTS_SHIFT 0
419 #define QCA_LSUART_MCR_DCTS_MASK BIT(QCA_LSUART_MCR_DCTS_SHIFT)
420 #define QCA_LSUART_MCR_DDSR_SHIFT 1
421 #define QCA_LSUART_MCR_DDSR_MASK BIT(QCA_LSUART_MCR_DDSR_SHIFT)
422 #define QCA_LSUART_MCR_TERI_SHIFT 2
423 #define QCA_LSUART_MCR_TERI_MASK BIT(QCA_LSUART_MCR_TERI_SHIFT)
424 #define QCA_LSUART_MCR_DDCD_SHIFT 3
425 #define QCA_LSUART_MCR_DDCD_MASK BIT(QCA_LSUART_MCR_DDCD_SHIFT)
426 #define QCA_LSUART_MCR_CTS_SHIFT 4
427 #define QCA_LSUART_MCR_CTS_MASK BIT(QCA_LSUART_MCR_CTS_SHIFT)
428 #define QCA_LSUART_MCR_DSR_SHIFT 5
429 #define QCA_LSUART_MCR_DSR_MASK BIT(QCA_LSUART_MCR_DSR_SHIFT)
430 #define QCA_LSUART_MCR_RI_SHIFT 6
431 #define QCA_LSUART_MCR_RI_MASK BIT(QCA_LSUART_MCR_RI_SHIFT)
432 #define QCA_LSUART_MCR_DCD_SHIFT 7
433 #define QCA_LSUART_MCR_DCD_MASK BIT(QCA_LSUART_MCR_DCD_SHIFT)
436 * High-Speed UART registers
438 #define QCA_HSUART_DATA_REG QCA_HSUART_BASE_REG + 0x00
439 #define QCA_HSUART_CS_REG QCA_HSUART_BASE_REG + 0x04
440 #define QCA_HSUART_CLK_REG QCA_HSUART_BASE_REG + 0x08
441 #define QCA_HSUART_INT_REG QCA_HSUART_BASE_REG + 0x0C
442 #define QCA_HSUART_INT_EN_REG QCA_HSUART_BASE_REG + 0x10
445 * High-Speed UART registers BIT fields
448 /* UART_DATA register (UART transmit and RX FIFO interface ) */
449 #define QCA_HSUART_DATA_TX_RX_DATA_SHIFT 0
450 #define QCA_HSUART_DATA_TX_RX_DATA_MASK BITS(QCA_HSUART_DATA_TX_RX_DATA_SHIFT, 8)
451 #define QCA_HSUART_DATA_RX_CSR_SHIFT 8
452 #define QCA_HSUART_DATA_RX_CSR_MASK BIT(QCA_HSUART_DATA_RX_CSR_SHIFT)
453 #define QCA_HSUART_DATA_TX_CSR_SHIFT 9
454 #define QCA_HSUART_DATA_TX_CSR_MASK BIT(QCA_HSUART_DATA_TX_CSR_SHIFT)
456 /* UART_CS register (UART configuration and status) */
457 #define QCA_HSUART_CS_PAR_MODE_SHIFT 0
458 #define QCA_HSUART_CS_PAR_MODE_MASK BITS(QCA_HSUART_CS_PAR_MODE_SHIFT, 2)
459 #define QCA_HSUART_CS_PAR_MODE_NO_VAL 0x0
460 #define QCA_HSUART_CS_PAR_MODE_ODD_VAL 0x2
461 #define QCA_HSUART_CS_PAR_MODE_OVEN_VAL 0x3
462 #define QCA_HSUART_CS_IFACE_MODE_SHIFT 2
463 #define QCA_HSUART_CS_IFACE_MODE_MASK BITS(QCA_HSUART_CS_IFACE_MODE_SHIFT, 2)
464 #define QCA_HSUART_CS_IFACE_MODE_DISABLE_VAL 0x0
465 #define QCA_HSUART_CS_IFACE_MODE_DTE_VAL 0x1
466 #define QCA_HSUART_CS_IFACE_MODE_DCE_VAL 0x2
467 #define QCA_HSUART_CS_FLOW_MODE_SHIFT 4
468 #define QCA_HSUART_CS_FLOW_MODE_MASK BITS(QCA_HSUART_CS_FLOW_MODE_SHIFT, 2)
469 #define QCA_HSUART_CS_FLOW_MODE_NO_VAL 0x0
470 #define QCA_HSUART_CS_FLOW_MODE_HW_VAL 0x2
471 #define QCA_HSUART_CS_FLOW_MODE_INV_VAL 0x3
472 #define QCA_HSUART_CS_DMA_EN_SHIFT 6
473 #define QCA_HSUART_CS_DMA_EN_MASK BIT(QCA_HSUART_CS_DMA_EN_SHIFT)
474 #define QCA_HSUART_CS_RX_READY_ORIDE_SHIFT 7
475 #define QCA_HSUART_CS_RX_READY_ORIDE_MASK BIT(QCA_HSUART_CS_RX_READY_ORIDE_SHIFT)
476 #define QCA_HSUART_CS_TX_READY_ORIDE_SHIFT 8
477 #define QCA_HSUART_CS_TX_READY_ORIDE_MASK BIT(QCA_HSUART_CS_TX_READY_ORIDE_SHIFT)
478 #define QCA_HSUART_CS_TX_READY_SHIFT 9
479 #define QCA_HSUART_CS_TX_READY_MASK BIT(QCA_HSUART_CS_TX_READY_SHIFT)
480 #define QCA_HSUART_CS_RX_BREAK_SHIFT 10
481 #define QCA_HSUART_CS_RX_BREAK_MASK BIT(QCA_HSUART_CS_RX_BREAK_SHIFT)
482 #define QCA_HSUART_CS_TX_BREAK_SHIFT 11
483 #define QCA_HSUART_CS_TX_BREAK_MASK BIT(QCA_HSUART_CS_TX_BREAK_SHIFT)
484 #define QCA_HSUART_CS_HOST_INT_SHIFT 12
485 #define QCA_HSUART_CS_HOST_INT_MASK BIT(QCA_HSUART_CS_HOST_INT_SHIFT)
486 #define QCA_HSUART_CS_HOST_INT_EN_SHIFT 13
487 #define QCA_HSUART_CS_HOST_INT_EN_MASK BIT(QCA_HSUART_CS_HOST_INT_EN_SHIFT)
488 #define QCA_HSUART_CS_TX_BUSY_SHIFT 14
489 #define QCA_HSUART_CS_TX_BUSY_MASK BIT(QCA_HSUART_CS_TX_BUSY_SHIFT)
490 #define QCA_HSUART_CS_RX_BUSY_SHIFT 15
491 #define QCA_HSUART_CS_RX_BUSY_MASK BIT(QCA_HSUART_CS_RX_BUSY_SHIFT)
493 /* UART_CLOCK register (UART clock) */
494 #define QCA_HSUART_CLK_STEP_SHIFT 0
495 #define QCA_HSUART_CLK_STEP_MASK BITS(QCA_HSUART_CLK_STEP_SHIFT, 16)
496 #define QCA_HSUART_CLK_STEP_MAX_VAL 0x3333
497 #define QCA_HSUART_CLK_SCALE_SHIFT 16
498 #define QCA_HSUART_CLK_SCALE_MASK BITS(QCA_HSUART_CLK_SCALE_SHIFT, 8)
499 #define QCA_HSUART_CLK_SCALE_MAX_VAL 0xFF
501 /* UART_INT register (UART interrupt/control status) */
502 #define QCA_HSUART_INT_RX_VALID_SHIFT 0
503 #define QCA_HSUART_INT_RX_VALID_MASK BIT(QCA_HSUART_INT_RX_VALID_SHIFT)
504 #define QCA_HSUART_INT_TX_READY_SHIFT 1
505 #define QCA_HSUART_INT_TX_READY_MASK BIT(QCA_HSUART_INT_TX_READY_SHIFT)
506 #define QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT 2
507 #define QCA_HSUART_INT_RX_FRAMING_ERR_MASK BIT(QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT)
508 #define QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT 3
509 #define QCA_HSUART_INT_RX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT)
510 #define QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT 4
511 #define QCA_HSUART_INT_TX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT)
512 #define QCA_HSUART_INT_RX_PARITY_ERR_SHIFT 5
513 #define QCA_HSUART_INT_RX_PARITY_ERR_MASK BIT(QCA_HSUART_INT_RX_PARITY_ERR_SHIFT)
514 #define QCA_HSUART_INT_RX_BREAK_ON_SHIFT 6
515 #define QCA_HSUART_INT_RX_BREAK_ON_MASK BIT(QCA_HSUART_INT_RX_BREAK_ON_SHIFT)
516 #define QCA_HSUART_INT_RX_BREAK_OFF_SHIFT 7
517 #define QCA_HSUART_INT_RX_BREAK_OFF_MASK BIT(QCA_HSUART_INT_RX_BREAK_OFF_SHIFT)
518 #define QCA_HSUART_INT_RX_FULL_SHIFT 8
519 #define QCA_HSUART_INT_RX_FULL_MASK BIT(QCA_HSUART_INT_RX_FULL_SHIFT)
520 #define QCA_HSUART_INT_TX_EMPTY_SHIFT 9
521 #define QCA_HSUART_INT_TX_EMPTY_MASK BIT(QCA_HSUART_INT_TX_EMPTY_SHIFT)
523 /* UART_INT_EN register (UART interrupt enable) */
524 #define QCA_HSUART_INT_EN_RX_VALID_SHIFT 0
525 #define QCA_HSUART_INT_EN_RX_VALID_MASK BIT(QCA_HSUART_INT_EN_RX_VALID_SHIFT)
526 #define QCA_HSUART_INT_EN_TX_READY_SHIFT 1
527 #define QCA_HSUART_INT_EN_TX_READY_MASK BIT(QCA_HSUART_INT_EN_TX_READY_SHIFT)
528 #define QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT 2
529 #define QCA_HSUART_INT_EN_RX_FRAMING_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT)
530 #define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT 3
531 #define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT)
532 #define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT 4
533 #define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT)
534 #define QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT 5
535 #define QCA_HSUART_INT_EN_RX_PARITY_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT)
536 #define QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT 6
537 #define QCA_HSUART_INT_EN_RX_BREAK_ON_MASK BIT(QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT)
538 #define QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT 7
539 #define QCA_HSUART_INT_EN_RX_BREAK_OFF_MASK BIT(QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT)
540 #define QCA_HSUART_INT_EN_RX_FULL_SHIFT 8
541 #define QCA_HSUART_INT_EN_RX_FULL_MASK BIT(QCA_HSUART_INT_EN_RX_FULL_SHIFT)
542 #define QCA_HSUART_INT_EN_TX_EMPTY_SHIFT 9
543 #define QCA_HSUART_INT_EN_TX_EMPTY_MASK BIT(QCA_HSUART_INT_EN_TX_EMPTY_SHIFT)
549 #if (SOC_TYPE & QCA_AR933X_SOC)
550 #define QCA_GPIO_COUNT 30
551 #elif (SOC_TYPE & QCA_AR934X_SOC)
552 #if (SOC_TYPE & QCA_AR9342_SOC)
553 #define QCA_GPIO_COUNT 18
555 #define QCA_GPIO_COUNT 23
557 #elif (SOC_TYPE & QCA_QCA953X_SOC)
558 #define QCA_GPIO_COUNT 18
559 #elif (SOC_TYPE & QCA_QCA955X_SOC)
560 #define QCA_GPIO_COUNT 24
561 #elif (SOC_TYPE & QCA_QCA956X_SOC)
562 #define QCA_GPIO_COUNT 23
565 /* JTAG GPIO pin mask */
566 #if (SOC_TYPE & QCA_AR933X_SOC)
567 #define QCA_GPIO_JTAG_MASK 0x200001C0 /* GPIO6~8, GPIO29 */
568 #elif (SOC_TYPE & QCA_QCA956X_SOC)
569 #define QCA_GPIO_JTAG_MASK 0x3C000 /* GPIO14~17 */
571 #define QCA_GPIO_JTAG_MASK 0x0000F /* GPIO0~3 */
574 #define QCA_GPIO_OE_REG QCA_GPIO_BASE_REG + 0x00
575 #define QCA_GPIO_IN_REG QCA_GPIO_BASE_REG + 0x04
576 #define QCA_GPIO_OUT_REG QCA_GPIO_BASE_REG + 0x08
577 #define QCA_GPIO_SET_REG QCA_GPIO_BASE_REG + 0x0C
578 #define QCA_GPIO_CLEAR_REG QCA_GPIO_BASE_REG + 0x10
579 #define QCA_GPIO_INT_EN_REG QCA_GPIO_BASE_REG + 0x14
580 #define QCA_GPIO_INT_TYPE_REG QCA_GPIO_BASE_REG + 0x18
581 #define QCA_GPIO_INT_POLARITY_REG QCA_GPIO_BASE_REG + 0x1C
582 #define QCA_GPIO_INT_PENDING_REG QCA_GPIO_BASE_REG + 0x20
583 #define QCA_GPIO_INT_MASK_REG QCA_GPIO_BASE_REG + 0x24
585 #if (SOC_TYPE & QCA_AR933X_SOC)
586 #define QCA_GPIO_FUNC_1_REG QCA_GPIO_BASE_REG + 0x28
587 #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x2C
588 #define QCA_GPIO_FUNC_2_REG QCA_GPIO_BASE_REG + 0x30
589 #define QCA_GPIO_WLAN_MUX_SET0_REG QCA_GPIO_BASE_REG + 0x34
590 #define QCA_GPIO_WLAN_MUX_SET1_REG QCA_GPIO_BASE_REG + 0x38
591 #define QCA_GPIO_WLAN_MUX_SET2_REG QCA_GPIO_BASE_REG + 0x3C
592 #define QCA_GPIO_WLAN_MUX_SET3_REG QCA_GPIO_BASE_REG + 0x40
594 #if (SOC_TYPE & QCA_QCA955X_SOC)
595 #define QCA_GPIO_SPARE_BITS_REG QCA_GPIO_BASE_REG + 0x28
597 #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x28
600 #define QCA_GPIO_OUT_FUNC0_REG QCA_GPIO_BASE_REG + 0x2C
601 #define QCA_GPIO_OUT_FUNC1_REG QCA_GPIO_BASE_REG + 0x30
602 #define QCA_GPIO_OUT_FUNC2_REG QCA_GPIO_BASE_REG + 0x34
603 #define QCA_GPIO_OUT_FUNC3_REG QCA_GPIO_BASE_REG + 0x38
604 #define QCA_GPIO_OUT_FUNC4_REG QCA_GPIO_BASE_REG + 0x3C
605 #define QCA_GPIO_OUT_FUNC5_REG QCA_GPIO_BASE_REG + 0x40
606 #define QCA_GPIO_IN_EN0_REG QCA_GPIO_BASE_REG + 0x44
607 #define QCA_GPIO_IN_EN1_REG QCA_GPIO_BASE_REG + 0x48
608 #define QCA_GPIO_IN_EN2_REG QCA_GPIO_BASE_REG + 0x4C
609 #define QCA_GPIO_IN_EN3_REG QCA_GPIO_BASE_REG + 0x50
610 #define QCA_GPIO_IN_EN4_REG QCA_GPIO_BASE_REG + 0x54
611 #define QCA_GPIO_IN_EN9_REG QCA_GPIO_BASE_REG + 0x68
612 #define QCA_GPIO_FUNC_REG QCA_GPIO_BASE_REG + 0x6C
616 * GPIO registers BIT fields
619 /* GPIO_FUNCTION_1/2 register (GPIO function) */
620 #if (SOC_TYPE & QCA_AR933X_SOC)
621 #define QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT 0
622 #define QCA_GPIO_FUNC_1_JTAG_DIS_MASK BIT(QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT)
623 #define QCA_GPIO_FUNC_1_UART_EN_SHIFT 1
624 #define QCA_GPIO_FUNC_1_UART_EN_MASK BIT(QCA_GPIO_FUNC_1_UART_EN_SHIFT)
625 #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT 2
626 #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_MASK BIT(QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT)
627 #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT 3
628 #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT)
629 #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT 4
630 #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT)
631 #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT 5
632 #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT)
633 #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT 6
634 #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT)
635 #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT 7
636 #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT)
637 #define QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT 13
638 #define QCA_GPIO_FUNC_1_SPI_CS_EN1_MASK BIT(QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT)
639 #define QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT 14
640 #define QCA_GPIO_FUNC_1_SPI_CS_EN2_MASK BIT(QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT)
641 #define QCA_GPIO_FUNC_1_SPI_EN_SHIFT 18
642 #define QCA_GPIO_FUNC_1_SPI_EN_MASK BIT(QCA_GPIO_FUNC_1_SPI_EN_SHIFT)
643 #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT 23
644 #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT)
645 #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT 24
646 #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT)
647 #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT 25
648 #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT)
649 #define QCA_GPIO_FUNC_1_I2S_EN_SHIFT 26
650 #define QCA_GPIO_FUNC_1_I2S_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_EN_SHIFT)
651 #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT 27
652 #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT)
653 #define QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT 29
654 #define QCA_GPIO_FUNC_1_I2S_22_18_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT)
655 #define QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT 30
656 #define QCA_GPIO_FUNC_1_SPDIF_EN_MASK BIT(QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT)
657 #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT 31
658 #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_MASK BIT(QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT)
660 #define QCA_GPIO_FUNC_2_MIC_DIS_SHIFT 0
661 #define QCA_GPIO_FUNC_2_MIC_DIS_MASK BIT(QCA_GPIO_FUNC_2_MIC_DIS_SHIFT)
662 #define QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT 1
663 #define QCA_GPIO_FUNC_2_I2S_ON_LED_MASK BIT(QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT)
664 #define QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT 2
665 #define QCA_GPIO_FUNC_2_SPDIF_ON23_MASK BIT(QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT)
666 #define QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT 3
667 #define QCA_GPIO_FUNC_2_I2SCK_ON1_MASK BIT(QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT)
668 #define QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT 4
669 #define QCA_GPIO_FUNC_2_I2SWS_ON0_MASK BIT(QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT)
670 #define QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT 5
671 #define QCA_GPIO_FUNC_2_I2SSD_ON12_MASK BIT(QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT)
672 #define QCA_GPIO_FUNC_2_WPS_DIS_SHIFT 8
673 #define QCA_GPIO_FUNC_2_WPS_DIS_MASK BIT(QCA_GPIO_FUNC_2_WPS_DIS_SHIFT)
674 #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT 9
675 #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_MASK BIT(QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT)
676 #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT 10
677 #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_MASK BIT(QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT)
678 #define QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT 11
679 #define QCA_GPIO_FUNC_2_USB_LED_ON1_MASK BIT(QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT)
680 #define QCA_GPIO_FUNC_2_LNA_ON28_SHIFT 12
681 #define QCA_GPIO_FUNC_2_LNA_ON28_MASK BIT(QCA_GPIO_FUNC_2_LNA_ON28_SHIFT)
682 #define QCA_GPIO_FUNC_2_SLIC_EN_SHIFT 13
683 #define QCA_GPIO_FUNC_2_SLIC_EN_MASK BIT(QCA_GPIO_FUNC_2_SLIC_EN_SHIFT)
684 #define QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT 14
685 #define QCA_GPIO_FUNC_2_SLIC_ON18_22_MASK BIT(QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT)
686 #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT 15
687 #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_MASK BIT(QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT)
688 #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT 16
689 #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_MASK BITS(QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT, 3)
695 #define QCA_GPIO_OUT_FUNCX_GPIOX_EN_SHIFT(_gpio) ((_gpio % 4) * 8)
696 #define QCA_GPIO_OUT_FUNCX_GPIOX_EN_MASK(_gpio) BIT(((_gpio % 4) * 8), 8)
698 #define QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT 0
699 #define QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT 0
700 #define QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT 0
701 #define QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT 0
702 #define QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT 0
703 #define QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT 0
704 #define QCA_GPIO_OUT_FUNCX_GPIO0_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT, 8)
705 #define QCA_GPIO_OUT_FUNCX_GPIO4_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT, 8)
706 #define QCA_GPIO_OUT_FUNCX_GPIO8_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT, 8)
707 #define QCA_GPIO_OUT_FUNCX_GPIO12_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT, 8)
708 #define QCA_GPIO_OUT_FUNCX_GPIO16_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT, 8)
709 #define QCA_GPIO_OUT_FUNCX_GPIO20_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT, 8)
711 #define QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT 8
712 #define QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT 8
713 #define QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT 8
714 #define QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT 8
715 #define QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT 8
716 #define QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT 8
717 #define QCA_GPIO_OUT_FUNCX_GPIO1_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT, 8)
718 #define QCA_GPIO_OUT_FUNCX_GPIO5_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT, 8)
719 #define QCA_GPIO_OUT_FUNCX_GPIO9_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT, 8)
720 #define QCA_GPIO_OUT_FUNCX_GPIO13_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT, 8)
721 #define QCA_GPIO_OUT_FUNCX_GPIO17_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT, 8)
722 #define QCA_GPIO_OUT_FUNCX_GPIO21_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT, 8)
724 #define QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT 16
725 #define QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT 16
726 #define QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT 16
727 #define QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT 16
728 #define QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT 16
729 #define QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT 16
730 #define QCA_GPIO_OUT_FUNCX_GPIO2_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT, 8)
731 #define QCA_GPIO_OUT_FUNCX_GPIO6_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT, 8)
732 #define QCA_GPIO_OUT_FUNCX_GPIO10_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT, 8)
733 #define QCA_GPIO_OUT_FUNCX_GPIO14_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT, 8)
734 #define QCA_GPIO_OUT_FUNCX_GPIO18_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT, 8)
735 #define QCA_GPIO_OUT_FUNCX_GPIO22_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT, 8)
737 #define QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT 24
738 #define QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT 24
739 #define QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT 24
740 #define QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT 24
741 #define QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT 24
742 #define QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT 24
743 #define QCA_GPIO_OUT_FUNCX_GPIO3_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT, 8)
744 #define QCA_GPIO_OUT_FUNCX_GPIO7_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT, 8)
745 #define QCA_GPIO_OUT_FUNCX_GPIO11_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT, 8)
746 #define QCA_GPIO_OUT_FUNCX_GPIO15_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT, 8)
747 #define QCA_GPIO_OUT_FUNCX_GPIO19_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT, 8)
748 #define QCA_GPIO_OUT_FUNCX_GPIO23_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT, 8)
750 /* GPIO output select values (for MUX) */
751 #define QCA_GPIO_OUT_MUX_GPIO_VAL 0
752 #define QCA_GPIO_OUT_MUX_MII_EXT_MDI_VAL 1
753 #define QCA_GPIO_OUT_MUX_SYS_RST_L_VAL 1
754 #define QCA_GPIO_OUT_MUX_NAND_CS0_VAL 1
755 #define QCA_GPIO_OUT_MUX_BOOT_RXT_MDI_VAL 2
756 #define QCA_GPIO_OUT_MUX_SPI_CS0_VAL 9
758 /* 5-port ethernet switch activity LEDs */
759 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN1_VAL 26
760 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN2_VAL 27
761 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN3_VAL 28
762 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN4_VAL 29
763 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN5_VAL 30
765 /* 5-port ethernet switch collision detect LEDs */
766 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN1_VAL 31
767 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN2_VAL 32
768 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN3_VAL 33
769 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN4_VAL 34
770 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN5_VAL 35
772 /* 5-port ethernet switch full/half duplex LEDs */
773 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN1_VAL 36
774 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN2_VAL 37
775 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN3_VAL 38
776 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN4_VAL 39
777 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN5_VAL 40
779 /* 5-port ethernet switch link indicator LEDs */
780 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK1_VAL 41
781 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK2_VAL 42
782 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK3_VAL 43
783 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK4_VAL 44
784 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK5_VAL 45
786 #if (SOC_TYPE & QCA_AR934X_SOC)
787 #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL 4
788 #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL 5
789 #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL 6
790 #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL 7
791 #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL 8
792 #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL 10
793 #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL 11
794 #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL 12
795 #define QCA_GPIO_OUT_MUX_I2S_WS_VAL 13
796 #define QCA_GPIO_OUT_MUX_I2S_SD_VAL 14
797 #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL 15
798 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 16
799 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 17
800 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 18
801 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 19
802 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 20
803 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 21
804 #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL 22
805 #define QCA_GPIO_OUT_MUX_CLK_OBS7_VAL 23
806 #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL 24
807 #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL 25
808 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 46
809 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 47
810 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 48
811 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL 49
812 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 50
813 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 51
814 #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL 72
815 #define QCA_GPIO_OUT_MUX_BT_ANT_VAL 73
816 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 74
817 #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL 78
818 #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL_VAL 79
819 #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL_VAL 80
820 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 84
821 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 87
823 #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL 3
824 #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL 4
825 #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL 5
826 #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL 8
827 #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL 10
828 #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL 11
829 #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL 12
830 #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL 13
831 #define QCA_GPIO_OUT_MUX_I2S_WS_VAL 14
832 #define QCA_GPIO_OUT_MUX_I2S_SD_VAL 15
833 #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL 16
834 #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL 17
835 #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL 18
836 #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL 19
837 #define QCA_GPIO_OUT_MUX_HSUART_RXD_VAL 20 /* TODO: RXD is INPUT, mistake in QCA9558 datasheet? */
838 #define QCA_GPIO_OUT_MUX_HSUART_CTS_VAL 21 /* TODO: CTS is INPUT, mistake in QCA9558 datasheet? */
839 #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL 22
840 #define QCA_GPIO_OUT_MUX_SRIF_OUT_VAL 23
842 #if (SOC_TYPE & QCA_QCA955X_SOC)
843 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_VAL 24
844 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_VAL 25
845 #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_VAL 26
846 #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_VAL 27
847 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_INV_VAL 28
848 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_INV_VAL 29
849 #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_INV_VAL 30
850 #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_INV_VAL 31
851 #define QCA_GPIO_OUT_MUX_GE1_MII_MDO_VAL 32
852 #define QCA_GPIO_OUT_MUX_GE1_MII_MDC_VAL 33
853 #define QCA_GPIO_OUT_MUX_SWCOM2_VAL 38
854 #define QCA_GPIO_OUT_MUX_SWCOM3_VAL 39
855 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL 40
856 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL 41
857 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 42
858 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 43
859 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 44
860 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL 45
861 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 46
862 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 47
863 #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL 68
864 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 70
865 #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_STROBE_VAL 71
866 #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_DATA_VAL 72
867 #define QCA_GPIO_OUT_MUX_NAND_CS1_VAL 73
868 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 74
869 #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL 75
870 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 76
871 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_EP_VAL 77
872 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL 78
873 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 79
874 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 80
875 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 81
876 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 82
877 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 83
878 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 84
881 #if (SOC_TYPE & QCA_QCA953X_SOC)
882 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL 48
883 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL 49
884 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 50
885 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 51
886 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 52
887 #define QCA_GPIO_OUT_MUX_RX_CLEAR_INT_VAL 53
888 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 54
889 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 55
890 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 78
891 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 86
892 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 88
893 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL 89
894 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 90
895 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 91
896 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 92
897 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 93
898 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 94
899 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 95
900 #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL 96
904 /* GPIO_IN_ENABLE0 register (GPIO in signals 0) */
905 #define QCA_GPIO_IN_EN0_SPI_MISO_SHIFT 0
906 #define QCA_GPIO_IN_EN0_SPI_MISO_MASK BITS(QCA_GPIO_IN_EN0_SPI_MISO_SHIFT, 8)
907 #define QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT 8
908 #define QCA_GPIO_IN_EN0_LSUART_RXD_MASK BITS(QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT ,8)
910 /* GPIO_IN_ENABLE1 register (GPIO in signals 1) */
911 #define QCA_GPIO_IN_EN1_I2S_WS_SHIFT 0
912 #define QCA_GPIO_IN_EN1_I2S_WS_MASK BITS(QCA_GPIO_IN_EN1_I2S_WS_SHIFT ,8)
913 #define QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT 8
914 #define QCA_GPIO_IN_EN1_I2S_MIC_SD_MASK BITS(QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT ,8)
915 #define QCA_GPIO_IN_EN1_I2S_CLK_SHIFT 16
916 #define QCA_GPIO_IN_EN1_I2S_CLK_MASK BITS(QCA_GPIO_IN_EN1_I2S_CLK_SHIFT ,8)
917 #define QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT 24
918 #define QCA_GPIO_IN_EN1_I2S_MCLK_MASK BITS(QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT ,8)
920 /* GPIO_IN_ENABLE9 register (GPIO in signals 9) */
921 #define QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT 16
922 #define QCA_GPIO_IN_EN9_HSUART_RXD_MASK BITS(QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT ,8)
923 #define QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT 24
924 #define QCA_GPIO_IN_EN9_HSUART_CTS_MASK BITS(QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT ,8)
926 /* GPIO_FUNCTION register (GPIO function) */
927 #define QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT 0
928 #define QCA_GPIO_FUNC_GPIO_SRIF_EN_MASK BIT(QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT)
929 #define QCA_GPIO_FUNC_JTAG_DIS_SHIFT 1
930 #define QCA_GPIO_FUNC_JTAG_DIS_MASK BIT(QCA_GPIO_FUNC_JTAG_DIS_SHIFT)
931 #define QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT 2
932 #define QCA_GPIO_FUNC_CLK_OBS0_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT)
933 #define QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT 3
934 #define QCA_GPIO_FUNC_CLK_OBS1_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT)
935 #define QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT 4
936 #define QCA_GPIO_FUNC_CLK_OBS2_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT)
937 #define QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT 5
938 #define QCA_GPIO_FUNC_CLK_OBS3_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT)
939 #define QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT 6
940 #define QCA_GPIO_FUNC_CLK_OBS4_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT)
941 #define QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT 7
942 #define QCA_GPIO_FUNC_CLK_OBS5_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT)
943 #define QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT 8
944 #define QCA_GPIO_FUNC_CLK_OBS6_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT)
945 #define QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT 9
946 #define QCA_GPIO_FUNC_CLK_OBS7_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT)
949 * PLL control registers
951 #define QCA_PLL_CPU_PLL_CFG_REG QCA_PLL_BASE_REG + 0x00
953 #if (SOC_TYPE & QCA_AR933X_SOC)
954 #define QCA_PLL_CPU_PLL_CFG2_REG QCA_PLL_BASE_REG + 0x04
955 #define QCA_PLL_CPU_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08
956 #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG QCA_PLL_BASE_REG + 0x10
957 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x14
958 #define QCA_PLL_ETHSW_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24
959 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C
960 #define QCA_PLL_USB_SUSPEND_REG QCA_PLL_BASE_REG + 0x40
961 #define QCA_PLL_WLAN_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x44
963 #if (SOC_TYPE & QCA_QCA956X_SOC)
964 #define QCA_PLL_CPU_PLL_CFG1_REG QCA_PLL_BASE_REG + 0x04
965 #define QCA_PLL_DDR_PLL_CFG_REG QCA_PLL_BASE_REG + 0x08
966 #define QCA_PLL_DDR_PLL_CFG1_REG QCA_PLL_BASE_REG + 0x0C
967 #define QCA_PLL_CPU_DDR_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x10
968 #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x14
969 #define QCA_PLL_PCIE_PLL_DITHER_MAX_REG QCA_PLL_BASE_REG + 0x18
970 #define QCA_PLL_PCIE_PLL_DITHER_MIN_REG QCA_PLL_BASE_REG + 0x1C
971 #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x20
972 #define QCA_PLL_LDO_PWR_CTRL_REG QCA_PLL_BASE_REG + 0x24
973 #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x28
974 #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x2C
975 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x30
976 #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x34
977 #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x38
978 #define QCA_PLL_DDR_PLL_DITHER2_REG QCA_PLL_BASE_REG + 0x3C
979 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x40
980 #define QCA_PLL_CPU_PLL_DITHER2_REG QCA_PLL_BASE_REG + 0x44
981 #define QCA_PLL_ETH_SGMII_CTRL_REG QCA_PLL_BASE_REG + 0x48
982 #define QCA_PLL_ETH_SGMII_SERDES_REG QCA_PLL_BASE_REG + 0x4C
984 #define QCA_PLL_DDR_PLL_CFG_REG QCA_PLL_BASE_REG + 0x04
985 #define QCA_PLL_CPU_DDR_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08
987 #if (SOC_TYPE & QCA_QCA955X_SOC)
988 #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x0C
989 #define QCA_PLL_PCIE_PLL_DITHER_MAX_REG QCA_PLL_BASE_REG + 0x10
990 #define QCA_PLL_PCIE_PLL_DITHER_MIN_REG QCA_PLL_BASE_REG + 0x14
991 #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x18
992 #define QCA_PLL_LDO_PWR_CTRL_REG QCA_PLL_BASE_REG + 0x1C
993 #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x20
994 #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x24
995 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x28
996 #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x2C
997 #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x30
998 #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x34
999 #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x38
1000 #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x3C
1001 #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x40
1002 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44
1003 #define QCA_PLL_ETH_SGMII_CTRL_REG QCA_PLL_BASE_REG + 0x48
1004 #define QCA_PLL_ETH_SGMII_SERDES_REG QCA_PLL_BASE_REG + 0x4C
1005 #define QCA_PLL_SLIC_PWM_DIV_REG QCA_PLL_BASE_REG + 0x50
1007 #define QCA_PLL_CPU_SYNC_REG QCA_PLL_BASE_REG + 0x0C
1008 #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x10
1009 #define QCA_PLL_PCIE_PLL_DITHER_MAX_REG QCA_PLL_BASE_REG + 0x14
1010 #define QCA_PLL_PCIE_PLL_DITHER_MIN_REG QCA_PLL_BASE_REG + 0x18
1011 #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x1C
1012 #define QCA_PLL_LDO_PWR_CTRL_REG QCA_PLL_BASE_REG + 0x20
1013 #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24
1014 #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28
1015 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C
1017 #if (SOC_TYPE & QCA_AR934X_SOC)
1018 #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x30
1019 #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x34
1020 #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x38
1021 #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x3C
1024 #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x40
1025 #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44
1026 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x48
1032 * PLL control registers BIT fields
1035 /* CPU_PLL_CONFIG register (CPU phase lock loop configuration) */
1036 #if (SOC_TYPE & QCA_AR933X_SOC)
1037 #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0
1038 #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 10)
1039 #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 10
1040 #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
1041 #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 16
1042 #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
1043 #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 21
1044 #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK BIT(QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)
1045 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 23
1046 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
1048 #if (SOC_TYPE & QCA_AR934X_SOC) |\
1049 (SOC_TYPE & QCA_QCA953X_SOC) |\
1050 (SOC_TYPE & QCA_QCA955X_SOC)
1051 #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0
1052 #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 6)
1053 #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 6
1054 #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
1057 #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 12
1058 #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
1059 #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 17
1060 #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK BITS(QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT, 2)
1061 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 19
1062 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
1065 #define QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT 30
1066 #define QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK BIT(QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT)
1067 #define QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT 31
1068 #define QCA_PLL_CPU_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT)
1070 /* CPU_PLL_CONFIG1 register (QCA956x only) */
1071 #define QCA_PLL_CPU_PLL_CFG1_NFRAC_L_SHIFT 0
1072 #define QCA_PLL_CPU_PLL_CFG1_NFRAC_L_MASK BITS(QCA_PLL_CPU_PLL_CFG1_NFRAC_L_SHIFT, 5)
1073 #define QCA_PLL_CPU_PLL_CFG1_NFRAC_H_SHIFT 5
1074 #define QCA_PLL_CPU_PLL_CFG1_NFRAC_H_MASK BITS(QCA_PLL_CPU_PLL_CFG1_NFRAC_H_SHIFT, 13)
1075 #define QCA_PLL_CPU_PLL_CFG1_NINT_SHIFT 18
1076 #define QCA_PLL_CPU_PLL_CFG1_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG1_NINT_SHIFT, 9)
1078 /* CPU_PLL_CONFIG2 register (CPU phase lock loop configuration, AR933x only) */
1079 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT 0
1080 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_MASK BITS(QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT, 12)
1082 /* CPU_CLOCK_CONTROL register (CPU clock control, AR933x only) */
1083 #define QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT 2
1084 #define QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK BIT(QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT)
1085 #define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT 5
1086 #define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT, 2)
1087 #define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT 10
1088 #define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT, 2)
1089 #define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT 15
1090 #define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT, 2)
1092 /* ETHSW_CLOCK_CONTROL register (Ethernet switch clock control, AR933x only) */
1093 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT 3
1094 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_MASK BIT(QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT)
1095 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT 4
1096 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_MASK BIT(QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT)
1098 /* ETH_XMII_CONTROL register (Ethernet XMII control) */
1099 #define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT 0
1100 #define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT, 8)
1101 #define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT 8
1102 #define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT, 8)
1103 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT 16
1104 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT, 8)
1105 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT 24
1106 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_MASK BIT(QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT)
1107 #define QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT 25
1108 #define QCA_PLL_ETH_XMII_CTRL_GIGE_MASK BIT(QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT)
1109 #define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT 26
1110 #define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT, 2)
1111 #define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT 28
1112 #define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT, 2)
1113 #define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT 30
1114 #define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_MASK BIT(QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT)
1115 #define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT 31
1116 #define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_MASK BIT(QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT)
1118 /* SUSPEND register (USB suspend, AR933x only) */
1119 #define QCA_PLL_USB_SUSPEND_EN_SHIFT 0
1120 #define QCA_PLL_USB_SUSPEND_EN_MASK BIT(QCA_PLL_USB_SUSPEND_EN_SHIFT)
1121 #define QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT 8
1122 #define QCA_PLL_USB_SUSPEND_RESTART_TIME_MASK BITS(QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT, 20)
1124 /* WLAN_CLOCK_CONTROL register (WLAN clock control, AR933x only) */
1125 #define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT 0
1126 #define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT)
1127 #define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT 1
1128 #define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT)
1129 #define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT 2
1130 #define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT)
1131 #define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT 3
1132 #define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT)
1133 #define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT 4
1134 #define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT)
1135 #define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT 8
1136 #define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT)
1137 #define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT 9
1138 #define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT)
1139 #define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT 10
1140 #define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT)
1141 #define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT 12
1142 #define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT)
1144 /* DDR_PLL_CONFIG register (DDR PLL configuration) */
1145 #if (SOC_TYPE & QCA_AR934X_SOC) |\
1146 (SOC_TYPE & QCA_QCA953X_SOC) |\
1147 (SOC_TYPE & QCA_QCA955X_SOC)
1148 #define QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT 0
1149 #define QCA_PLL_DDR_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT, 10)
1150 #define QCA_PLL_DDR_PLL_CFG_NINT_SHIFT 10
1151 #define QCA_PLL_DDR_PLL_CFG_NINT_MASK BITS(QCA_PLL_DDR_PLL_CFG_NINT_SHIFT, 6)
1154 #define QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT 16
1155 #define QCA_PLL_DDR_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT, 5)
1156 #define QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT 21
1157 #define QCA_PLL_DDR_PLL_CFG_RANGE_MASK BITS(QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT, 2)
1158 #define QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT 23
1159 #define QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT, 3)
1160 #define QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT 30
1161 #define QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK BIT(QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT)
1162 #define QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT 31
1163 #define QCA_PLL_DDR_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT)
1165 /* DDR_PLL_CONFIG1 register (QCA956x only) */
1166 #define QCA_PLL_DDR_PLL_CFG1_NFRAC_L_SHIFT 0
1167 #define QCA_PLL_DDR_PLL_CFG1_NFRAC_L_MASK BITS(QCA_PLL_DDR_PLL_CFG1_NFRAC_L_SHIFT, 5)
1168 #define QCA_PLL_DDR_PLL_CFG1_NFRAC_H_SHIFT 5
1169 #define QCA_PLL_DDR_PLL_CFG1_NFRAC_H_MASK BITS(QCA_PLL_DDR_PLL_CFG1_NFRAC_H_SHIFT, 13)
1170 #define QCA_PLL_DDR_PLL_CFG1_NINT_SHIFT 18
1171 #define QCA_PLL_DDR_PLL_CFG1_NINT_MASK BITS(QCA_PLL_DDR_PLL_CFG1_NINT_SHIFT, 9)
1173 /* CPU_DDR_CLOCK_CONTROL register (CPU DDR clock control) */
1174 #define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT 1
1175 #define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT)
1176 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT 2
1177 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT)
1178 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT 3
1179 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT)
1180 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT 4
1181 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT)
1182 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
1183 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT, 5)
1184 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
1185 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT, 5)
1186 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
1187 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT, 5)
1189 #if (SOC_TYPE & QCA_QCA955X_SOC) |\
1190 (SOC_TYPE & QCA_QCA956X_SOC)
1191 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_DDRPLL_SHIFT 20
1192 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_DDRPLL_SHIFT)
1193 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_CPUPLL_SHIFT 21
1194 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_CPUPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_CPUPLL_SHIFT)
1196 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT 20
1197 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT)
1198 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT 21
1199 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT)
1202 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT 22
1203 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT)
1204 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT 23
1205 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT)
1206 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT 24
1207 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT)
1209 /* PCIE_PLL_CONFIG register (PCIE RC phase lock loop configuration) */
1210 #define QCA_PLL_PCIE_PLL_CFG_REFDIV_SHIFT 10
1211 #define QCA_PLL_PCIE_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_PCIE_PLL_CFG_REFDIV_SHIFT, 5)
1212 #define QCA_PLL_PCIE_PLL_CFG_BYPASS_SHIFT 16
1213 #define QCA_PLL_PCIE_PLL_CFG_BYPASS_MASK BIT(QCA_PLL_PCIE_PLL_CFG_BYPASS_SHIFT)
1214 #define QCA_PLL_PCIE_PLL_CFG_PLLPWD_SHIFT 30
1215 #define QCA_PLL_PCIE_PLL_CFG_PLLPWD_MASK BIT(QCA_PLL_PCIE_PLL_CFG_PLLPWD_SHIFT)
1216 #define QCA_PLL_PCIE_PLL_CFG_UPDATING_SHIFT 31
1217 #define QCA_PLL_PCIE_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_PCIE_PLL_CFG_UPDATING_SHIFT)
1219 /* PCIE_PLL_DITHER_DIV_MAX (PCIE PLL dither parameter) */
1220 #define QCA_PLL_PCIE_PLL_DITHER_MAX_NFRAC_MAX_SHIFT 1
1221 #define QCA_PLL_PCIE_PLL_DITHER_MAX_NFRAC_MAX_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_MAX_NFRAC_MAX_SHIFT, 14)
1222 #define QCA_PLL_PCIE_PLL_DITHER_MAX_NINT_MAX_SHIFT 15
1223 #define QCA_PLL_PCIE_PLL_DITHER_MAX_NINT_MAX_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_MAX_NINT_MAX_SHIFT, 6)
1224 #define QCA_PLL_PCIE_PLL_DITHER_MAX_USE_MAX_SHIFT 30
1225 #define QCA_PLL_PCIE_PLL_DITHER_MAX_USE_MAX_MASK BIT(QCA_PLL_PCIE_PLL_DITHER_MAX_USE_MAX_SHIFT)
1226 #define QCA_PLL_PCIE_PLL_DITHER_MAX_DITHER_EN_SHIFT 31
1227 #define QCA_PLL_PCIE_PLL_DITHER_MAX_DITHER_EN_MASK BIT(QCA_PLL_PCIE_PLL_DITHER_MAX_DITHER_EN_SHIFT)
1229 /* PCIE_PLL_DITHER_DIV_MIN (PCIE PLL dither parameter) */
1230 #define QCA_PLL_PCIE_PLL_DITHER_MIN_NFRAC_MIN_SHIFT 1
1231 #define QCA_PLL_PCIE_PLL_DITHER_MIN_NFRAC_MIN_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_MIN_NFRAC_MIN_SHIFT, 14)
1232 #define QCA_PLL_PCIE_PLL_DITHER_MIN_NINT_MIN_SHIFT 15
1233 #define QCA_PLL_PCIE_PLL_DITHER_MIN_NINT_MIN_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_MIN_NINT_MIN_SHIFT, 6)
1235 /* PCIE_PLL_DITHER_STEP (PCIE PLL dither parameter) */
1236 #define QCA_PLL_PCIE_PLL_DITHER_STEP_NFRAC_STEP_SHIFT 1
1237 #define QCA_PLL_PCIE_PLL_DITHER_STEP_NFRAC_STEP_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_STEP_NFRAC_STEP_SHIFT, 14)
1238 #define QCA_PLL_PCIE_PLL_DITHER_STEP_NINT_STEP_SHIFT 15
1239 #define QCA_PLL_PCIE_PLL_DITHER_STEP_NINT_STEP_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_STEP_NINT_STEP_SHIFT, 10)
1240 #define QCA_PLL_PCIE_PLL_DITHER_STEP_UPDATE_CNT_SHIFT 28
1241 #define QCA_PLL_PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_STEP_UPDATE_CNT_SHIFT, 4)
1243 /* SWITCH_CLOCK_CONTROL */
1244 #if (SOC_TYPE & QCA_AR934X_SOC) |\
1245 (SOC_TYPE & QCA_QCA953X_SOC)
1246 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT 0
1247 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT)
1248 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT 1
1249 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT)
1250 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT 2
1251 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT)
1252 #define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT 3
1253 #define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT)
1254 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT 4
1255 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT)
1256 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT 5
1257 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT)
1258 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT 6
1259 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT)
1261 #define QCA_PLL_SWITCH_CLK_CTRL_I2C_CLK_SEL_SHIFT 5
1262 #define QCA_PLL_SWITCH_CLK_CTRL_I2C_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_I2C_CLK_SEL_SHIFT)
1263 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT 6
1264 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT)
1266 #if (SOC_TYPE & QCA_QCA955X_SOC)
1267 #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT 12
1268 #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT)
1269 #elif (SOC_TYPE & QCA_QCA956X_SOC)
1270 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT 12
1271 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT)
1272 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT 19
1273 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT)
1274 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT 16
1275 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT)
1276 #define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT 17
1277 #define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT)
1278 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT 18
1279 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT)
1282 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT 13
1283 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT)
1284 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT 14
1285 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT)
1286 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT 15
1287 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT)
1290 #define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT 7
1291 #define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT)
1292 #define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT 8
1293 #define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_MASK BITS(QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT, 4)
1294 #define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_25M_VAL 0x2
1295 #define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_40M_VAL 0x5
1297 /* DDR_PLL_DITHER register (DDR PLL dither parameter) */
1298 #if (SOC_TYPE & QCA_QCA956X_SOC)
1299 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_L_SHIFT 0
1300 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_L_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_L_SHIFT, 5)
1301 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_H_SHIFT 5
1302 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_H_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_H_SHIFT, 13)
1304 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT 0
1305 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT, 10)
1306 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT 10
1307 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 10)
1310 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_SHIFT 20
1311 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 7)
1312 #define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT 27
1313 #define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT, 4)
1314 #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT 31
1315 #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT)
1317 /* DDR_PLL_DITHER2 register (QCA956x only) */
1318 #define QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_L_SHIFT 0
1319 #define QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_L_MASK BITS(QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_L_SHIFT, 5)
1320 #define QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_H_SHIFT 5
1321 #define QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_H_MASK BITS(QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_H_SHIFT, 13)
1323 #if (SOC_TYPE & QCA_AR933X_SOC)
1324 /* PLL_DITHER_FRAC register (CPU PLL dither FRAC) */
1325 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT 0
1326 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT, 10)
1327 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT 10
1328 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT, 10)
1329 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT 20
1330 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT, 10)
1332 /* PLL_DITHER register (CPU PLL dither) */
1333 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 0
1334 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 14)
1336 /* CPU_PLL_DITHER register (CPU PLL dither parameter) */
1337 #if (SOC_TYPE & QCA_QCA956X_SOC)
1338 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_L_SHIFT 0
1339 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_L_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_L_SHIFT, 5)
1340 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_H_SHIFT 5
1341 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_H_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_H_SHIFT, 13)
1342 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 18
1343 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
1344 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 24
1345 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6)
1347 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT 0
1348 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 6)
1349 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT 6
1350 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
1351 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 12
1352 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
1353 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 18
1354 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6)
1358 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31
1359 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT)
1361 /* CPU_PLL_DITHER2 register (QCA956x only) */
1362 #define QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_L_SHIFT 0
1363 #define QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_L_MASK BITS(QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_L_SHIFT, 5)
1364 #define QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_H_SHIFT 5
1365 #define QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_H_MASK BITS(QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_H_SHIFT, 13)
1368 * PLL SRIF registers (not available in AR933x)
1370 #define QCA_PLL_SRIF_BB_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0x180
1371 #define QCA_PLL_SRIF_AUD_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0x200
1373 #if (SOC_TYPE & QCA_QCA955X_SOC) |\
1374 (SOC_TYPE & QCA_QCA956X_SOC)
1375 #define QCA_PLL_SRIF_CPU_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0xF00
1376 #define QCA_PLL_SRIF_DDR_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0xEC0
1377 #define QCA_PLL_SRIF_PCIE_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0xC80
1379 #define QCA_PLL_SRIF_CPU_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0x1C0
1380 #define QCA_PLL_SRIF_DDR_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0x240
1381 #define QCA_PLL_SRIF_PCIE_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0xC00
1384 #define QCA_PLL_SRIF_BB_DPLL1_REG QCA_PLL_SRIF_BB_DPLL_BASE_REG + 0x0
1385 #define QCA_PLL_SRIF_BB_DPLL2_REG QCA_PLL_SRIF_BB_DPLL_BASE_REG + 0x4
1386 #define QCA_PLL_SRIF_BB_DPLL3_REG QCA_PLL_SRIF_BB_DPLL_BASE_REG + 0x8
1387 #define QCA_PLL_SRIF_BB_DPLL4_REG QCA_PLL_SRIF_BB_DPLL_BASE_REG + 0xC
1389 #define QCA_PLL_SRIF_CPU_DPLL1_REG QCA_PLL_SRIF_CPU_DPLL_BASE_REG + 0x0
1390 #define QCA_PLL_SRIF_CPU_DPLL2_REG QCA_PLL_SRIF_CPU_DPLL_BASE_REG + 0x4
1391 #define QCA_PLL_SRIF_CPU_DPLL3_REG QCA_PLL_SRIF_CPU_DPLL_BASE_REG + 0x8
1392 #define QCA_PLL_SRIF_CPU_DPLL4_REG QCA_PLL_SRIF_CPU_DPLL_BASE_REG + 0xC
1394 #define QCA_PLL_SRIF_AUD_DPLL1_REG QCA_PLL_SRIF_AUD_DPLL_BASE_REG + 0x0
1395 #define QCA_PLL_SRIF_AUD_DPLL2_REG QCA_PLL_SRIF_AUD_DPLL_BASE_REG + 0x4
1396 #define QCA_PLL_SRIF_AUD_DPLL3_REG QCA_PLL_SRIF_AUD_DPLL_BASE_REG + 0x8
1397 #define QCA_PLL_SRIF_AUD_DPLL4_REG QCA_PLL_SRIF_AUD_DPLL_BASE_REG + 0xC
1399 #define QCA_PLL_SRIF_DDR_DPLL1_REG QCA_PLL_SRIF_DDR_DPLL_BASE_REG + 0x0
1400 #define QCA_PLL_SRIF_DDR_DPLL2_REG QCA_PLL_SRIF_DDR_DPLL_BASE_REG + 0x4
1401 #define QCA_PLL_SRIF_DDR_DPLL3_REG QCA_PLL_SRIF_DDR_DPLL_BASE_REG + 0x8
1402 #define QCA_PLL_SRIF_DDR_DPLL4_REG QCA_PLL_SRIF_DDR_DPLL_BASE_REG + 0xC
1404 #define QCA_PLL_SRIF_PCIE_DPLL1_REG QCA_PLL_SRIF_PCIE_DPLL_BASE_REG + 0x0
1405 #define QCA_PLL_SRIF_PCIE_DPLL2_REG QCA_PLL_SRIF_PCIE_DPLL_BASE_REG + 0x4
1406 #define QCA_PLL_SRIF_PCIE_DPLL3_REG QCA_PLL_SRIF_PCIE_DPLL_BASE_REG + 0x8
1407 #define QCA_PLL_SRIF_PCIE_DPLL4_REG QCA_PLL_SRIF_PCIE_DPLL_BASE_REG + 0xC
1410 * PLL SRIF registers BIT fields (not available in AR933x)
1413 /* DPLL1 (common for BB, CPU, AUD, DDR and PCIE) */
1414 #define QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT 0
1415 #define QCA_PLL_SRIF_DPLL1_NFRAC_MASK BITS(QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT, 18)
1416 #define QCA_PLL_SRIF_DPLL1_NINT_SHIFT 18
1417 #define QCA_PLL_SRIF_DPLL1_NINT_MASK BITS(QCA_PLL_SRIF_DPLL1_NINT_SHIFT, 9)
1418 #define QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT 27
1419 #define QCA_PLL_SRIF_DPLL1_REFDIV_MASK BITS(QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT, 5)
1421 /* DPLL2 (common for BB, CPU, AUD, DDR and PCIE) */
1422 #if (SOC_TYPE & QCA_QCA953X_SOC) |\
1423 (SOC_TYPE & QCA_QCA956X_SOC)
1424 #define QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT 0
1425 #define QCA_PLL_SRIF_DPLL2_RST_TEST_MASK BIT(QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT)
1426 #define QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT 1
1427 #define QCA_PLL_SRIF_DPLL2_SEL_CNT_MASK BIT(QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT)
1428 #define QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT 2
1429 #define QCA_PLL_SRIF_DPLL2_TEST_IN_MASK BITS(QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT, 10)
1430 #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT 12
1431 #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_MASK BITS(QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT, 7)
1432 #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 19
1433 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 3)
1434 #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 22
1435 #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK BIT(QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
1436 #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT 23
1437 #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_MASK BIT(QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT)
1438 #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT 24
1439 #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_MASK BIT(QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT)
1440 #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 25
1441 #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 4)
1442 #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 29
1443 #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 2)
1444 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 31
1445 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK BIT(QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
1447 #define QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT 0
1448 #define QCA_PLL_SRIF_DPLL2_TEST_IN_MASK BITS(QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT, 7)
1449 #define QCA_PLL_SRIF_DPLL2_DELTA_SHIFT 7
1450 #define QCA_PLL_SRIF_DPLL2_DELTA_MASK BITS(QCA_PLL_SRIF_DPLL2_DELTA_SHIFT, 6)
1451 #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 13
1452 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2)
1453 #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 16
1454 #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK BIT(QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
1455 #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT 17
1456 #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_MASK BIT(QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT)
1457 #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT 18
1458 #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_MASK BIT(QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT)
1459 #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 19
1460 #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7)
1461 #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 26
1462 #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KI_SHIFT, 4)
1463 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 30
1464 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK BIT(QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
1465 #define QCA_PLL_SRIF_DPLL2_RANGE_SHIFT 31
1466 #define QCA_PLL_SRIF_DPLL2_RANGE_MASK BIT(QCA_PLL_SRIF_DPLL2_RANGE_SHIFT)
1469 /* DPLL3 (common for BB, CPU, AUD, DDR and PCIE) */
1470 /* DPLL4 (common for BB, CPU, AUD, DDR and PCIE) */
1473 * TODO: check and confirm DPLL3/4 register structure
1477 * Reset control registers
1479 #define QCA_RST_GENERAL_TIMER1_REG QCA_RST_BASE_REG + 0x00
1480 #define QCA_RST_GENERAL_TIMER1_RELOAD_REG QCA_RST_BASE_REG + 0x04
1481 #define QCA_RST_WATCHDOG_TIMER_CTRL_REG QCA_RST_BASE_REG + 0x08
1482 #define QCA_RST_WATCHDOG_TIMER_REG QCA_RST_BASE_REG + 0x0C
1483 #define QCA_RST_MISC_INTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x10
1484 #define QCA_RST_MISC_INTERRUPT_MASK_REG QCA_RST_BASE_REG + 0x14
1485 #define QCA_RST_GLOBALINTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x18
1486 #define QCA_RST_RESET_REG QCA_RST_BASE_REG + 0x1C
1487 #define QCA_RST_REVISION_ID_REG QCA_RST_BASE_REG + 0x90
1488 #define QCA_RST_GENERAL_TIMER2_REG QCA_RST_BASE_REG + 0x94
1489 #define QCA_RST_GENERAL_TIMER2_RELOAD_REG QCA_RST_BASE_REG + 0x98
1490 #define QCA_RST_GENERAL_TIMER3_REG QCA_RST_BASE_REG + 0x9C
1491 #define QCA_RST_GENERAL_TIMER3_RELOAD_REG QCA_RST_BASE_REG + 0xA0
1492 #define QCA_RST_GENERAL_TIMER4_REG QCA_RST_BASE_REG + 0xA4
1493 #define QCA_RST_GENERAL_TIMER4_RELOAD_REG QCA_RST_BASE_REG + 0xA8
1495 #if (SOC_TYPE & QCA_AR933X_SOC)
1496 #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xAC
1498 #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xB0
1501 #if (SOC_TYPE & QCA_QCA956X_SOC)
1502 #define QCA_RST_MISC2_REG QCA_RST_BASE_REG + 0xB8
1503 #define QCA_RST_RESET2_REG QCA_RST_BASE_REG + 0xC0
1505 #define QCA_RST_MISC2_REG QCA_RST_BASE_REG + 0xBC
1506 #define QCA_RST_RESET2_REG QCA_RST_BASE_REG + 0xC4
1510 * Reset control registers BIT fields
1513 /* RST_WATCHDOG_TIMER_CTRL (Watchdog timer control) */
1514 #define QCA_RST_WATCHDOG_TIMER_CTRL_ACTION_SHIFT 0
1515 #define QCA_RST_WATCHDOG_TIMER_CTRL_ACTION_MASK BITS(QCA_RST_WATCHDOG_TIMER_CTRL_ACTION_SHIFT, 2)
1516 #define QCA_RST_WATCHDOG_TIMER_CTRL_LAST_SHIFT 31
1517 #define QCA_RST_WATCHDOG_TIMER_CTRL_LAST_MASK BIT(QCA_RST_WATCHDOG_TIMER_CTRL_LAST_SHIFT)
1519 /* RST_BOOTSTRAP (Reset bootstrap) */
1520 #if (SOC_TYPE & QCA_AR933X_SOC)
1521 #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 0
1522 #elif (SOC_TYPE & QCA_QCA956X_SOC)
1523 #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 2
1525 #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 4
1527 #define QCA_RST_BOOTSTRAP_REF_CLK_MASK BIT(QCA_RST_BOOTSTRAP_REF_CLK_SHIFT)
1528 #define QCA_RST_BOOTSTRAP_REF_CLK_25M_VAL 0x0
1529 #define QCA_RST_BOOTSTRAP_REF_CLK_40M_VAL 0x1
1531 #if (SOC_TYPE & QCA_AR933X_SOC)
1532 #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT 3
1533 #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK BIT(QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT)
1534 #define QCA_RST_BOOTSTRAP_EEPBUSY_SHIFT 4
1535 #define QCA_RST_BOOTSTRAP_EEPBUSY_MASK BIT(QCA_RST_BOOTSTRAP_EEPBUSY_SHIFT)
1536 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 12
1537 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
1538 #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT 16
1539 #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK BIT(QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT)
1540 #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT 17
1541 #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_MASK BIT(QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT)
1542 #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT 18
1543 #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_MASK BIT(QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT)
1545 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 0
1546 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1
1547 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 2
1549 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 0
1551 /* v2 does not support SDR, but we can read reserved bit and make it universal */
1552 #if (SOC_TYPE & QCA_QCA953X_SOC)
1553 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
1555 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BIT(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT)
1558 #define QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT 2
1559 #define QCA_RST_BOOTSTRAP_BOOT_SEL_MASK BIT(QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT)
1560 #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT 3
1561 #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_MASK BIT(QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT)
1562 #define QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT 5
1563 #define QCA_RST_BOOTSTRAP_JTAG_MODE_MASK BIT(QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT)
1564 #define QCA_RST_BOOTSTRAP_PCIE_RC_MODE_SHIFT 6
1565 #define QCA_RST_BOOTSTRAP_PCIE_RC_MODE_MASK BIT(QCA_RST_BOOTSTRAP_PCIE_RC_MODE_SHIFT)
1566 #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT 7
1567 #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK BIT(QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT)
1569 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 3
1570 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1
1571 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 0
1575 #if (SOC_TYPE & QCA_QCA956X_SOC)
1576 #define QCA_RST_RESET_ETH_SWITCH_RST_SHIFT 0
1577 #define QCA_RST_RESET_ETH_SWITCH_RST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_RST_SHIFT)
1578 #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 2
1579 #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
1581 #define QCA_RST_RESET_I2S_RST_SHIFT 0
1582 #define QCA_RST_RESET_I2S_RST_MASK BIT(QCA_RST_RESET_I2S_RST_SHIFT)
1583 #define QCA_RST_RESET_LUT_RST_SHIFT 2
1584 #define QCA_RST_RESET_LUT_RST_MASK BIT(QCA_RST_RESET_LUT_RST_SHIFT)
1587 #define QCA_RST_RESET_MBOX_RST_SHIFT 1
1588 #define QCA_RST_RESET_MBOX_RST_MASK BIT(QCA_RST_RESET_MBOX_RST_SHIFT)
1589 #define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT 3
1590 #define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_MASK BIT(QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT)
1591 #define QCA_RST_RESET_USB_PHY_RST_SHIFT 4
1592 #define QCA_RST_RESET_USB_PHY_RST_MASK BIT(QCA_RST_RESET_USB_PHY_RST_SHIFT)
1593 #define QCA_RST_RESET_USB_HOST_RST_SHIFT 5
1594 #define QCA_RST_RESET_USB_HOST_RST_MASK BIT(QCA_RST_RESET_USB_HOST_RST_SHIFT)
1596 #if (SOC_TYPE & QCA_AR933X_SOC)
1597 #define QCA_RST_RESET_SLIC_RST_SHIFT 6
1598 #define QCA_RST_RESET_SLIC_RST_MASK BIT(QCA_RST_RESET_SLIC_RST_SHIFT)
1600 #define QCA_RST_RESET_PCIE_RST_SHIFT 6
1601 #define QCA_RST_RESET_PCIE_RST_MASK BIT(QCA_RST_RESET_PCIE_RST_SHIFT)
1602 #define QCA_RST_RESET_SLIC_RST_SHIFT 30
1603 #define QCA_RST_RESET_SLIC_RST_MASK BIT(QCA_RST_RESET_SLIC_RST_SHIFT)
1606 #define QCA_RST_RESET_PCIE_PHY_RST_SHIFT 7
1607 #define QCA_RST_RESET_PCIE_PHY_RST_MASK BIT(QCA_RST_RESET_PCIE_PHY_RST_SHIFT)
1609 #if (SOC_TYPE & QCA_QCA955X_SOC) |\
1610 (SOC_TYPE & QCA_QCA956X_SOC)
1611 #define QCA_RST_RESET_ETH_SGMII_RST_SHIFT 8
1612 #define QCA_RST_RESET_ETH_SGMII_RST_MASK BIT(QCA_RST_RESET_ETH_SGMII_RST_SHIFT)
1614 #define QCA_RST_RESET_ETH_SWITCH_RST_SHIFT 8
1615 #define QCA_RST_RESET_ETH_SWITCH_RST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_RST_SHIFT)
1618 #define QCA_RST_RESET_GE0_MAC_RST_SHIFT 9
1619 #define QCA_RST_RESET_GE0_MAC_RST_MASK BIT(QCA_RST_RESET_GE0_MAC_RST_SHIFT)
1620 #define QCA_RST_RESET_HOST_DMA_INT_SHIFT 10
1621 #define QCA_RST_RESET_HOST_DMA_INT_MASK BIT(QCA_RST_RESET_HOST_DMA_INT_SHIFT)
1623 #if (SOC_TYPE & QCA_AR933X_SOC)
1624 #define QCA_RST_RESET_WLAN_RST_SHIFT 11
1625 #define QCA_RST_RESET_WLAN_RST_MASK BIT(QCA_RST_RESET_WLAN_RST_SHIFT)
1627 #define QCA_RST_RESET_USB_PHY_ARST_SHIFT 11
1628 #define QCA_RST_RESET_USB_PHY_ARST_MASK BIT(QCA_RST_RESET_USB_PHY_ARST_SHIFT)
1631 #if (SOC_TYPE & QCA_AR933X_SOC)
1632 #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 14
1633 #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
1635 #if (SOC_TYPE & QCA_QCA955X_SOC) |\
1636 (SOC_TYPE & QCA_QCA956X_SOC)
1637 #define QCA_RST_RESET_ETH_SGMII_ARST_SHIFT 12
1638 #define QCA_RST_RESET_ETH_SGMII_ARST_MASK BIT(QCA_RST_RESET_ETH_SGMII_ARST_SHIFT)
1640 #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 12
1641 #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
1644 #define QCA_RST_RESET_NAND_FLASH_RST_SHIFT 14
1645 #define QCA_RST_RESET_NAND_FLASH_RST_MASK BIT(QCA_RST_RESET_NAND_FLASH_RST_SHIFT)
1648 #define QCA_RST_RESET_GE1_MAC_RST_SHIFT 13
1649 #define QCA_RST_RESET_GE1_MAC_RST_MASK BIT(QCA_RST_RESET_GE1_MAC_RST_SHIFT)
1650 #define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT 15
1651 #define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_MASK BIT(QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT)
1652 #define QCA_RST_RESET_DDR_RST_SHIFT 16
1653 #define QCA_RST_RESET_DDR_RST_MASK BIT(QCA_RST_RESET_DDR_RST_SHIFT)
1654 #define QCA_RST_RESET_HSUART_RST_SHIFT 17
1655 #define QCA_RST_RESET_HSUART_RST_MASK BIT(QCA_RST_RESET_HSUART_RST_SHIFT)
1656 #define QCA_RST_RESET_PCIEEP_RST_SHIFT 18
1657 #define QCA_RST_RESET_PCIEEP_RST_MASK BIT(QCA_RST_RESET_PCIEEP_RST_SHIFT)
1658 #define QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT 19
1659 #define QCA_RST_RESET_HOST_DMA_RST_INT_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT)
1660 #define QCA_RST_RESET_CPU_COLD_RST_SHIFT 20
1661 #define QCA_RST_RESET_CPU_COLD_RST_MASK BIT(QCA_RST_RESET_CPU_COLD_RST_SHIFT)
1662 #define QCA_RST_RESET_CPU_NMI_SHIFT 21
1663 #define QCA_RST_RESET_CPU_NMI_MASK BIT(QCA_RST_RESET_CPU_NMI_SHIFT)
1664 #define QCA_RST_RESET_GE0_MDIO_RST_SHIFT 22
1665 #define QCA_RST_RESET_GE0_MDIO_RST_MASK BIT(QCA_RST_RESET_GE0_MDIO_RST_SHIFT)
1666 #define QCA_RST_RESET_GE1_MDIO_RST_SHIFT 23
1667 #define QCA_RST_RESET_GE1_MDIO_RST_MASK BIT(QCA_RST_RESET_GE1_MDIO_RST_SHIFT)
1668 #define QCA_RST_RESET_FULL_CHIP_RST_SHIFT 24
1669 #define QCA_RST_RESET_FULL_CHIP_RST_MASK BIT(QCA_RST_RESET_FULL_CHIP_RST_SHIFT)
1670 #define QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT 25
1671 #define QCA_RST_RESET_CHECKSUM_ACC_RST_MASK BIT(QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT)
1672 #define QCA_RST_RESET_PCIEEP_RST_INT_SHIFT 26
1673 #define QCA_RST_RESET_PCIEEP_RST_INT_MASK BIT(QCA_RST_RESET_PCIEEP_RST_INT_SHIFT)
1674 #define QCA_RST_RESET_RTC_RST_SHIFT 27
1675 #define QCA_RST_RESET_RTC_RST_MASK BIT(QCA_RST_RESET_RTC_RST_SHIFT)
1676 #define QCA_RST_RESET_EXT_RST_SHIFT 28
1677 #define QCA_RST_RESET_EXT_RST_MASK BIT(QCA_RST_RESET_EXT_RST_SHIFT)
1679 #if (SOC_TYPE & QCA_AR934X_SOC) |\
1680 (SOC_TYPE & QCA_QCA955X_SOC)
1681 #define QCA_RST_RESET_HOST_DMA_RST_SHIFT 29
1682 #define QCA_RST_RESET_HOST_DMA_RST_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_SHIFT)
1683 #elif (SOC_TYPE & QCA_QCA953X_SOC)
1684 #define QCA_RST_RESET_USB_EXT_PWR_SHIFT 29
1685 #define QCA_RST_RESET_USB_EXT_PWR_MASK BIT(QCA_RST_RESET_USB_EXT_PWR_SHIFT)
1688 #define QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT 31
1689 #define QCA_RST_RESET_HOST_DMA_RST_STATUS_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT)
1691 /* RST_RESET2 (QCA955x and QCA956x only) */
1692 #define QCA_RST_RESET2_USB2_MODE_DEV_SHIFT 0
1693 #define QCA_RST_RESET2_USB2_MODE_DEV_MASK BIT(QCA_RST_RESET2_USB2_MODE_DEV_SHIFT)
1694 #define QCA_RST_RESET2_USB2_PHY_SUSPEND_ORIDE_SHIFT 3
1695 #define QCA_RST_RESET2_USB2_PHY_SUSPEND_ORIDE_MASK BIT(QCA_RST_RESET2_USB2_PHY_SUSPEND_ORIDE_SHIFT)
1696 #define QCA_RST_RESET2_USB2_PHY_RST_SHIFT 4
1697 #define QCA_RST_RESET2_USB2_PHY_RST_MASK BIT(QCA_RST_RESET2_USB2_PHY_RST_SHIFT)
1698 #define QCA_RST_RESET2_USB2_HOST_RST_SHIFT 5
1699 #define QCA_RST_RESET2_USB2_HOST_RST_MASK BIT(QCA_RST_RESET2_USB2_HOST_RST_SHIFT)
1700 #define QCA_RST_RESET2_PCIE2_RST_SHIFT 6
1701 #define QCA_RST_RESET2_PCIE2_RST_MASK BIT(QCA_RST_RESET2_PCIE2_RST_SHIFT)
1702 #define QCA_RST_RESET2_PCIE2_PHY_RST_SHIFT 7
1703 #define QCA_RST_RESET2_PCIE2_PHY_RST_MASK BIT(QCA_RST_RESET2_PCIE2_PHY_RST_SHIFT)
1704 #define QCA_RST_RESET2_USB2_PHY_ARST_SHIFT 11
1705 #define QCA_RST_RESET2_USB2_PHY_ARST_MASK BIT(QCA_RST_RESET2_USB2_PHY_ARST_SHIFT)
1706 #define QCA_RST_RESET2_USB2_PHY_PLLPWD_EXT_SHIFT 15
1707 #define QCA_RST_RESET2_USB2_PHY_PLLPWD_EXT_MASK BIT(QCA_RST_RESET2_USB2_PHY_PLLPWD_EXT_SHIFT)
1708 #define QCA_RST_RESET2_USB_EXT_PWR_SHIFT 16
1709 #define QCA_RST_RESET2_USB_EXT_PWR_MASK BIT(QCA_RST_RESET2_USB_EXT_PWR_SHIFT)
1710 #define QCA_RST_RESET2_USB2_EXT_PWR_SHIFT 17
1711 #define QCA_RST_RESET2_USB2_EXT_PWR_MASK BIT(QCA_RST_RESET2_USB2_EXT_PWR_SHIFT)
1712 #define QCA_RST_RESET2_EP_MODE_SHIFT 18
1713 #define QCA_RST_RESET2_EP_MODE_MASK BIT(QCA_RST_RESET2_EP_MODE_SHIFT)
1715 /* RST_REVISION_ID (Chip revision ID) */
1716 #define QCA_RST_REVISION_ID_MAJOR_SHIFT 4
1717 #define QCA_RST_REVISION_ID_MAJOR_MASK BITS(QCA_RST_REVISION_ID_MAJOR_SHIFT, 12)
1719 #if (SOC_TYPE & QCA_AR933X_SOC)
1720 #define QCA_RST_REVISION_ID_REV_SHIFT 0
1721 #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 2)
1723 #define QCA_RST_REVISION_ID_REV_SHIFT 0
1724 #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 4)
1727 #define QCA_RST_REVISION_ID_MAJOR_AR9330_VAL 0x0110
1728 #define QCA_RST_REVISION_ID_MAJOR_AR9331_VAL 0x1110
1729 #define QCA_RST_REVISION_ID_MAJOR_AR9341_VAL 0x0120
1730 #define QCA_RST_REVISION_ID_MAJOR_AR9342_VAL 0x1120
1731 #define QCA_RST_REVISION_ID_MAJOR_AR9344_VAL 0x2120
1732 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL 0x0140
1733 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL 0x0160
1734 #define QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL 0x1130
1736 /* RST_MISC2 register (Miscellaneous CPU control bits) */
1737 #define QCA_RST_MISC2_PERSTN_RCPHY_SHIFT 13
1738 #define QCA_RST_MISC2_PERSTN_RCPHY_MASK BIT(QCA_RST_MISC2_PERSTN_RCPHY_SHIFT)
1739 #define QCA_RST_MISC2_PERSTN_RCPHY2_SHIFT 14
1740 #define QCA_RST_MISC2_PERSTN_RCPHY2_MASK BIT(QCA_RST_MISC2_PERSTN_RCPHY2_SHIFT)
1743 * PCIE RC control registers
1745 #define QCA_PCIE_RC0_CTRL_APP_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x00
1746 #define QCA_PCIE_RC1_CTRL_APP_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x00
1747 #define QCA_PCIE_RC0_CTRL_AER_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x04
1748 #define QCA_PCIE_RC1_CTRL_AER_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x04
1749 #define QCA_PCIE_RC0_CTRL_PWR_MGMT_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x08
1750 #define QCA_PCIE_RC1_CTRL_PWR_MGMT_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x08
1751 #define QCA_PCIE_RC0_CTRL_ELEC_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x0C
1752 #define QCA_PCIE_RC1_CTRL_ELEC_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x0C
1753 #define QCA_PCIE_RC0_CTRL_CFG_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x10
1754 #define QCA_PCIE_RC1_CTRL_CFG_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x10
1755 #define QCA_PCIE_RC0_CTRL_RX_CNTL_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x14
1756 #define QCA_PCIE_RC1_CTRL_RX_CNTL_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x14
1757 #define QCA_PCIE_RC0_CTRL_RST_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x18
1758 #define QCA_PCIE_RC1_CTRL_RST_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x18
1759 #define QCA_PCIE_RC0_CTRL_DBG_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x1C
1760 #define QCA_PCIE_RC1_CTRL_DBG_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x1C
1761 #define QCA_PCIE_RC0_CTRL_PHY_RW_DATA_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x24
1762 #define QCA_PCIE_RC1_CTRL_PHY_RW_DATA_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x24
1763 #define QCA_PCIE_RC0_CTRL_PHY_TRG_RD_LOAD_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x28
1764 #define QCA_PCIE_RC1_CTRL_PHY_TRG_RD_LOAD_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x28
1765 #define QCA_PCIE_RC0_CTRL_PHY_CFG_DATA_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x2C
1766 #define QCA_PCIE_RC1_CTRL_PHY_CFG_DATA_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x2C
1767 #define QCA_PCIE_RC0_CTRL_MAC_PHY_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x30
1768 #define QCA_PCIE_RC1_CTRL_MAC_PHY_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x30
1769 #define QCA_PCIE_RC0_CTRL_PHY_MAC_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x34
1770 #define QCA_PCIE_RC1_CTRL_PHY_MAC_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x34
1771 #define QCA_PCIE_RC0_CTRL_SIDEBAND1_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x38
1772 #define QCA_PCIE_RC1_CTRL_SIDEBAND1_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x38
1773 #define QCA_PCIE_RC0_CTRL_SIDEBAND2_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x3C
1774 #define QCA_PCIE_RC1_CTRL_SIDEBAND2_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x3C
1775 #define QCA_PCIE_RC0_CTRL_SPARE_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x40
1776 #define QCA_PCIE_RC1_CTRL_SPARE_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x40
1777 #define QCA_PCIE_RC0_CTRL_MSI_ADDR_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x44
1778 #define QCA_PCIE_RC1_CTRL_MSI_ADDR_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x44
1779 #define QCA_PCIE_RC0_CTRL_MSI_DATA_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x48
1780 #define QCA_PCIE_RC1_CTRL_MSI_DATA_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x48
1781 #define QCA_PCIE_RC0_CTRL_INT_STATUS_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x4C
1782 #define QCA_PCIE_RC1_CTRL_INT_STATUS_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x4C
1783 #define QCA_PCIE_RC0_CTRL_INT_MASK_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x50
1784 #define QCA_PCIE_RC1_CTRL_INT_MASK_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x50
1785 #define QCA_PCIE_RC0_CTRL_ERR_CNT_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x54
1786 #define QCA_PCIE_RC1_CTRL_ERR_CNT_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x54
1787 #define QCA_PCIE_RC0_CTRL_REQ_LAT_INT_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x58
1788 #define QCA_PCIE_RC1_CTRL_REQ_LAT_INT_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x58
1789 #define QCA_PCIE_RC0_CTRL_MISC_REG QCA_PCIE_RC0_CTRL_BASE_REG + 0x5C
1790 #define QCA_PCIE_RC1_CTRL_MISC_REG QCA_PCIE_RC1_CTRL_BASE_REG + 0x5C
1793 * PCIE RC control registers BIT fields
1796 /* PCIE_APP register (PCIE application control) */
1797 #define QCA_PCIE_RCX_CTRL_APP_LTSSM_EN_SHIFT 0
1798 #define QCA_PCIE_RCX_CTRL_APP_LTSSM_EN_MASK BIT(QCA_PCIE_RCX_CTRL_APP_LTSSM_EN_SHIFT)
1799 #define QCA_PCIE_RCX_CTRL_APP_UNLOCK_MSG_SHIFT 1
1800 #define QCA_PCIE_RCX_CTRL_APP_UNLOCK_MSG_MASK BIT(QCA_PCIE_RCX_CTRL_APP_UNLOCK_MSG_SHIFT)
1801 #define QCA_PCIE_RCX_CTRL_APP_PM_XMT_TURNOFF_SHIFT 2
1802 #define QCA_PCIE_RCX_CTRL_APP_PM_XMT_TURNOFF_MASK BIT(QCA_PCIE_RCX_CTRL_APP_PM_XMT_TURNOFF_SHIFT)
1803 #define QCA_PCIE_RCX_CTRL_APP_INIT_RST_SHIFT 3
1804 #define QCA_PCIE_RCX_CTRL_APP_INIT_RST_MASK BIT(QCA_PCIE_RCX_CTRL_APP_INIT_RST_SHIFT)
1805 #define QCA_PCIE_RCX_CTRL_APP_MASTER_RESP_ERR_MAP_SHIFT 4
1806 #define QCA_PCIE_RCX_CTRL_APP_MASTER_RESP_ERR_MAP_MASK BITS(QCA_PCIE_RCX_CTRL_APP_MASTER_RESP_ERR_MAP_SHIFT, 2)
1807 #define QCA_PCIE_RCX_CTRL_APP_SLAVE_RESP_ERR_MAP_SHIFT 6
1808 #define QCA_PCIE_RCX_CTRL_APP_SLAVE_RESP_ERR_MAP_MASK BITS(QCA_PCIE_RCX_CTRL_APP_SLAVE_RESP_ERR_MAP_SHIFT, 6)
1809 #define QCA_PCIE_RCX_CTRL_APP_CFG_BE_SHIFT 12
1810 #define QCA_PCIE_RCX_CTRL_APP_CFG_BE_MASK BITS(QCA_PCIE_RCX_CTRL_APP_CFG_BE_SHIFT, 4)
1811 #define QCA_PCIE_RCX_CTRL_APP_BAR_MSN_SHIFT 16
1812 #define QCA_PCIE_RCX_CTRL_APP_BAR_MSN_MASK BITS(QCA_PCIE_RCX_CTRL_APP_BAR_MSN_SHIFT, 4)
1813 #define QCA_PCIE_RCX_CTRL_APP_CFG_TYPE_SHIFT 20
1814 #define QCA_PCIE_RCX_CTRL_APP_CFG_TYPE_MASK BITS(QCA_PCIE_RCX_CTRL_APP_CFG_TYPE_SHIFT, 2)
1816 /* PCIE_RESET register (PCIE reset) */
1817 #define QCA_PCIE_RCX_CTRL_RST_LINK_UP_SHIFT 0
1818 #define QCA_PCIE_RCX_CTRL_RST_LINK_UP_MASK BIT(QCA_PCIE_RCX_CTRL_RST_LINK_UP_SHIFT)
1819 #define QCA_PCIE_RCX_CTRL_RST_LINK_REQ_RST_SHIFT 1
1820 #define QCA_PCIE_RCX_CTRL_RST_LINK_REQ_RST_MASK BIT(QCA_PCIE_RCX_CTRL_RST_LINK_REQ_RST_SHIFT)
1821 #define QCA_PCIE_RCX_CTRL_RST_EP_RST_L_SHIFT 2
1822 #define QCA_PCIE_RCX_CTRL_RST_EP_RST_L_MASK BIT(QCA_PCIE_RCX_CTRL_RST_EP_RST_L_SHIFT)
1827 #define QCA_RTC_RST_CTRL_REG QCA_RTC_BASE_REG + 0x00
1828 #define QCA_RTC_XTAL_CTRL_REG QCA_RTC_BASE_REG + 0x04
1829 #define QCA_RTC_WLAN_PLL_CTRL_REG QCA_RTC_BASE_REG + 0x14
1830 #define QCA_RTC_PLL_SETTLE_REG QCA_RTC_BASE_REG + 0x18
1831 #define QCA_RTC_XTAL_SETTLE_REG QCA_RTC_BASE_REG + 0x1C
1832 #define QCA_RTC_CLK_OUT_REG QCA_RTC_BASE_REG + 0x20
1833 #define QCA_RTC_RST_CAUSE_REG QCA_RTC_BASE_REG + 0x28
1834 #define QCA_RTC_SYS_SLEEP_REG QCA_RTC_BASE_REG + 0x2C
1835 #define QCA_RTC_KEEP_AWAKE_REG QCA_RTC_BASE_REG + 0x34
1836 #define QCA_RTC_DERIVED_RTC_CLK_REG QCA_RTC_BASE_REG + 0x38
1837 #define QCA_RTC_PLL_CTRL2_REG QCA_RTC_BASE_REG + 0x3C
1838 #define QCA_RTC_SYNC_RST_REG QCA_RTC_BASE_REG + 0x40
1839 #define QCA_RTC_SYNC_STATUS_REG QCA_RTC_BASE_REG + 0x44
1840 #define QCA_RTC_SYNC_DERIVED_REG QCA_RTC_BASE_REG + 0x48
1841 #define QCA_RTC_SYNC_FORCE_WAKE_REG QCA_RTC_BASE_REG + 0x4C
1842 #define QCA_RTC_INTERRUPT_CAUSE_REG QCA_RTC_BASE_REG + 0x50
1843 #define QCA_RTC_INTERRUPT_EN_REG QCA_RTC_BASE_REG + 0x54
1844 #define QCA_RTC_INTERRUPT_MASK_REG QCA_RTC_BASE_REG + 0x58
1847 * RTC registers BIT fields
1850 /* RESET_CONTROL register (RTC reset control) */
1851 #define QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT 0
1852 #define QCA_RTC_RST_CTRL_MAC_WARM_RST_MASK BIT(QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT)
1853 #define QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT 1
1854 #define QCA_RTC_RST_CTRL_MAC_COLD_RST_MASK BIT(QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT)
1855 #define QCA_RTC_RST_CTRL_WARM_RST_SHIFT 2
1856 #define QCA_RTC_RST_CTRL_WARM_RST_MASK BIT(QCA_RTC_RST_CTRL_WARM_RST_SHIFT)
1857 #define QCA_RTC_RST_CTRL_COLD_RST_SHIFT 3
1858 #define QCA_RTC_RST_CTRL_COLD_RST_MASK BIT(QCA_RTC_RST_CTRL_COLD_RST_SHIFT)
1860 /* RESET_CAUSE register (Reset cause) */
1861 #define QCA_RTC_RST_CAUSE_LAST_SHIFT 0
1862 #define QCA_RTC_RST_CAUSE_LAST_MASK BITS(QCA_RTC_RST_CAUSE_LAST_SHIFT, 2)
1864 #define QCA_RTC_RST_CAUSE_LAST_HARD_VAL 0
1865 #define QCA_RTC_RST_CAUSE_LAST_COLD_VAL 1
1866 #define QCA_RTC_RST_CAUSE_LAST_WARM_VAL 2
1868 /* RTC_SYNC_REGISTER register (RTC reset, force sleep and force wakeup) */
1869 #define QCA_RTC_SYNC_RST_RESET_SHIFT 0
1870 #define QCA_RTC_SYNC_RST_RESET_MASK BIT(QCA_RTC_SYNC_RST_RESET_SHIFT)
1872 /* RTC_SYNC_STATUS register (RTC sync/sleep status) */
1873 #define QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT 0
1874 #define QCA_RTC_SYNC_STATUS_SHUTDOWN_MASK BIT(QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT)
1875 #define QCA_RTC_SYNC_STATUS_ON_SHIFT 1
1876 #define QCA_RTC_SYNC_STATUS_ON_MASK BIT(QCA_RTC_SYNC_STATUS_ON_SHIFT)
1877 #define QCA_RTC_SYNC_STATUS_SLEEP_SHIFT 2
1878 #define QCA_RTC_SYNC_STATUS_SLEEP_MASK BIT(QCA_RTC_SYNC_STATUS_SLEEP_SHIFT)
1879 #define QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT 3
1880 #define QCA_RTC_SYNC_STATUS_WAKEUP_MASK BIT(QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT)
1881 #define QCA_RTC_SYNC_STATUS_WRESET_SHIFT 4
1882 #define QCA_RTC_SYNC_STATUS_WRESET_MASK BIT(QCA_RTC_SYNC_STATUS_WRESET_SHIFT)
1883 #define QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT 5
1884 #define QCA_RTC_SYNC_STATUS_PLL_CHANGING_MASK BIT(QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT)
1886 /* RTC_SYNC_FORCE_WAKE register (RTC force wake) */
1887 #define QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT 0
1888 #define QCA_RTC_SYNC_FORCE_WAKE_EN_MASK BIT(QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT)
1889 #define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT 1
1890 #define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_MASK BIT(QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT)
1893 * SPI serial flash registers
1895 #define QCA_SPI_FUNC_SEL_REG QCA_FLASH_BASE_REG + 0x00
1896 #define QCA_SPI_CTRL_REG QCA_FLASH_BASE_REG + 0x04
1897 #define QCA_SPI_IO_CTRL_REG QCA_FLASH_BASE_REG + 0x08
1898 #define QCA_SPI_READ_DATA_REG QCA_FLASH_BASE_REG + 0x0C
1899 #define QCA_SPI_SHIFT_DATAOUT_REG QCA_FLASH_BASE_REG + 0x10
1900 #define QCA_SPI_SHIFT_CNT_REG QCA_FLASH_BASE_REG + 0x14
1901 #define QCA_SPI_SHIFT_DATAIN_REG QCA_FLASH_BASE_REG + 0x18
1904 * SPI serial flash registers BIT fields
1907 /* SPI_FUNC_SELECT register (SPI function select) */
1908 #define QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT 0
1909 #define QCA_SPI_FUNC_SEL_FUNC_SEL_MASK BIT(QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT)
1911 /* SPI_CONTROL register (SPI control) */
1912 #define QCA_SPI_CTRL_CLK_DIV_SHIFT 0
1913 #define QCA_SPI_CTRL_CLK_DIV_MASK BITS(QCA_SPI_CTRL_CLK_DIV_SHIFT, 6)
1914 #define QCA_SPI_CTRL_REMAP_DIS_SHIFT 6
1915 #define QCA_SPI_CTRL_REMAP_DIS_MASK BIT(QCA_SPI_CTRL_REMAP_DIS_SHIFT)
1916 #define QCA_SPI_CTRL_SPI_RELOCATE_SHIFT 7
1917 #define QCA_SPI_CTRL_SPI_RELOCATE_MASK BIT(QCA_SPI_CTRL_SPI_RELOCATE_SHIFT)
1918 #define QCA_SPI_CTRL_TSHSL_CNT_SHIFT 8
1919 #define QCA_SPI_CTRL_TSHSL_CNT_MASK BITS(QCA_SPI_CTRL_TSHSL_CNT_SHIFT, 6)
1921 /* SPI_IO_CONTROL register (SPI I/O control) */
1922 #define QCA_SPI_IO_CTRL_IO_DO_SHIFT 0
1923 #define QCA_SPI_IO_CTRL_IO_DO_MASK BIT(QCA_SPI_IO_CTRL_IO_DO_SHIFT)
1924 #define QCA_SPI_IO_CTRL_IO_CLK_SHIFT 8
1925 #define QCA_SPI_IO_CTRL_IO_CLK_MASK BIT(QCA_SPI_IO_CTRL_IO_CLK_SHIFT)
1926 #define QCA_SPI_IO_CTRL_IO_CS0_SHIFT 16
1927 #define QCA_SPI_IO_CTRL_IO_CS0_MASK BIT(QCA_SPI_IO_CTRL_IO_CS0_SHIFT)
1928 #define QCA_SPI_IO_CTRL_IO_CS1_SHIFT 17
1929 #define QCA_SPI_IO_CTRL_IO_CS1_MASK BIT(QCA_SPI_IO_CTRL_IO_CS1_SHIFT)
1930 #define QCA_SPI_IO_CTRL_IO_CS2_SHIFT 18
1931 #define QCA_SPI_IO_CTRL_IO_CS2_MASK BIT(QCA_SPI_IO_CTRL_IO_CS2_SHIFT)
1933 /* SPI_SHIFT_CNT_ADDR register (SPI content to shift out or in) */
1934 #define QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT 0
1935 #define QCA_SPI_SHIFT_CNT_BITS_CNT_MASK BITS(QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT, 7)
1936 #define QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT 26
1937 #define QCA_SPI_SHIFT_CNT_TERMINATE_MASK BIT(QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT)
1938 #define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT 27
1939 #define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_MASK BIT(QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT)
1940 #define QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT 28
1941 #define QCA_SPI_SHIFT_CNT_CHNL_CS0_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT)
1942 #define QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT 29
1943 #define QCA_SPI_SHIFT_CNT_CHNL_CS1_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT)
1944 #define QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT 30
1945 #define QCA_SPI_SHIFT_CNT_CHNL_CS2_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT)
1946 #define QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT 31
1947 #define QCA_SPI_SHIFT_CNT_SHIFT_EN_MASK BIT(QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT)
1950 * Other useful defines
1953 /* Magic flag for indication that PLL/clocks config is stored in FLASH */
1954 #define QCA_PLL_IN_FLASH_MAGIC 0x504C4C73
1956 /* Maximum DRAM size: 256 MB */
1957 #define QCA_DRAM_MAX_SIZE_VAL (256 * 1024 * 1024)
1960 * PLL/clocks configuration in FLASH offset
1962 #if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
1963 #if !defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE)
1964 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
1967 #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET \
1969 CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
1974 * For PLL/clocks recovery use reset button by default
1976 #if defined(CONFIG_GPIO_RESET_BTN)
1977 #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN CONFIG_GPIO_RESET_BTN
1980 #if defined(CONFIG_GPIO_RESET_BTN_ACTIVE_LOW)
1981 #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW 1
1987 #ifndef __ASSEMBLY__
1988 u32 qca_dram_cas_lat(void);
1989 u32 qca_dram_ddr_width(void);
1990 void qca_dram_init(void);
1991 u32 qca_dram_size(void);
1992 u32 qca_dram_tras_lat(void);
1993 u32 qca_dram_trcd_lat(void);
1994 u32 qca_dram_trp_lat(void);
1995 u32 qca_dram_type(void);
1996 void qca_full_chip_reset(void);
1997 u32 qca_pcie_dev_info(u32 rc_num, u32 *vid, u32 *did);
1998 u32 qca_pcie0_in_ep_mode(void);
1999 void qca_sf_bulk_erase(u32 bank);
2000 u32 qca_sf_jedec_id(u32 bank);
2001 u32 qca_sf_sect_erase(u32 bank, u32 address, u32 sect_size, u8 erase_cmd);
2002 u32 qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_cmd);
2003 void qca_sf_write_page(u32 bank, u32 address, u32 length, u8 *data);
2004 void qca_soc_name_rev(char *buf);
2005 void qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk, u32 *spi_clk, u32 *ref_clk);
2006 u32 qca_xtal_is_40mhz(void);
2007 #endif /* !__ASSEMBLY__ */
2010 * Read, write, set and clear macros
2012 #define qca_soc_reg_read(_addr) \
2013 *(volatile unsigned int *)(KSEG1ADDR(_addr))
2015 #define qca_soc_reg_write(_addr, _val) \
2016 ((*(volatile unsigned int *)KSEG1ADDR(_addr)) = (_val))
2018 #define qca_soc_reg_read_set(_addr, _mask) \
2019 qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) | (_mask)))
2021 #define qca_soc_reg_read_clear(_addr, _mask) \
2022 qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) & ~(_mask)))
2024 #endif /* _QCA_SOC_COMMON_H_ */