2 * Qualcomm/Atheros Wireless SOC common registers definitions
4 * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
5 * Copyright (C) 2014 Qualcomm Atheros, Inc.
6 * Copyright (C) 2008-2010 Atheros Communications Inc.
9 * Linux/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
11 * SPDX-License-Identifier: GPL-2.0
14 #ifndef _QCA_SOC_COMMON_H_
15 #define _QCA_SOC_COMMON_H_
17 #include <soc/soc_common.h>
22 #define QCA_APB_BASE_REG 0x18000000
23 #define QCA_FLASH_BASE_REG 0x1F000000
28 #define QCA_DDR_CTRL_BASE_REG QCA_APB_BASE_REG + 0x00000000
30 #if (SOC_TYPE & QCA_AR933X_SOC)
31 #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000
33 #define QCA_LSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000
34 #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00500000
37 #define QCA_USB_CFG_BASE_REG QCA_APB_BASE_REG + 0x00030000
38 #define QCA_GPIO_BASE_REG QCA_APB_BASE_REG + 0x00040000
39 #define QCA_PLL_BASE_REG QCA_APB_BASE_REG + 0x00050000
40 #define QCA_RST_BASE_REG QCA_APB_BASE_REG + 0x00060000
41 #define QCA_GMAC_BASE_REG QCA_APB_BASE_REG + 0x00070000
42 #define QCA_RTC_BASE_REG QCA_APB_BASE_REG + 0x00107000
43 #define QCA_PLL_SRIF_BASE_REG QCA_APB_BASE_REG + 0x00116000
45 #if (SOC_TYPE & QCA_AR933X_SOC)
46 #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x00090000
47 #elif (SOC_TYPE & QCA_AR934X_SOC) |\
48 (SOC_TYPE & QCA_AR955X_SOC)
49 #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x000A9000
55 #define QCA_DDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x000
56 #define QCA_DDR_CFG2_REG QCA_DDR_CTRL_BASE_REG + 0x004
57 #define QCA_DDR_MR_REG QCA_DDR_CTRL_BASE_REG + 0x008
58 #define QCA_DDR_EMR_REG QCA_DDR_CTRL_BASE_REG + 0x00C
59 #define QCA_DDR_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x010
60 #define QCA_DDR_REFRESH_REG QCA_DDR_CTRL_BASE_REG + 0x014
61 #define QCA_DDR_RD_DATA_THIS_CYCLE_REG QCA_DDR_CTRL_BASE_REG + 0x018
62 #define QCA_DDR_TAP_CTRL_0_REG QCA_DDR_CTRL_BASE_REG + 0x01C
63 #define QCA_DDR_TAP_CTRL_1_REG QCA_DDR_CTRL_BASE_REG + 0x020
64 #define QCA_DDR_TAP_CTRL_2_REG QCA_DDR_CTRL_BASE_REG + 0x024
65 #define QCA_DDR_TAP_CTRL_3_REG QCA_DDR_CTRL_BASE_REG + 0x028
67 #if (SOC_TYPE & QCA_AR933X_SOC)
68 #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x07C
69 #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x080
70 #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x084
71 #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x08C
72 #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x090
73 #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x094
74 #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x098
75 #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x09C
76 #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0A0
77 #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0A4
78 #define QCA_SDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0D8
80 #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x09C
81 #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x0A0
82 #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x0A4
83 #define QCA_DDR_WB_FLUSH_PCIE_REG QCA_DDR_CTRL_BASE_REG + 0x0A8
84 #define QCA_DDR_WB_FLUSH_WMAC_REG QCA_DDR_CTRL_BASE_REG + 0x0AC
85 #define QCA_DDR_WB_FLUSH_SRC1_REG QCA_DDR_CTRL_BASE_REG + 0x0B0
86 #define QCA_DDR_WB_FLUSH_SRC2_REG QCA_DDR_CTRL_BASE_REG + 0x0B4
87 #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0B8
88 #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x0BC
89 #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x0C0
90 #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x0C4
91 #define QCA_DDR_BURST2_REG QCA_DDR_CTRL_BASE_REG + 0x0C8
92 #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x0CC
93 #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0D0
94 #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0D4
95 #define QCA_DDR_FSM_WAIT_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x0E4
96 #define QCA_DDR_CTRL_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x108
97 #define QCA_DDR_SELF_REFRESH_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x110
98 #define QCA_DDR_SELF_REFRESH_TIMER_REG QCA_DDR_CTRL_BASE_REG + 0x114
99 #define QCA_DDR_WMAC_FLUSH_REG QCA_DDR_CTRL_BASE_REG + 0x128
100 #define QCA_DDR_CFG3_REG QCA_DDR_CTRL_BASE_REG + 0x15C
103 * Below register addresses and names come directly form Atheros (Q)SDK code:
104 * tap-955x.S/tap-953x.S/tap-956x.S, as they do not exist in any datasheet
106 #define QCA_DDR_PERF_MASK_ADDR_0_REG QCA_DDR_CTRL_BASE_REG + 0x02C
107 #define QCA_DDR_PERF_MASK_AHB_GE0_0_REG QCA_DDR_CTRL_BASE_REG + 0x034
108 #define QCA_DDR_PERF_COMP_AHB_GE0_0_REG QCA_DDR_CTRL_BASE_REG + 0x038
109 #define QCA_DDR_PERF_MASK_AHB_GE1_0_REG QCA_DDR_CTRL_BASE_REG + 0x03C
110 #define QCA_DDR_PERF_COMP_AHB_GE1_0_REG QCA_DDR_CTRL_BASE_REG + 0x040
111 #define QCA_DDR_PERF_COMP_ADDR_1_REG QCA_DDR_CTRL_BASE_REG + 0x068
112 #define QCA_DDR_PERF_MASK_AHB_GE0_1_REG QCA_DDR_CTRL_BASE_REG + 0x06C
113 #define QCA_DDR_PERF_COMP_AHB_GE0_1_REG QCA_DDR_CTRL_BASE_REG + 0x070
114 #define QCA_DDR_PERF_MASK_AHB_GE1_1_REG QCA_DDR_CTRL_BASE_REG + 0x074
115 #define QCA_DDR_PERF_COMP_AHB_GE1_1_REG QCA_DDR_CTRL_BASE_REG + 0x078
116 #define QCA_DDR_BIST_REG QCA_DDR_CTRL_BASE_REG + 0x11C
117 #define QCA_DDR_BIST_STATUS_REG QCA_DDR_CTRL_BASE_REG + 0x120
121 * DDR registers BIT fields
124 /* DDR_CONFIG register (DDR DRAM configuration) */
125 #define QCA_DDR_CFG_TRAS_SHIFT 0
126 #define QCA_DDR_CFG_TRAS_MASK BITS(QCA_DDR_CFG_TRAS_SHIFT, 5)
127 #define QCA_DDR_CFG_TRCD_SHIFT 5
128 #define QCA_DDR_CFG_TRCD_MASK BITS(QCA_DDR_CFG_TRCD_SHIFT, 4)
129 #define QCA_DDR_CFG_TRP_SHIFT 9
130 #define QCA_DDR_CFG_TRP_MASK BITS(QCA_DDR_CFG_TRP_SHIFT, 4)
131 #define QCA_DDR_CFG_TRRD_SHIFT 13
132 #define QCA_DDR_CFG_TRRD_MASK BITS(QCA_DDR_CFG_TRRD_SHIFT, 4)
133 #define QCA_DDR_CFG_TRFC_SHIFT 17
134 #define QCA_DDR_CFG_TRFC_MASK BITS(QCA_DDR_CFG_TRFC_SHIFT, 6)
135 #define QCA_DDR_CFG_TMRD_SHIFT 23
136 #define QCA_DDR_CFG_TMRD_MASK BITS(QCA_DDR_CFG_TMRD_SHIFT, 4)
137 #define QCA_DDR_CFG_CAS_3LSB_SHIFT 27
138 #define QCA_DDR_CFG_CAS_3LSB_MASK BITS(QCA_DDR_CFG_CAS_3LSB_SHIFT, 3)
139 #define QCA_DDR_CFG_PAGE_CLOSE_SHIFT 30
140 #define QCA_DDR_CFG_PAGE_CLOSE_MASK BIT(QCA_DDR_CFG_PAGE_CLOSE_SHIFT)
141 #define QCA_DDR_CFG_CAS_MSB_SHIFT 31
142 #define QCA_DDR_CFG_CAS_MSB_MASK BIT(QCA_DDR_CFG_CAS_MSB_SHIFT)
144 /* DDR_CONFIG2 register (DDR DRAM configuration 2) */
145 #define QCA_DDR_CFG2_BURST_LEN_SHIFT 0
146 #define QCA_DDR_CFG2_BURST_LEN_MASK BITS(QCA_DDR_CFG2_BURST_LEN_SHIFT, 4)
147 #define QCA_DDR_CFG2_BURST_TYPE_SHIFT 4
148 #define QCA_DDR_CFG2_BURST_TYPE_MASK BIT(QCA_DDR_CFG2_BURST_TYPE_SHIFT)
149 #define QCA_DDR_CFG2_CTRL_OE_EN_SHIFT 5
150 #define QCA_DDR_CFG2_CTRL_OE_EN_MASK BIT(QCA_DDR_CFG2_CTRL_OE_EN_SHIFT)
151 #define QCA_DDR_CFG2_PHASE_SEL_SHIFT 6
152 #define QCA_DDR_CFG2_PHASE_SEL_MASK BIT(QCA_DDR_CFG2_PHASE_SEL_SHIFT)
153 #define QCA_DDR_CFG2_CKE_SHIFT 7
154 #define QCA_DDR_CFG2_CKE_MASK BIT(QCA_DDR_CFG2_CKE_SHIFT)
155 #define QCA_DDR_CFG2_TWR_SHIFT 8
156 #define QCA_DDR_CFG2_TWR_MASK BITS(QCA_DDR_CFG2_TWR_SHIFT, 4)
157 #define QCA_DDR_CFG2_TRTW_SHIFT 12
158 #define QCA_DDR_CFG2_TRTW_MASK BITS(QCA_DDR_CFG2_TRTW_SHIFT, 5)
159 #define QCA_DDR_CFG2_TRTP_SHIFT 17
160 #define QCA_DDR_CFG2_TRTP_MASK BITS(QCA_DDR_CFG2_TRTP_SHIFT, 4)
161 #define QCA_DDR_CFG2_TWTR_SHIFT 21
162 #define QCA_DDR_CFG2_TWTR_MASK BITS(QCA_DDR_CFG2_TWTR_SHIFT, 5)
163 #define QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT 26
164 #define QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK BITS(QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT, 4)
165 #define QCA_DDR_CFG2_SWAP_A26_A27_SHIFT 30
166 #define QCA_DDR_CFG2_SWAP_A26_A27_MASK BIT(QCA_DDR_CFG2_SWAP_A26_A27_SHIFT)
167 #define QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT 31
168 #define QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK BIT(QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT)
170 /* DDR_MODE register (DDR mode register value) */
171 #define QCA_DDR_MR_VALUE_SHIFT 0
172 #define QCA_DDR_MR_VALUE_MASK BITS(QCA_DDR_MR_VALUE_SHIFT, 14)
174 /* DDR_EMR registers (DDR extended mode register 1/2/3 values) */
175 #define QCA_DDR_EMR_VALUE_SHIFT 0
176 #define QCA_DDR_EMR_VALUE_MASK BITS(QCA_DDR_EMR_VALUE_SHIFT, 14)
178 /* DDR_CONTROL register (DDR control) */
179 #define QCA_DDR_CTRL_FORCE_MRS_SHIFT 0
180 #define QCA_DDR_CTRL_FORCE_MRS_MASK BIT(QCA_DDR_CTRL_FORCE_MRS_SHIFT)
181 #define QCA_DDR_CTRL_FORCE_EMRS_SHIFT 1
182 #define QCA_DDR_CTRL_FORCE_EMRS_MASK BIT(QCA_DDR_CTRL_FORCE_EMRS_SHIFT)
183 #define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT 2
184 #define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK BIT(QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT)
185 #define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT 3
186 #define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK BIT(QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT)
187 #define QCA_DDR_CTRL_FORCE_EMR2S_SHIFT 4
188 #define QCA_DDR_CTRL_FORCE_EMR2S_MASK BIT(QCA_DDR_CTRL_FORCE_EMR2S_SHIFT)
189 #define QCA_DDR_CTRL_FORCE_EMR3S_SHIFT 5
190 #define QCA_DDR_CTRL_FORCE_EMR3S_MASK BIT(QCA_DDR_CTRL_FORCE_EMR3S_SHIFT)
192 /* DDR_REFRESH register (DDR refresh control and configuration) */
193 #define QCA_DDR_REFRESH_PERIOD_SHIFT 0
194 #define QCA_DDR_REFRESH_PERIOD_MASK BITS(QCA_DDR_REFRESH_PERIOD_SHIFT, 14)
195 #define QCA_DDR_REFRESH_EN_SHIFT 14
196 #define QCA_DDR_REFRESH_EN_MASK BIT(QCA_DDR_REFRESH_EN_SHIFT)
198 /* DDR_RD_DATA_THIS_CYCLE register (DDR read data capture bit mask) */
199 #define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT 0
200 #define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_MASK BITS(QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT, 32)
202 /* TAP_CONTROL_X registers (DQS delay tap control for byte X) */
203 #if (SOC_TYPE & QCA_AR933X_SOC) |\
204 (SOC_TYPE & QCA_AR934X_SOC)
205 #define QCA_DDR_TAP_CTRL_TAP_L_SHIFT 0
206 #define QCA_DDR_TAP_CTRL_TAP_L_MASK BITS(QCA_DDR_TAP_CTRL_TAP_L_SHIFT, 5)
207 #define QCA_DDR_TAP_CTRL_TAP_H_SHIFT 8
208 #define QCA_DDR_TAP_CTRL_TAP_H_MASK BITS(QCA_DDR_TAP_CTRL_TAP_H_SHIFT, 5)
209 #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT 16
210 #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_MASK BIT(QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT)
212 #define QCA_DDR_TAP_CTRL_TAP_SHIFT 0
213 #define QCA_DDR_TAP_CTRL_TAP_MASK BITS(QCA_DDR_TAP_CTRL_TAP_SHIFT, 6)
216 /* DDR_DDR2_CONFIG register (DDR2 configuration) */
217 #define QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT 0
218 #define QCA_DDR_DDR2_CFG_DDR2_EN_MASK BIT(QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT)
219 #define QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT 2
220 #define QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT, 6)
221 #if (SOC_TYPE & QCA_AR933X_SOC)
222 #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT 10
223 #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 3)
225 #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT 10
226 #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 4)
229 /* DDR_BURST (DDR bank arbiter per client burst size) */
230 #define QCA_DDR_BURST_GE0_MAX_BL_SHIFT 0
231 #define QCA_DDR_BURST_GE0_MAX_BL_MASK BITS(QCA_DDR_BURST_GE0_MAX_BL_SHIFT, 4)
232 #define QCA_DDR_BURST_GE1_MAX_BL_SHIFT 4
233 #define QCA_DDR_BURST_GE1_MAX_BL_MASK BITS(QCA_DDR_BURST_GE1_MAX_BL_SHIFT, 4)
234 #define QCA_DDR_BURST_PCIE_MAX_BL_SHIFT 8
235 #define QCA_DDR_BURST_PCIE_MAX_BL_MASK BITS(QCA_DDR_BURST_PCIE_MAX_BL_SHIFT, 4)
236 #define QCA_DDR_BURST_USB_MAX_BL_SHIFT 12
237 #define QCA_DDR_BURST_USB_MAX_BL_MASK BITS(QCA_DDR_BURST_USB_MAX_BL_SHIFT, 4)
238 #define QCA_DDR_BURST_CPU_MAX_BL_SHIFT 16
239 #define QCA_DDR_BURST_CPU_MAX_BL_MASK BITS(QCA_DDR_BURST_CPU_MAX_BL_SHIFT, 4)
240 #define QCA_DDR_BURST_MAX_READ_BURST_SHIFT 20
241 #define QCA_DDR_BURST_MAX_READ_BURST_MASK BITS(QCA_DDR_BURST_MAX_READ_BURST_SHIFT, 4)
242 #define QCA_DDR_BURST_MAX_WRITE_BURST_SHIFT 24
243 #define QCA_DDR_BURST_MAX_WRITE_BURST_MASK BITS(QCA_DDR_BURST_MAX_WRITE_BURST_SHIFT, 4)
244 #define QCA_DDR_BURST_RWP_MASK_EN_SHIFT 28
245 #define QCA_DDR_BURST_RWP_MASK_EN_MASK BITS(QCA_DDR_BURST_RWP_MASK_EN_SHIFT, 2)
246 #define QCA_DDR_BURST_CPU_PRIO_BE_SHIFT 30
247 #define QCA_DDR_BURST_CPU_PRIO_BE_MASK BIT(QCA_DDR_BURST_CPU_PRIO_BE_SHIFT)
248 #define QCA_DDR_BURST_CPU_PRIO_SHIFT 31
249 #define QCA_DDR_BURST_CPU_PRIO_MASK BIT(QCA_DDR_BURST_CPU_PRIO_SHIFT)
251 /* DDR_BURST2 (DDR bank arbiter per client burst size 2) */
252 #define QCA_DDR_BURST2_WMAC_MAX_BL_SHIFT 0
253 #define QCA_DDR_BURST2_WMAC_MAX_BL_MASK BITS(QCA_DDR_BURST2_WMAC_MAX_BL_SHIFT, 4)
254 #define QCA_DDR_BURST2_MISC_SRC1_MAX_BL_SHIFT 4
255 #define QCA_DDR_BURST2_MISC_SRC1_MAX_BL_MASK BITS(QCA_DDR_BURST2_MISC_SRC1_MAX_BL_SHIFT, 4)
256 #define QCA_DDR_BURST2_MISC_SRC2_MAX_BL_SHIFT 8
257 #define QCA_DDR_BURST2_MISC_SRC2_MAX_BL_MASK BITS(QCA_DDR_BURST2_MISC_SRC2_MAX_BL_SHIFT, 4)
259 /* DDR_CTRL_CFG (DDR controller configuration) */
260 #define QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT 0
261 #define QCA_DDR_CTRL_CFG_SDRAM_EN_MASK BIT(QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT)
262 #define QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT 1
263 #define QCA_DDR_CTRL_CFG_HALF_WIDTH_MASK BIT(QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT)
264 #define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT 2
265 #define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_MASK BIT(QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT)
266 #define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT 3
267 #define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_MASK BIT(QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT)
268 #define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT 4
269 #define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_MASK BIT(QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT)
270 #define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT 6
271 #define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_MASK BIT(QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT)
273 /* DDR_CONFIG3 register (DDR DRAM configuration 3) */
274 #define QCA_DDR_CFG3_TRFC_LSB_SHIFT 0
275 #define QCA_DDR_CFG3_TRFC_LSB_MASK BITS(QCA_DDR_CFG3_TRFC_LSB_SHIFT, 2)
276 #define QCA_DDR_CFG3_TRAS_MSB_SHIFT 2
277 #define QCA_DDR_CFG3_TRAS_MSB_MASK BIT(QCA_DDR_CFG3_TRAS_MSB_SHIFT)
278 #define QCA_DDR_CFG3_TWR_MSB_SHIFT 3
279 #define QCA_DDR_CFG3_TWR_MSB_MASK BIT(QCA_DDR_CFG3_TWR_MSB_SHIFT)
281 /* DDR_BIST (unknown, not described in datasheet, based on code only) */
282 #define QCA_DDR_BIST_TEST_EN_SHIFT 0
283 #define QCA_DDR_BIST_TEST_EN_MASK BIT(QCA_DDR_BIST_TEST_EN_SHIFT)
285 /* DDR_BIST_STATUS (unknown, not described in datasheet, based on code only) */
286 #define QCA_DDR_BIST_STATUS_DONE_SHIFT 0
287 #define QCA_DDR_BIST_STATUS_DONE_MASK BIT(QCA_DDR_BIST_STATUS_DONE_SHIFT)
288 #define QCA_DDR_BIST_STATUS_PASS_CNT_SHIFT 1
289 #define QCA_DDR_BIST_STATUS_PASS_CNT_MASK BITS(QCA_DDR_BIST_STATUS_PASS_CNT_SHIFT, 8)
290 #define QCA_DDR_BIST_STATUS_FAIL_CNT_SHIFT 9
291 #define QCA_DDR_BIST_STATUS_FAIL_CNT_MASK BITS(QCA_DDR_BIST_STATUS_FAIL_CNT_SHIFT, 8)
293 /* DDR_PERF_COMP_ADDR_1 (unknown, not described in datasheet, based on code only) */
294 #define QCA_DDR_PERF_COMP_ADDR_1_TEST_CNT_SHIFT 1
295 #define QCA_DDR_PERF_COMP_ADDR_1_TEST_CNT_MASK BITS(QCA_DDR_PERF_COMP_ADDR_1_TEST_CNT_SHIFT, 8)
298 * Low-Speed UART registers
300 #define QCA_LSUART_RBR_REG QCA_LSUART_BASE_REG + 0x00
301 #define QCA_LSUART_THR_REG QCA_LSUART_BASE_REG + 0x00
302 #define QCA_LSUART_DLL_REG QCA_LSUART_BASE_REG + 0x00
303 #define QCA_LSUART_DLH_REG QCA_LSUART_BASE_REG + 0x04
304 #define QCA_LSUART_IER_REG QCA_LSUART_BASE_REG + 0x04
305 #define QCA_LSUART_IIR_REG QCA_LSUART_BASE_REG + 0x08
306 #define QCA_LSUART_FCR_REG QCA_LSUART_BASE_REG + 0x08
307 #define QCA_LSUART_LCR_REG QCA_LSUART_BASE_REG + 0x0C
308 #define QCA_LSUART_MCR_REG QCA_LSUART_BASE_REG + 0x10
309 #define QCA_LSUART_LSR_REG QCA_LSUART_BASE_REG + 0x14
310 #define QCA_LSUART_MSR_REG QCA_LSUART_BASE_REG + 0x18
313 * Low-Speed UART registers BIT fields
316 /* RBR register (Receive buffer) */
317 #define QCA_LSUART_RBR_RBR_SHIFT 0
318 #define QCA_LSUART_RBR_RBR_MASK BITS(QCA_LSUART_RBR_RBR_SHIFT, 8)
320 /* THR register (Transmit holding) */
321 #define QCA_LSUART_THR_THR_SHIFT 0
322 #define QCA_LSUART_THR_THR_MASK BITS(QCA_LSUART_THR_THR_SHIFT, 8)
324 /* DLL register (Divisor latch low) */
325 #define QCA_LSUART_DLL_DLL_SHIFT 0
326 #define QCA_LSUART_DLL_DLL_MASK BITS(QCA_LSUART_DLL_DLL_SHIFT, 8)
328 /* DLH register (Divisor latch high) */
329 #define QCA_LSUART_DLH_DLH_SHIFT 0
330 #define QCA_LSUART_DLH_DLH_MASK BITS(QCA_LSUART_DLH_DLH_SHIFT, 8)
332 /* IER register (Interrupt enable) */
333 #define QCA_LSUART_IER_ERBFI_SHIFT 0
334 #define QCA_LSUART_IER_ERBFI_MASK BIT(QCA_LSUART_IER_ERBFI_SHIFT)
335 #define QCA_LSUART_IER_ETBEI_SHIFT 1
336 #define QCA_LSUART_IER_ETBEI_MASK BIT(QCA_LSUART_IER_ETBEI_SHIFT)
337 #define QCA_LSUART_IER_ELSI_SHIFT 2
338 #define QCA_LSUART_IER_ELSI_MASK BIT(QCA_LSUART_IER_ELSI_SHIFT)
339 #define QCA_LSUART_IER_EDDSI_SHIFT 3
340 #define QCA_LSUART_IER_EDDSI_MASK BIT(QCA_LSUART_IER_EDDSI_SHIFT)
342 /* IIR register (Interrupt identity) */
343 #define QCA_LSUART_IIR_IID_SHIFT 0
344 #define QCA_LSUART_IIR_IID_MASK BITS(QCA_LSUART_IIR_IID_SHIFT, 4)
345 #define QCA_LSUART_IIR_FIFO_STATUS_SHIFT 6
346 #define QCA_LSUART_IIR_FIFO_STATUS_MASK BITS(QCA_LSUART_IIR_FIFO_STATUS_SHIFT, 2)
348 /* FCR register (FIFO control) */
349 #define QCA_LSUART_FCR_FIFO_EN_SHIFT 0
350 #define QCA_LSUART_FCR_EDDSI_MASK BIT(QCA_LSUART_FCR_FIFO_EN_SHIFT)
351 #define QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT 1
352 #define QCA_LSUART_FCR_RCVR_FIFO_RST_MASK BIT(QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT)
353 #define QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT 2
354 #define QCA_LSUART_FCR_XMIT_FIFO_RST_MASK BIT(QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT)
355 #define QCA_LSUART_FCR_DMA_MODE_SHIFT 3
356 #define QCA_LSUART_FCR_DMA_MODE_MASK BIT(QCA_LSUART_FCR_DMA_MODE_SHIFT)
357 #define QCA_LSUART_FCR_RCVR_TRIG_SHIFT 6
358 #define QCA_LSUART_FCR_RCVR_TRIG_MASK BITS(QCA_LSUART_FCR_RCVR_TRIG_SHIFT, 2)
360 /* LCR register (Line control) */
361 #define QCA_LSUART_LCR_CLS_SHIFT 0
362 #define QCA_LSUART_LCR_CLS_MASK BITS(QCA_LSUART_LCR_CLS_SHIFT, 2)
363 #define QCA_LSUART_LCR_CLS_5BIT_VAL 0x0
364 #define QCA_LSUART_LCR_CLS_6BIT_VAL 0x1
365 #define QCA_LSUART_LCR_CLS_7BIT_VAL 0x2
366 #define QCA_LSUART_LCR_CLS_8BIT_VAL 0x3
367 #define QCA_LSUART_LCR_STOP_SHIFT 2
368 #define QCA_LSUART_LCR_STOP_MASK BIT(QCA_LSUART_LCR_STOP_SHIFT)
369 #define QCA_LSUART_LCR_PEN_SHIFT 3
370 #define QCA_LSUART_LCR_PEN_MASK BIT(QCA_LSUART_LCR_PEN_SHIFT)
371 #define QCA_LSUART_LCR_EPS_SHIFT 4
372 #define QCA_LSUART_LCR_EPS_MASK BIT(QCA_LSUART_LCR_EPS_SHIFT)
373 #define QCA_LSUART_LCR_BREAK_SHIFT 6
374 #define QCA_LSUART_LCR_BREAK_MASK BIT(QCA_LSUART_LCR_BREAK_SHIFT)
375 #define QCA_LSUART_LCR_DLAB_SHIFT 7
376 #define QCA_LSUART_LCR_DLAB_MASK BIT(QCA_LSUART_LCR_DLAB_SHIFT)
378 /* MCR register (Modem control) */
379 #define QCA_LSUART_MCR_DTR_SHIFT 0
380 #define QCA_LSUART_MCR_DTR_MASK BIT(QCA_LSUART_MCR_DTR_SHIFT)
381 #define QCA_LSUART_MCR_RTS_SHIFT 1
382 #define QCA_LSUART_MCR_RTS_MASK BIT(QCA_LSUART_MCR_RTS_SHIFT)
383 #define QCA_LSUART_MCR_OUT1_SHIFT 2
384 #define QCA_LSUART_MCR_OUT1_MASK BIT(QCA_LSUART_MCR_OUT1_SHIFT)
385 #define QCA_LSUART_MCR_OUT2_SHIFT 3
386 #define QCA_LSUART_MCR_OUT2_MASK BIT(QCA_LSUART_MCR_OUT2_SHIFT)
387 #define QCA_LSUART_MCR_LOOPBACK_SHIFT 5
388 #define QCA_LSUART_MCR_LOOPBACK_MASK BIT(QCA_LSUART_MCR_LOOPBACK_SHIFT)
390 /* LSR register (Line status) */
391 #define QCA_LSUART_LSR_DR_SHIFT 0
392 #define QCA_LSUART_LSR_DR_MASK BIT(QCA_LSUART_LSR_DR_SHIFT)
393 #define QCA_LSUART_LSR_OE_SHIFT 1
394 #define QCA_LSUART_LSR_OE_MASK BIT(QCA_LSUART_LSR_OE_SHIFT)
395 #define QCA_LSUART_LSR_PE_SHIFT 2
396 #define QCA_LSUART_LSR_PE_MASK BIT(QCA_LSUART_LSR_PE_SHIFT)
397 #define QCA_LSUART_LSR_FE_SHIFT 3
398 #define QCA_LSUART_LSR_FE_MASK BIT(QCA_LSUART_LSR_FE_SHIFT)
399 #define QCA_LSUART_LSR_BI_SHIFT 4
400 #define QCA_LSUART_LSR_BI_MASK BIT(QCA_LSUART_LSR_BI_SHIFT)
401 #define QCA_LSUART_LSR_THRE_SHIFT 5
402 #define QCA_LSUART_LSR_THRE_MASK BIT(QCA_LSUART_LSR_THRE_SHIFT)
403 #define QCA_LSUART_LSR_TEMT_SHIFT 6
404 #define QCA_LSUART_LSR_TEMT_MASK BIT(QCA_LSUART_LSR_TEMT_SHIFT)
405 #define QCA_LSUART_LSR_FERR_SHIFT 7
406 #define QCA_LSUART_LSR_FERR_MASK BIT(QCA_LSUART_LSR_FERR_SHIFT)
408 /* MCR register (Modem status) */
409 #define QCA_LSUART_MCR_DCTS_SHIFT 0
410 #define QCA_LSUART_MCR_DCTS_MASK BIT(QCA_LSUART_MCR_DCTS_SHIFT)
411 #define QCA_LSUART_MCR_DDSR_SHIFT 1
412 #define QCA_LSUART_MCR_DDSR_MASK BIT(QCA_LSUART_MCR_DDSR_SHIFT)
413 #define QCA_LSUART_MCR_TERI_SHIFT 2
414 #define QCA_LSUART_MCR_TERI_MASK BIT(QCA_LSUART_MCR_TERI_SHIFT)
415 #define QCA_LSUART_MCR_DDCD_SHIFT 3
416 #define QCA_LSUART_MCR_DDCD_MASK BIT(QCA_LSUART_MCR_DDCD_SHIFT)
417 #define QCA_LSUART_MCR_CTS_SHIFT 4
418 #define QCA_LSUART_MCR_CTS_MASK BIT(QCA_LSUART_MCR_CTS_SHIFT)
419 #define QCA_LSUART_MCR_DSR_SHIFT 5
420 #define QCA_LSUART_MCR_DSR_MASK BIT(QCA_LSUART_MCR_DSR_SHIFT)
421 #define QCA_LSUART_MCR_RI_SHIFT 6
422 #define QCA_LSUART_MCR_RI_MASK BIT(QCA_LSUART_MCR_RI_SHIFT)
423 #define QCA_LSUART_MCR_DCD_SHIFT 7
424 #define QCA_LSUART_MCR_DCD_MASK BIT(QCA_LSUART_MCR_DCD_SHIFT)
427 * High-Speed UART registers
429 #define QCA_HSUART_DATA_REG QCA_HSUART_BASE_REG + 0x00
430 #define QCA_HSUART_CS_REG QCA_HSUART_BASE_REG + 0x04
431 #define QCA_HSUART_CLK_REG QCA_HSUART_BASE_REG + 0x08
432 #define QCA_HSUART_INT_REG QCA_HSUART_BASE_REG + 0x0C
433 #define QCA_HSUART_INT_EN_REG QCA_HSUART_BASE_REG + 0x10
436 * High-Speed UART registers BIT fields
439 /* UART_DATA register (UART transmit and RX FIFO interface ) */
440 #define QCA_HSUART_DATA_TX_RX_DATA_SHIFT 0
441 #define QCA_HSUART_DATA_TX_RX_DATA_MASK BITS(QCA_HSUART_DATA_TX_RX_DATA_SHIFT, 8)
442 #define QCA_HSUART_DATA_RX_CSR_SHIFT 8
443 #define QCA_HSUART_DATA_RX_CSR_MASK BIT(QCA_HSUART_DATA_RX_CSR_SHIFT)
444 #define QCA_HSUART_DATA_TX_CSR_SHIFT 9
445 #define QCA_HSUART_DATA_TX_CSR_MASK BIT(QCA_HSUART_DATA_TX_CSR_SHIFT)
447 /* UART_CS register (UART configuration and status) */
448 #define QCA_HSUART_CS_PAR_MODE_SHIFT 0
449 #define QCA_HSUART_CS_PAR_MODE_MASK BITS(QCA_HSUART_CS_PAR_MODE_SHIFT, 2)
450 #define QCA_HSUART_CS_PAR_MODE_NO_VAL 0x0
451 #define QCA_HSUART_CS_PAR_MODE_ODD_VAL 0x2
452 #define QCA_HSUART_CS_PAR_MODE_OVEN_VAL 0x3
453 #define QCA_HSUART_CS_IFACE_MODE_SHIFT 2
454 #define QCA_HSUART_CS_IFACE_MODE_MASK BITS(QCA_HSUART_CS_IFACE_MODE_SHIFT, 2)
455 #define QCA_HSUART_CS_IFACE_MODE_DISABLE_VAL 0x0
456 #define QCA_HSUART_CS_IFACE_MODE_DTE_VAL 0x1
457 #define QCA_HSUART_CS_IFACE_MODE_DCE_VAL 0x2
458 #define QCA_HSUART_CS_FLOW_MODE_SHIFT 4
459 #define QCA_HSUART_CS_FLOW_MODE_MASK BITS(QCA_HSUART_CS_FLOW_MODE_SHIFT, 2)
460 #define QCA_HSUART_CS_FLOW_MODE_NO_VAL 0x0
461 #define QCA_HSUART_CS_FLOW_MODE_HW_VAL 0x2
462 #define QCA_HSUART_CS_FLOW_MODE_INV_VAL 0x3
463 #define QCA_HSUART_CS_DMA_EN_SHIFT 6
464 #define QCA_HSUART_CS_DMA_EN_MASK BIT(QCA_HSUART_CS_DMA_EN_SHIFT)
465 #define QCA_HSUART_CS_RX_READY_ORIDE_SHIFT 7
466 #define QCA_HSUART_CS_RX_READY_ORIDE_MASK BIT(QCA_HSUART_CS_RX_READY_ORIDE_SHIFT)
467 #define QCA_HSUART_CS_TX_READY_ORIDE_SHIFT 8
468 #define QCA_HSUART_CS_TX_READY_ORIDE_MASK BIT(QCA_HSUART_CS_TX_READY_ORIDE_SHIFT)
469 #define QCA_HSUART_CS_TX_READY_SHIFT 9
470 #define QCA_HSUART_CS_TX_READY_MASK BIT(QCA_HSUART_CS_TX_READY_SHIFT)
471 #define QCA_HSUART_CS_RX_BREAK_SHIFT 10
472 #define QCA_HSUART_CS_RX_BREAK_MASK BIT(QCA_HSUART_CS_RX_BREAK_SHIFT)
473 #define QCA_HSUART_CS_TX_BREAK_SHIFT 11
474 #define QCA_HSUART_CS_TX_BREAK_MASK BIT(QCA_HSUART_CS_TX_BREAK_SHIFT)
475 #define QCA_HSUART_CS_HOST_INT_SHIFT 12
476 #define QCA_HSUART_CS_HOST_INT_MASK BIT(QCA_HSUART_CS_HOST_INT_SHIFT)
477 #define QCA_HSUART_CS_HOST_INT_EN_SHIFT 13
478 #define QCA_HSUART_CS_HOST_INT_EN_MASK BIT(QCA_HSUART_CS_HOST_INT_EN_SHIFT)
479 #define QCA_HSUART_CS_TX_BUSY_SHIFT 14
480 #define QCA_HSUART_CS_TX_BUSY_MASK BIT(QCA_HSUART_CS_TX_BUSY_SHIFT)
481 #define QCA_HSUART_CS_RX_BUSY_SHIFT 15
482 #define QCA_HSUART_CS_RX_BUSY_MASK BIT(QCA_HSUART_CS_RX_BUSY_SHIFT)
484 /* UART_CLOCK register (UART clock) */
485 #define QCA_HSUART_CLK_STEP_SHIFT 0
486 #define QCA_HSUART_CLK_STEP_MASK BITS(QCA_HSUART_CLK_STEP_SHIFT, 16)
487 #define QCA_HSUART_CLK_STEP_MAX_VAL 0x3333
488 #define QCA_HSUART_CLK_SCALE_SHIFT 16
489 #define QCA_HSUART_CLK_SCALE_MASK BITS(QCA_HSUART_CLK_SCALE_SHIFT, 8)
490 #define QCA_HSUART_CLK_SCALE_MAX_VAL 0xFF
492 /* UART_INT register (UART interrupt/control status) */
493 #define QCA_HSUART_INT_RX_VALID_SHIFT 0
494 #define QCA_HSUART_INT_RX_VALID_MASK BIT(QCA_HSUART_INT_RX_VALID_SHIFT)
495 #define QCA_HSUART_INT_TX_READY_SHIFT 1
496 #define QCA_HSUART_INT_TX_READY_MASK BIT(QCA_HSUART_INT_TX_READY_SHIFT)
497 #define QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT 2
498 #define QCA_HSUART_INT_RX_FRAMING_ERR_MASK BIT(QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT)
499 #define QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT 3
500 #define QCA_HSUART_INT_RX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT)
501 #define QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT 4
502 #define QCA_HSUART_INT_TX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT)
503 #define QCA_HSUART_INT_RX_PARITY_ERR_SHIFT 5
504 #define QCA_HSUART_INT_RX_PARITY_ERR_MASK BIT(QCA_HSUART_INT_RX_PARITY_ERR_SHIFT)
505 #define QCA_HSUART_INT_RX_BREAK_ON_SHIFT 6
506 #define QCA_HSUART_INT_RX_BREAK_ON_MASK BIT(QCA_HSUART_INT_RX_BREAK_ON_SHIFT)
507 #define QCA_HSUART_INT_RX_BREAK_OFF_SHIFT 7
508 #define QCA_HSUART_INT_RX_BREAK_OFF_MASK BIT(QCA_HSUART_INT_RX_BREAK_OFF_SHIFT)
509 #define QCA_HSUART_INT_RX_FULL_SHIFT 8
510 #define QCA_HSUART_INT_RX_FULL_MASK BIT(QCA_HSUART_INT_RX_FULL_SHIFT)
511 #define QCA_HSUART_INT_TX_EMPTY_SHIFT 9
512 #define QCA_HSUART_INT_TX_EMPTY_MASK BIT(QCA_HSUART_INT_TX_EMPTY_SHIFT)
514 /* UART_INT_EN register (UART interrupt enable) */
515 #define QCA_HSUART_INT_EN_RX_VALID_SHIFT 0
516 #define QCA_HSUART_INT_EN_RX_VALID_MASK BIT(QCA_HSUART_INT_EN_RX_VALID_SHIFT)
517 #define QCA_HSUART_INT_EN_TX_READY_SHIFT 1
518 #define QCA_HSUART_INT_EN_TX_READY_MASK BIT(QCA_HSUART_INT_EN_TX_READY_SHIFT)
519 #define QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT 2
520 #define QCA_HSUART_INT_EN_RX_FRAMING_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT)
521 #define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT 3
522 #define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT)
523 #define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT 4
524 #define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT)
525 #define QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT 5
526 #define QCA_HSUART_INT_EN_RX_PARITY_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT)
527 #define QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT 6
528 #define QCA_HSUART_INT_EN_RX_BREAK_ON_MASK BIT(QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT)
529 #define QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT 7
530 #define QCA_HSUART_INT_EN_RX_BREAK_OFF_MASK BIT(QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT)
531 #define QCA_HSUART_INT_EN_RX_FULL_SHIFT 8
532 #define QCA_HSUART_INT_EN_RX_FULL_MASK BIT(QCA_HSUART_INT_EN_RX_FULL_SHIFT)
533 #define QCA_HSUART_INT_EN_TX_EMPTY_SHIFT 9
534 #define QCA_HSUART_INT_EN_TX_EMPTY_MASK BIT(QCA_HSUART_INT_EN_TX_EMPTY_SHIFT)
540 #if (SOC_TYPE & QCA_AR933X_SOC)
541 #define QCA_GPIO_COUNT 30
542 #elif (SOC_TYPE & QCA_AR934X_SOC)
543 #define QCA_GPIO_COUNT 23
544 #elif (SOC_TYPE & QCA_QCA953X_SOC)
545 #define QCA_GPIO_COUNT 18
546 #elif (SOC_TYPE & QCA_QCA955X_SOC)
547 #define QCA_GPIO_COUNT 24
550 #define QCA_GPIO_OE_REG QCA_GPIO_BASE_REG + 0x00
551 #define QCA_GPIO_IN_REG QCA_GPIO_BASE_REG + 0x04
552 #define QCA_GPIO_OUT_REG QCA_GPIO_BASE_REG + 0x08
553 #define QCA_GPIO_SET_REG QCA_GPIO_BASE_REG + 0x0C
554 #define QCA_GPIO_CLEAR_REG QCA_GPIO_BASE_REG + 0x10
555 #define QCA_GPIO_INT_EN_REG QCA_GPIO_BASE_REG + 0x14
556 #define QCA_GPIO_INT_TYPE_REG QCA_GPIO_BASE_REG + 0x18
557 #define QCA_GPIO_INT_POLARITY_REG QCA_GPIO_BASE_REG + 0x1C
558 #define QCA_GPIO_INT_PENDING_REG QCA_GPIO_BASE_REG + 0x20
559 #define QCA_GPIO_INT_MASK_REG QCA_GPIO_BASE_REG + 0x24
561 #if (SOC_TYPE & QCA_AR933X_SOC)
562 #define QCA_GPIO_FUNC_1_REG QCA_GPIO_BASE_REG + 0x28
563 #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x2C
564 #define QCA_GPIO_FUNC_2_REG QCA_GPIO_BASE_REG + 0x30
565 #define QCA_GPIO_WLAN_MUX_SET0_REG QCA_GPIO_BASE_REG + 0x34
566 #define QCA_GPIO_WLAN_MUX_SET1_REG QCA_GPIO_BASE_REG + 0x38
567 #define QCA_GPIO_WLAN_MUX_SET2_REG QCA_GPIO_BASE_REG + 0x3C
568 #define QCA_GPIO_WLAN_MUX_SET3_REG QCA_GPIO_BASE_REG + 0x40
570 #if (SOC_TYPE & QCA_QCA955X_SOC)
571 #define QCA_GPIO_SPARE_BITS_REG QCA_GPIO_BASE_REG + 0x28
573 #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x28
576 #define QCA_GPIO_OUT_FUNC0_REG QCA_GPIO_BASE_REG + 0x2C
577 #define QCA_GPIO_OUT_FUNC1_REG QCA_GPIO_BASE_REG + 0x30
578 #define QCA_GPIO_OUT_FUNC2_REG QCA_GPIO_BASE_REG + 0x34
579 #define QCA_GPIO_OUT_FUNC3_REG QCA_GPIO_BASE_REG + 0x38
580 #define QCA_GPIO_OUT_FUNC4_REG QCA_GPIO_BASE_REG + 0x3C
581 #define QCA_GPIO_OUT_FUNC5_REG QCA_GPIO_BASE_REG + 0x40
582 #define QCA_GPIO_IN_EN0_REG QCA_GPIO_BASE_REG + 0x44
583 #define QCA_GPIO_IN_EN1_REG QCA_GPIO_BASE_REG + 0x48
584 #define QCA_GPIO_IN_EN2_REG QCA_GPIO_BASE_REG + 0x4C
585 #define QCA_GPIO_IN_EN3_REG QCA_GPIO_BASE_REG + 0x50
586 #define QCA_GPIO_IN_EN4_REG QCA_GPIO_BASE_REG + 0x54
587 #define QCA_GPIO_IN_EN9_REG QCA_GPIO_BASE_REG + 0x68
588 #define QCA_GPIO_FUNC_REG QCA_GPIO_BASE_REG + 0x6C
592 * GPIO registers BIT fields
595 /* GPIO_FUNCTION_1/2 register (GPIO function) */
596 #if (SOC_TYPE & QCA_AR933X_SOC)
597 #define QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT 0
598 #define QCA_GPIO_FUNC_1_JTAG_DIS_MASK BIT(QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT)
599 #define QCA_GPIO_FUNC_1_UART_EN_SHIFT 1
600 #define QCA_GPIO_FUNC_1_UART_EN_MASK BIT(QCA_GPIO_FUNC_1_UART_EN_SHIFT)
601 #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT 2
602 #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_MASK BIT(QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT)
603 #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT 3
604 #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT)
605 #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT 4
606 #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT)
607 #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT 5
608 #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT)
609 #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT 6
610 #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT)
611 #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT 7
612 #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT)
613 #define QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT 13
614 #define QCA_GPIO_FUNC_1_SPI_CS_EN1_MASK BIT(QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT)
615 #define QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT 14
616 #define QCA_GPIO_FUNC_1_SPI_CS_EN2_MASK BIT(QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT)
617 #define QCA_GPIO_FUNC_1_SPI_EN_SHIFT 18
618 #define QCA_GPIO_FUNC_1_SPI_EN_MASK BIT(QCA_GPIO_FUNC_1_SPI_EN_SHIFT)
619 #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT 23
620 #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT)
621 #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT 24
622 #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT)
623 #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT 25
624 #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT)
625 #define QCA_GPIO_FUNC_1_I2S_EN_SHIFT 26
626 #define QCA_GPIO_FUNC_1_I2S_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_EN_SHIFT)
627 #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT 27
628 #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT)
629 #define QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT 29
630 #define QCA_GPIO_FUNC_1_I2S_22_18_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT)
631 #define QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT 30
632 #define QCA_GPIO_FUNC_1_SPDIF_EN_MASK BIT(QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT)
633 #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT 31
634 #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_MASK BIT(QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT)
636 #define QCA_GPIO_FUNC_2_MIC_DIS_SHIFT 0
637 #define QCA_GPIO_FUNC_2_MIC_DIS_MASK BIT(QCA_GPIO_FUNC_2_MIC_DIS_SHIFT)
638 #define QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT 1
639 #define QCA_GPIO_FUNC_2_I2S_ON_LED_MASK BIT(QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT)
640 #define QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT 2
641 #define QCA_GPIO_FUNC_2_SPDIF_ON23_MASK BIT(QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT)
642 #define QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT 3
643 #define QCA_GPIO_FUNC_2_I2SCK_ON1_MASK BIT(QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT)
644 #define QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT 4
645 #define QCA_GPIO_FUNC_2_I2SWS_ON0_MASK BIT(QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT)
646 #define QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT 5
647 #define QCA_GPIO_FUNC_2_I2SSD_ON12_MASK BIT(QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT)
648 #define QCA_GPIO_FUNC_2_WPS_DIS_SHIFT 8
649 #define QCA_GPIO_FUNC_2_WPS_DIS_MASK BIT(QCA_GPIO_FUNC_2_WPS_DIS_SHIFT)
650 #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT 9
651 #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_MASK BIT(QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT)
652 #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT 10
653 #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_MASK BIT(QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT)
654 #define QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT 11
655 #define QCA_GPIO_FUNC_2_USB_LED_ON1_MASK BIT(QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT)
656 #define QCA_GPIO_FUNC_2_LNA_ON28_SHIFT 12
657 #define QCA_GPIO_FUNC_2_LNA_ON28_MASK BIT(QCA_GPIO_FUNC_2_LNA_ON28_SHIFT)
658 #define QCA_GPIO_FUNC_2_SLIC_EN_SHIFT 13
659 #define QCA_GPIO_FUNC_2_SLIC_EN_MASK BIT(QCA_GPIO_FUNC_2_SLIC_EN_SHIFT)
660 #define QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT 14
661 #define QCA_GPIO_FUNC_2_SLIC_ON18_22_MASK BIT(QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT)
662 #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT 15
663 #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_MASK BIT(QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT)
664 #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT 16
665 #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_MASK BITS(QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT, 3)
671 #define QCA_GPIO_OUT_FUNCX_GPIOX_EN_SHIFT(_gpio) ((_gpio % 4) * 8)
672 #define QCA_GPIO_OUT_FUNCX_GPIOX_EN_MASK(_gpio) BIT(((_gpio % 4) * 8), 8)
674 #define QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT 0
675 #define QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT 0
676 #define QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT 0
677 #define QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT 0
678 #define QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT 0
679 #define QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT 0
680 #define QCA_GPIO_OUT_FUNCX_GPIO0_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT, 8)
681 #define QCA_GPIO_OUT_FUNCX_GPIO4_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT, 8)
682 #define QCA_GPIO_OUT_FUNCX_GPIO8_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT, 8)
683 #define QCA_GPIO_OUT_FUNCX_GPIO12_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT, 8)
684 #define QCA_GPIO_OUT_FUNCX_GPIO16_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT, 8)
685 #define QCA_GPIO_OUT_FUNCX_GPIO20_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT, 8)
687 #define QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT 8
688 #define QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT 8
689 #define QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT 8
690 #define QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT 8
691 #define QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT 8
692 #define QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT 8
693 #define QCA_GPIO_OUT_FUNCX_GPIO1_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT, 8)
694 #define QCA_GPIO_OUT_FUNCX_GPIO5_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT, 8)
695 #define QCA_GPIO_OUT_FUNCX_GPIO9_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT, 8)
696 #define QCA_GPIO_OUT_FUNCX_GPIO13_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT, 8)
697 #define QCA_GPIO_OUT_FUNCX_GPIO17_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT, 8)
698 #define QCA_GPIO_OUT_FUNCX_GPIO21_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT, 8)
700 #define QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT 16
701 #define QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT 16
702 #define QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT 16
703 #define QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT 16
704 #define QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT 16
705 #define QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT 16
706 #define QCA_GPIO_OUT_FUNCX_GPIO2_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT, 8)
707 #define QCA_GPIO_OUT_FUNCX_GPIO6_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT, 8)
708 #define QCA_GPIO_OUT_FUNCX_GPIO10_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT, 8)
709 #define QCA_GPIO_OUT_FUNCX_GPIO14_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT, 8)
710 #define QCA_GPIO_OUT_FUNCX_GPIO18_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT, 8)
711 #define QCA_GPIO_OUT_FUNCX_GPIO22_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT, 8)
713 #define QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT 24
714 #define QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT 24
715 #define QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT 24
716 #define QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT 24
717 #define QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT 24
718 #define QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT 24
719 #define QCA_GPIO_OUT_FUNCX_GPIO3_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT, 8)
720 #define QCA_GPIO_OUT_FUNCX_GPIO7_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT, 8)
721 #define QCA_GPIO_OUT_FUNCX_GPIO11_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT, 8)
722 #define QCA_GPIO_OUT_FUNCX_GPIO15_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT, 8)
723 #define QCA_GPIO_OUT_FUNCX_GPIO19_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT, 8)
724 #define QCA_GPIO_OUT_FUNCX_GPIO23_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT, 8)
726 /* GPIO output select values (for MUX) */
727 #define QCA_GPIO_OUT_MUX_GPIO_VAL 0
728 #define QCA_GPIO_OUT_MUX_MII_EXT_MDI_VAL 1
729 #define QCA_GPIO_OUT_MUX_SYS_RST_L_VAL 1
730 #define QCA_GPIO_OUT_MUX_NAND_CS0_VAL 1
731 #define QCA_GPIO_OUT_MUX_BOOT_RXT_MDI_VAL 2
732 #define QCA_GPIO_OUT_MUX_SPI_CS0_VAL 9
734 /* 5-port ethernet switch activity LEDs */
735 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN1_VAL 26
736 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN2_VAL 27
737 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN3_VAL 28
738 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN4_VAL 29
739 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN5_VAL 30
741 /* 5-port ethernet switch collision detect LEDs */
742 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN1_VAL 31
743 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN2_VAL 32
744 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN3_VAL 33
745 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN4_VAL 34
746 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN5_VAL 35
748 /* 5-port ethernet switch full/half duplex LEDs */
749 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN1_VAL 36
750 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN2_VAL 37
751 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN3_VAL 38
752 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN4_VAL 39
753 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN5_VAL 40
755 /* 5-port ethernet switch link indicator LEDs */
756 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK1_VAL 41
757 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK2_VAL 42
758 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK3_VAL 43
759 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK4_VAL 44
760 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK5_VAL 45
762 #if (SOC_TYPE & QCA_AR934X_SOC)
763 #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL 4
764 #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL 5
765 #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL 6
766 #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL 7
767 #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL 8
768 #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL 10
769 #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL 11
770 #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL 12
771 #define QCA_GPIO_OUT_MUX_I2S_WS_VAL 13
772 #define QCA_GPIO_OUT_MUX_I2S_SD_VAL 14
773 #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL 15
774 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 16
775 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 17
776 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 18
777 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 19
778 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 20
779 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 21
780 #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL 22
781 #define QCA_GPIO_OUT_MUX_CLK_OBS7_VAL 23
782 #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL 24
783 #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL 25
784 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 46
785 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 47
786 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 48
787 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL 49
788 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 50
789 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 51
790 #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL 72
791 #define QCA_GPIO_OUT_MUX_BT_ANT_VAL 73
792 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 74
793 #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL 78
794 #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL_VAL 79
795 #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL_VAL 80
796 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 84
797 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 87
799 #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL 3
800 #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL 4
801 #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL 5
802 #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL 8
803 #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL 10
804 #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL 11
805 #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL 12
806 #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL 13
807 #define QCA_GPIO_OUT_MUX_I2S_WS_VAL 14
808 #define QCA_GPIO_OUT_MUX_I2S_SD_VAL 15
809 #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL 16
810 #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL 17
811 #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL 18
812 #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL 19
813 #define QCA_GPIO_OUT_MUX_HSUART_RXD_VAL 20 /* TODO: RXD is INPUT, mistake in QCA9558 datasheet? */
814 #define QCA_GPIO_OUT_MUX_HSUART_CTS_VAL 21 /* TODO: CTS is INPUT, mistake in QCA9558 datasheet? */
815 #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL 22
816 #define QCA_GPIO_OUT_MUX_SRIF_OUT_VAL 23
818 #if (SOC_TYPE & QCA_QCA955X_SOC)
819 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_VAL 24
820 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_VAL 25
821 #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_VAL 26
822 #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_VAL 27
823 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_INV_VAL 28
824 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_INV_VAL 29
825 #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_INV_VAL 30
826 #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_INV_VAL 31
827 #define QCA_GPIO_OUT_MUX_GE1_MII_MDO_VAL 32
828 #define QCA_GPIO_OUT_MUX_GE1_MII_MDC_VAL 33
829 #define QCA_GPIO_OUT_MUX_SWCOM2_VAL 38
830 #define QCA_GPIO_OUT_MUX_SWCOM3_VAL 39
831 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL 40
832 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL 41
833 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 42
834 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 43
835 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 44
836 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL 45
837 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 46
838 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 47
839 #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL 68
840 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 70
841 #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_STROBE_VAL 71
842 #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_DATA_VAL 72
843 #define QCA_GPIO_OUT_MUX_NAND_CS1_VAL 73
844 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 74
845 #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL 75
846 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 76
847 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_EP_VAL 77
848 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL 78
849 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 79
850 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 80
851 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 81
852 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 82
853 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 83
854 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 84
857 #if (SOC_TYPE & QCA_QCA953X_SOC)
858 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL 48
859 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL 49
860 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 50
861 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 51
862 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 52
863 #define QCA_GPIO_OUT_MUX_RX_CLEAR_INT_VAL 53
864 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 54
865 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 55
866 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 78
867 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 86
868 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 88
869 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL 89
870 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 90
871 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 91
872 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 92
873 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 93
874 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 94
875 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 95
876 #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL 96
880 /* GPIO_IN_ENABLE0 register (GPIO in signals 0) */
881 #define QCA_GPIO_IN_EN0_SPI_MISO_SHIFT 0
882 #define QCA_GPIO_IN_EN0_SPI_MISO_MASK BITS(QCA_GPIO_IN_EN0_SPI_MISO_SHIFT, 8)
883 #define QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT 8
884 #define QCA_GPIO_IN_EN0_LSUART_RXD_MASK BITS(QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT ,8)
886 /* GPIO_IN_ENABLE1 register (GPIO in signals 1) */
887 #define QCA_GPIO_IN_EN1_I2S_WS_SHIFT 0
888 #define QCA_GPIO_IN_EN1_I2S_WS_MASK BITS(QCA_GPIO_IN_EN1_I2S_WS_SHIFT ,8)
889 #define QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT 8
890 #define QCA_GPIO_IN_EN1_I2S_MIC_SD_MASK BITS(QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT ,8)
891 #define QCA_GPIO_IN_EN1_I2S_CLK_SHIFT 16
892 #define QCA_GPIO_IN_EN1_I2S_CLK_MASK BITS(QCA_GPIO_IN_EN1_I2S_CLK_SHIFT ,8)
893 #define QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT 24
894 #define QCA_GPIO_IN_EN1_I2S_MCLK_MASK BITS(QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT ,8)
896 /* GPIO_IN_ENABLE9 register (GPIO in signals 9) */
897 #define QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT 16
898 #define QCA_GPIO_IN_EN9_HSUART_RXD_MASK BITS(QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT ,8)
899 #define QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT 24
900 #define QCA_GPIO_IN_EN9_HSUART_CTS_MASK BITS(QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT ,8)
902 /* GPIO_FUNCTION register (GPIO function) */
903 #define QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT 0
904 #define QCA_GPIO_FUNC_GPIO_SRIF_EN_MASK BIT(QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT)
905 #define QCA_GPIO_FUNC_JTAG_DIS_SHIFT 1
906 #define QCA_GPIO_FUNC_JTAG_DIS_MASK BIT(QCA_GPIO_FUNC_JTAG_DIS_SHIFT)
907 #define QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT 2
908 #define QCA_GPIO_FUNC_CLK_OBS0_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT)
909 #define QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT 3
910 #define QCA_GPIO_FUNC_CLK_OBS1_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT)
911 #define QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT 4
912 #define QCA_GPIO_FUNC_CLK_OBS2_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT)
913 #define QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT 5
914 #define QCA_GPIO_FUNC_CLK_OBS3_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT)
915 #define QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT 6
916 #define QCA_GPIO_FUNC_CLK_OBS4_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT)
917 #define QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT 7
918 #define QCA_GPIO_FUNC_CLK_OBS5_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT)
919 #define QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT 8
920 #define QCA_GPIO_FUNC_CLK_OBS6_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT)
921 #define QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT 9
922 #define QCA_GPIO_FUNC_CLK_OBS7_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT)
925 * PLL control registers
927 #define QCA_PLL_CPU_PLL_CFG_REG QCA_PLL_BASE_REG + 0x00
929 #if (SOC_TYPE & QCA_AR933X_SOC)
930 #define QCA_PLL_CPU_PLL_CFG2_REG QCA_PLL_BASE_REG + 0x04
931 #define QCA_PLL_CPU_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08
932 #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG QCA_PLL_BASE_REG + 0x10
933 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x14
934 #define QCA_PLL_ETHSW_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24
935 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C
936 #define QCA_PLL_USB_SUSPEND_REG QCA_PLL_BASE_REG + 0x40
937 #define QCA_PLL_WLAN_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x44
939 #define QCA_PLL_DDR_PLL_CFG_REG QCA_PLL_BASE_REG + 0x04
940 #define QCA_PLL_CPU_DDR_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08
942 #if (SOC_TYPE & QCA_QCA955X_SOC)
943 #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x0C
944 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x10
945 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x14
946 #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x18
947 #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x1C
948 #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x20
949 #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x24
950 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x28
951 #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x2C
952 #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x30
953 #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x34
954 #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x38
955 #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x40
956 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44
957 #define QCA_PLL_ETH_SGMII_CTRL_REG QCA_PLL_BASE_REG + 0x48
958 #define QCA_PLL_ETH_SGMII_SERDES_REG QCA_PLL_BASE_REG + 0x4C
959 #define QCA_PLL_SLIC_PWM_DIV_REG QCA_PLL_BASE_REG + 0x50
961 #define QCA_PLL_CPU_SYNC_REG QCA_PLL_BASE_REG + 0x0C
962 #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x10
963 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x14
964 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x18
965 #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x1C
966 #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x20
967 #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24
969 #if (SOC_TYPE & QCA_AR9344_SOC)
970 #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28
972 #define QCA_PLL_CURR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28
975 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C
976 #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x30
977 #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x34
978 #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x38
979 #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x3C
980 #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x40
981 #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44
982 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x48
987 * PLL control registers BIT fields
990 /* CPU_PLL_CONFIG register (CPU phase lock loop configuration) */
991 #if (SOC_TYPE & QCA_AR933X_SOC)
992 #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0
993 #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 10)
994 #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 10
995 #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
996 #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 16
997 #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
998 #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 21
999 #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK BIT(QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)
1000 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 23
1001 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
1003 #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0
1004 #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 6)
1005 #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 6
1006 #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
1007 #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 12
1008 #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
1009 #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 17
1010 #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK BITS(QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT, 2)
1011 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 19
1012 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
1015 #define QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT 30
1016 #define QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK BIT(QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT)
1017 #define QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT 31
1018 #define QCA_PLL_CPU_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT)
1020 /* CPU_PLL_CONFIG2 register (CPU phase lock loop configuration, AR933x only) */
1021 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT 0
1022 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_MASK BITS(QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT, 12)
1024 /* CPU_CLOCK_CONTROL register (CPU clock control, AR933x only) */
1025 #define QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT 2
1026 #define QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK BIT(QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT)
1027 #define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT 5
1028 #define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT, 2)
1029 #define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT 10
1030 #define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT, 2)
1031 #define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT 15
1032 #define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT, 2)
1034 /* ETHSW_CLOCK_CONTROL register (Ethernet switch clock control, AR933x only) */
1035 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT 3
1036 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_MASK BIT(QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT)
1037 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT 4
1038 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_MASK BIT(QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT)
1040 /* ETH_XMII_CONTROL register (Ethernet XMII control) */
1041 #define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT 0
1042 #define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT, 8)
1043 #define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT 8
1044 #define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT, 8)
1045 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT 16
1046 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT, 8)
1047 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT 24
1048 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_MASK BIT(QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT)
1049 #define QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT 25
1050 #define QCA_PLL_ETH_XMII_CTRL_GIGE_MASK BIT(QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT)
1051 #define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT 26
1052 #define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT, 2)
1053 #define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT 28
1054 #define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT, 2)
1055 #define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT 30
1056 #define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_MASK BIT(QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT)
1057 #define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT 31
1058 #define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_MASK BIT(QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT)
1060 /* SUSPEND register (USB suspend, AR933x only) */
1061 #define QCA_PLL_USB_SUSPEND_EN_SHIFT 0
1062 #define QCA_PLL_USB_SUSPEND_EN_MASK BIT(QCA_PLL_USB_SUSPEND_EN_SHIFT)
1063 #define QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT 8
1064 #define QCA_PLL_USB_SUSPEND_RESTART_TIME_MASK BITS(QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT, 20)
1066 /* WLAN_CLOCK_CONTROL register (WLAN clock control, AR933x only) */
1067 #define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT 0
1068 #define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT)
1069 #define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT 1
1070 #define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT)
1071 #define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT 2
1072 #define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT)
1073 #define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT 3
1074 #define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT)
1075 #define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT 4
1076 #define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT)
1077 #define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT 8
1078 #define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT)
1079 #define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT 9
1080 #define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT)
1081 #define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT 10
1082 #define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT)
1083 #define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT 12
1084 #define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT)
1086 /* DDR_PLL_CONFIG register (DDR PLL configuration) */
1087 #define QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT 0
1088 #define QCA_PLL_DDR_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT, 10)
1089 #define QCA_PLL_DDR_PLL_CFG_NINT_SHIFT 10
1090 #define QCA_PLL_DDR_PLL_CFG_NINT_MASK BITS(QCA_PLL_DDR_PLL_CFG_NINT_SHIFT, 6)
1091 #define QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT 16
1092 #define QCA_PLL_DDR_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT, 5)
1093 #define QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT 21
1094 #define QCA_PLL_DDR_PLL_CFG_RANGE_MASK BITS(QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT, 2)
1095 #define QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT 23
1096 #define QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT, 3)
1097 #define QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT 30
1098 #define QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK BIT(QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT)
1099 #define QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT 31
1100 #define QCA_PLL_DDR_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT)
1102 /* CPU_DDR_CLOCK_CONTROL register (CPU DDR clock control) */
1103 #define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT 1
1104 #define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT)
1105 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT 2
1106 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT)
1107 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT 3
1108 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT)
1109 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT 4
1110 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT)
1111 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
1112 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT, 5)
1113 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
1114 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT, 5)
1115 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
1116 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT, 5)
1117 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT 20
1118 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT)
1119 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT 21
1120 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT)
1121 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT 22
1122 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT)
1123 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT 23
1124 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT)
1125 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT 24
1126 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT)
1128 /* SWITCH_CLOCK_CONTROL */
1129 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT 0
1130 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT)
1131 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT 1
1132 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT)
1133 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT 2
1134 #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT)
1135 #define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT 3
1136 #define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT)
1137 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT 4
1138 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT)
1139 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT 5
1140 #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT)
1142 #if (SOC_TYPE & QCA_AR934X_SOC) |\
1143 (SOC_TYPE & QCA_QCA953X_SOC)
1144 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT 6
1145 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT)
1147 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT 6
1148 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT)
1149 #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT 12
1150 #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT)
1151 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT 13
1152 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT)
1153 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT 14
1154 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT)
1155 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT 15
1156 #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT)
1159 #define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT 7
1160 #define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT)
1161 #define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT 8
1162 #define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_MASK BITS(QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT, 4)
1164 /* DDR_PLL_DITHER register (DDR PLL dither parameter) */
1165 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT 0
1166 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT, 10)
1167 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT 10
1168 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 10)
1169 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_SHIFT 20
1170 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 7)
1171 #define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT 27
1172 #define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT, 4)
1173 #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT 31
1174 #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT)
1176 #if (SOC_TYPE & QCA_AR933X_SOC)
1177 /* PLL_DITHER_FRAC register (CPU PLL dither FRAC) */
1178 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT 0
1179 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT, 10)
1180 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT 10
1181 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT, 10)
1182 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT 20
1183 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT, 10)
1185 /* PLL_DITHER register (CPU PLL dither) */
1186 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 0
1187 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 14)
1188 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31
1189 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT)
1191 /* CPU_PLL_DITHER register (CPU PLL dither parameter) */
1192 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT 0
1193 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 6)
1194 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT 6
1195 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
1196 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 12
1197 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
1198 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 18
1199 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6)
1200 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31
1201 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT)
1205 * PLL SRIF registers (not available in AR933x)
1207 #define QCA_PLL_SRIF_CPU_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x1C0
1208 #define QCA_PLL_SRIF_CPU_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x1C4
1209 #define QCA_PLL_SRIF_CPU_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x1C8
1210 #define QCA_PLL_SRIF_AUD_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x200
1211 #define QCA_PLL_SRIF_AUD_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x204
1212 #define QCA_PLL_SRIF_AUD_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x208
1213 #define QCA_PLL_SRIF_DDR_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x240
1214 #define QCA_PLL_SRIF_DDR_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x244
1215 #define QCA_PLL_SRIF_DDR_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x248
1216 #define QCA_PLL_SRIF_PCIE_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0xC00
1217 #define QCA_PLL_SRIF_PCIE_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0xC04
1218 #define QCA_PLL_SRIF_PCIE_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0xC08
1221 * PLL SRIF registers BIT fields (not available in AR933x)
1224 /* DPLL1 (common for CPU, AUD, DDR and PCIE) */
1225 #define QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT 0
1226 #define QCA_PLL_SRIF_DPLL1_NFRAC_MASK BITS(QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT, 18)
1227 #define QCA_PLL_SRIF_DPLL1_NINT_SHIFT 18
1228 #define QCA_PLL_SRIF_DPLL1_NINT_MASK BITS(QCA_PLL_SRIF_DPLL1_NINT_SHIFT, 9)
1229 #define QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT 27
1230 #define QCA_PLL_SRIF_DPLL1_REFDIV_MASK BITS(QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT, 5)
1232 /* DPLL2 (common for CPU, AUD, DDR and PCIE) */
1233 #if (SOC_TYPE & QCA_QCA953X_SOC)
1234 #define QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT 0
1235 #define QCA_PLL_SRIF_DPLL2_RST_TEST_MASK BIT(QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT)
1236 #define QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT 1
1237 #define QCA_PLL_SRIF_DPLL2_SEL_CNT_MASK BIT(QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT)
1238 #define QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT 2
1239 #define QCA_PLL_SRIF_DPLL2_TEST_IN_MASK BITS(QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT, 10)
1240 #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT 12
1241 #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_MASK BITS(QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT, 7)
1242 #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 19
1243 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 3)
1244 #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 22
1245 #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK BIT(QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
1246 #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT 23
1247 #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_MASK BIT(QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT)
1248 #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT 24
1249 #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_MASK BIT(QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT)
1250 #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 25
1251 #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 4)
1252 #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 29
1253 #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 2)
1254 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 31
1255 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK BIT(QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
1257 #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 13
1258 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2)
1259 #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 16
1260 #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK BIT(QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
1261 #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 19
1262 #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7)
1263 #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 26
1264 #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KI_SHIFT, 4)
1265 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 30
1266 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK BIT(QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
1267 #define QCA_PLL_SRIF_DPLL2_RANGE_SHIFT 31
1268 #define QCA_PLL_SRIF_DPLL2_RANGE_MASK BIT(QCA_PLL_SRIF_DPLL2_RANGE_SHIFT)
1271 /* DPLL3 (common for CPU, AUD, DDR and PCIE) */
1272 #define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT 23
1273 #define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_MASK BITS(QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT, 7)
1276 * Reset control registers
1278 #define QCA_RST_GENERAL_TIMER1_REG QCA_RST_BASE_REG + 0x00
1279 #define QCA_RST_GENERAL_TIMER1_RELOAD_REG QCA_RST_BASE_REG + 0x04
1280 #define QCA_RST_WATCHDOG_TIMER_CTRL_REG QCA_RST_BASE_REG + 0x08
1281 #define QCA_RST_WATCHDOG_TIMER_REG QCA_RST_BASE_REG + 0x0C
1282 #define QCA_RST_MISC_INTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x10
1283 #define QCA_RST_MISC_INTERRUPT_MASK_REG QCA_RST_BASE_REG + 0x14
1284 #define QCA_RST_GLOBALINTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x18
1285 #define QCA_RST_RESET_REG QCA_RST_BASE_REG + 0x1C
1286 #define QCA_RST_REVISION_ID_REG QCA_RST_BASE_REG + 0x90
1287 #define QCA_RST_GENERAL_TIMER2_REG QCA_RST_BASE_REG + 0x94
1288 #define QCA_RST_GENERAL_TIMER2_RELOAD_REG QCA_RST_BASE_REG + 0x98
1289 #define QCA_RST_GENERAL_TIMER3_REG QCA_RST_BASE_REG + 0x9C
1290 #define QCA_RST_GENERAL_TIMER3_RELOAD_REG QCA_RST_BASE_REG + 0xA0
1291 #define QCA_RST_GENERAL_TIMER4_REG QCA_RST_BASE_REG + 0xA4
1292 #define QCA_RST_GENERAL_TIMER4_RELOAD_REG QCA_RST_BASE_REG + 0xA8
1294 #if (SOC_TYPE & QCA_AR933X_SOC)
1295 #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xAC
1297 #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xB0
1301 * Reset control registers BIT fields
1304 /* RST_BOOTSTRAP (Reset bootstrap) */
1305 #if (SOC_TYPE & QCA_AR933X_SOC)
1306 #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 0
1308 #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 4
1310 #define QCA_RST_BOOTSTRAP_REF_CLK_MASK BIT(QCA_RST_BOOTSTRAP_REF_CLK_SHIFT)
1311 #define QCA_RST_BOOTSTRAP_REF_CLK_25M_VAL 0x0
1312 #define QCA_RST_BOOTSTRAP_REF_CLK_40M_VAL 0x1
1314 #if (SOC_TYPE & QCA_AR933X_SOC)
1315 #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT 3
1316 #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK BIT(QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT)
1317 #define QCA_RST_BOOTSTRAP_EEPBUSY_SHIFT 4
1318 #define QCA_RST_BOOTSTRAP_EEPBUSY_MASK BIT(QCA_RST_BOOTSTRAP_EEPBUSY_SHIFT)
1319 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 12
1320 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
1321 #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT 16
1322 #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK BIT(QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT)
1323 #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT 17
1324 #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_MASK BIT(QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT)
1325 #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT 18
1326 #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_MASK BIT(QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT)
1328 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 0
1329 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1
1330 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 2
1332 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 0
1334 /* v2 does not support SDR, but we can read reserved bit and make it universal */
1335 #if (SOC_TYPE & QCA_QCA953X_SOC)
1336 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
1338 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BIT(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT)
1341 #define QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT 2
1342 #define QCA_RST_BOOTSTRAP_BOOT_SEL_MASK BIT(QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT)
1343 #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT 3
1344 #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_MASK BIT(QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT)
1345 #define QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT 5
1346 #define QCA_RST_BOOTSTRAP_JTAG_MODE_MASK BIT(QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT)
1347 #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT 7
1348 #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK BIT(QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT)
1350 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 3
1351 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1
1352 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 0
1356 #define QCA_RST_RESET_I2C_RST_SHIFT 0
1357 #define QCA_RST_RESET_I2C_RST_MASK BIT(QCA_RST_RESET_I2C_RST_SHIFT)
1358 #define QCA_RST_RESET_MBOX_RST_SHIFT 1
1359 #define QCA_RST_RESET_MBOX_RST_MASK BIT(QCA_RST_RESET_MBOX_RST_SHIFT)
1360 #define QCA_RST_RESET_LUT_RST_SHIFT 2
1361 #define QCA_RST_RESET_LUT_RST_MASK BIT(QCA_RST_RESET_LUT_RST_SHIFT)
1362 #define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT 3
1363 #define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_MASK BIT(QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT)
1364 #define QCA_RST_RESET_USB_PHY_RST_SHIFT 4
1365 #define QCA_RST_RESET_USB_PHY_RST_MASK BIT(QCA_RST_RESET_USB_PHY_RST_SHIFT)
1366 #define QCA_RST_RESET_USB_HOST_RST_SHIFT 5
1367 #define QCA_RST_RESET_USB_HOST_RST_MASK BIT(QCA_RST_RESET_USB_HOST_RST_SHIFT)
1369 #if (SOC_TYPE & QCA_AR933X_SOC)
1370 #define QCA_RST_RESET_SLIC_RST_SHIFT 6
1371 #define QCA_RST_RESET_SLIC_RST_MASK BIT(QCA_RST_RESET_SLIC_RST_SHIFT)
1373 #define QCA_RST_RESET_PCIE_RST_SHIFT 6
1374 #define QCA_RST_RESET_PCIE_RST_MASK BIT(QCA_RST_RESET_PCIE_RST_SHIFT)
1375 #define QCA_RST_RESET_SLIC_RST_SHIFT 30
1376 #define QCA_RST_RESET_SLIC_RST_MASK BIT(QCA_RST_RESET_SLIC_RST_SHIFT)
1379 #define QCA_RST_RESET_PCIE_PHY_RST_SHIFT 7
1380 #define QCA_RST_RESET_PCIE_PHY_RST_MASK BIT(QCA_RST_RESET_PCIE_PHY_RST_SHIFT)
1382 #if (SOC_TYPE & QCA_QCA955X_SOC)
1383 #define QCA_RST_RESET_ETH_SGMII_RST_SHIFT 8
1384 #define QCA_RST_RESET_ETH_SGMII_RST_MASK BIT(QCA_RST_RESET_ETH_SGMII_RST_SHIFT)
1386 #define QCA_RST_RESET_ETH_SWITCH_RST_SHIFT 8
1387 #define QCA_RST_RESET_ETH_SWITCH_RST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_RST_SHIFT)
1390 #define QCA_RST_RESET_GE0_MAC_RST_SHIFT 9
1391 #define QCA_RST_RESET_GE0_MAC_RST_MASK BIT(QCA_RST_RESET_GE0_MAC_RST_SHIFT)
1392 #define QCA_RST_RESET_HOST_DMA_INT_SHIFT 10
1393 #define QCA_RST_RESET_HOST_DMA_INT_MASK BIT(QCA_RST_RESET_HOST_DMA_INT_SHIFT)
1395 #if (SOC_TYPE & QCA_AR933X_SOC)
1396 #define QCA_RST_RESET_WLAN_RST_SHIFT 11
1397 #define QCA_RST_RESET_WLAN_RST_MASK BIT(QCA_RST_RESET_WLAN_RST_SHIFT)
1399 #define QCA_RST_RESET_USB_PHY_ARST_SHIFT 11
1400 #define QCA_RST_RESET_USB_PHY_ARST_MASK BIT(QCA_RST_RESET_USB_PHY_ARST_SHIFT)
1403 #if (SOC_TYPE & QCA_AR933X_SOC)
1404 #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 14
1405 #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
1407 #if (SOC_TYPE & QCA_QCA955X_SOC)
1408 #define QCA_RST_RESET_ETH_SGMII_ARST_SHIFT 12
1409 #define QCA_RST_RESET_ETH_SGMII_ARST_MASK BIT(QCA_RST_RESET_ETH_SGMII_ARST_SHIFT)
1411 #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 12
1412 #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
1415 #define QCA_RST_RESET_NANDF_RST_SHIFT 14
1416 #define QCA_RST_RESET_NANDF_RST_MASK BIT(QCA_RST_RESET_NANDF_RST_SHIFT)
1419 #define QCA_RST_RESET_GE1_MAC_RST_SHIFT 13
1420 #define QCA_RST_RESET_GE1_MAC_RST_MASK BIT(QCA_RST_RESET_GE1_MAC_RST_SHIFT)
1421 #define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT 15
1422 #define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_MASK BIT(QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT)
1423 #define QCA_RST_RESET_DDR_RST_SHIFT 16
1424 #define QCA_RST_RESET_DDR_RST_MASK BIT(QCA_RST_RESET_DDR_RST_SHIFT)
1425 #define QCA_RST_RESET_HSUART_RST_SHIFT 17
1426 #define QCA_RST_RESET_HSUART_RST_MASK BIT(QCA_RST_RESET_HSUART_RST_SHIFT)
1427 #define QCA_RST_RESET_PCIEEP_RST_SHIFT 18
1428 #define QCA_RST_RESET_PCIEEP_RST_MASK BIT(QCA_RST_RESET_PCIEEP_RST_SHIFT)
1429 #define QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT 19
1430 #define QCA_RST_RESET_HOST_DMA_RST_INT_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT)
1431 #define QCA_RST_RESET_CPU_COLD_RST_SHIFT 20
1432 #define QCA_RST_RESET_CPU_COLD_RST_MASK BIT(QCA_RST_RESET_CPU_COLD_RST_SHIFT)
1433 #define QCA_RST_RESET_CPU_NMI_SHIFT 21
1434 #define QCA_RST_RESET_CPU_NMI_MASK BIT(QCA_RST_RESET_CPU_NMI_SHIFT)
1435 #define QCA_RST_RESET_GE0_MDIO_RST_SHIFT 22
1436 #define QCA_RST_RESET_GE0_MDIO_RST_MASK BIT(QCA_RST_RESET_GE0_MDIO_RST_SHIFT)
1437 #define QCA_RST_RESET_GE1_MDIO_RST_SHIFT 23
1438 #define QCA_RST_RESET_GE1_MDIO_RST_MASK BIT(QCA_RST_RESET_GE1_MDIO_RST_SHIFT)
1439 #define QCA_RST_RESET_FULL_CHIP_RST_SHIFT 24
1440 #define QCA_RST_RESET_FULL_CHIP_RST_MASK BIT(QCA_RST_RESET_FULL_CHIP_RST_SHIFT)
1441 #define QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT 25
1442 #define QCA_RST_RESET_CHECKSUM_ACC_RST_MASK BIT(QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT)
1443 #define QCA_RST_RESET_PCIEEP_RST_INT_SHIFT 26
1444 #define QCA_RST_RESET_PCIEEP_RST_INT_MASK BIT(QCA_RST_RESET_PCIEEP_RST_INT_SHIFT)
1445 #define QCA_RST_RESET_RTC_RST_SHIFT 27
1446 #define QCA_RST_RESET_RTC_RST_MASK BIT(QCA_RST_RESET_RTC_RST_SHIFT)
1447 #define QCA_RST_RESET_EXT_RST_SHIFT 28
1448 #define QCA_RST_RESET_EXT_RST_MASK BIT(QCA_RST_RESET_EXT_RST_SHIFT)
1450 #if (SOC_TYPE & QCA_AR934X_SOC) |\
1451 (SOC_TYPE & QCA_QCA955X_SOC)
1452 #define QCA_RST_RESET_HOST_DMA_RST_SHIFT 29
1453 #define QCA_RST_RESET_HOST_DMA_RST_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_SHIFT)
1455 #define QCA_RST_RESET_USB_EXT_PWR_SHIFT 29
1456 #define QCA_RST_RESET_USB_EXT_PWR_MASK BIT(QCA_RST_RESET_USB_EXT_PWR_SHIFT)
1459 #define QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT 31
1460 #define QCA_RST_RESET_HOST_DMA_RST_STATUS_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT)
1462 /* RST_REVISION_ID (Chip revision ID) */
1463 #define QCA_RST_REVISION_ID_MAJOR_SHIFT 4
1464 #define QCA_RST_REVISION_ID_MAJOR_MASK BITS(QCA_RST_REVISION_ID_MAJOR_SHIFT, 12)
1466 #if (SOC_TYPE & QCA_AR933X_SOC)
1467 #define QCA_RST_REVISION_ID_REV_SHIFT 0
1468 #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 2)
1470 #define QCA_RST_REVISION_ID_REV_SHIFT 0
1471 #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 4)
1474 #define QCA_RST_REVISION_ID_MAJOR_AR9330_VAL 0x0110
1475 #define QCA_RST_REVISION_ID_MAJOR_AR9331_VAL 0x1110
1476 #define QCA_RST_REVISION_ID_MAJOR_AR9341_VAL 0x0120
1477 #define QCA_RST_REVISION_ID_MAJOR_AR9344_VAL 0x2120
1478 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL 0x0140
1479 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL 0x0160
1480 #define QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL 0x1130
1485 #define QCA_RTC_RST_CTRL_REG QCA_RTC_BASE_REG + 0x00
1486 #define QCA_RTC_XTAL_CTRL_REG QCA_RTC_BASE_REG + 0x04
1487 #define QCA_RTC_WLAN_PLL_CTRL_REG QCA_RTC_BASE_REG + 0x14
1488 #define QCA_RTC_PLL_SETTLE_REG QCA_RTC_BASE_REG + 0x18
1489 #define QCA_RTC_XTAL_SETTLE_REG QCA_RTC_BASE_REG + 0x1C
1490 #define QCA_RTC_CLK_OUT_REG QCA_RTC_BASE_REG + 0x20
1491 #define QCA_RTC_RST_CAUSE_REG QCA_RTC_BASE_REG + 0x28
1492 #define QCA_RTC_SYS_SLEEP_REG QCA_RTC_BASE_REG + 0x2C
1493 #define QCA_RTC_KEEP_AWAKE_REG QCA_RTC_BASE_REG + 0x34
1494 #define QCA_RTC_DERIVED_RTC_CLK_REG QCA_RTC_BASE_REG + 0x38
1495 #define QCA_RTC_PLL_CTRL2_REG QCA_RTC_BASE_REG + 0x3C
1496 #define QCA_RTC_SYNC_RST_REG QCA_RTC_BASE_REG + 0x40
1497 #define QCA_RTC_SYNC_STATUS_REG QCA_RTC_BASE_REG + 0x44
1498 #define QCA_RTC_SYNC_DERIVED_REG QCA_RTC_BASE_REG + 0x48
1499 #define QCA_RTC_SYNC_FORCE_WAKE_REG QCA_RTC_BASE_REG + 0x4C
1500 #define QCA_RTC_INTERRUPT_CAUSE_REG QCA_RTC_BASE_REG + 0x50
1501 #define QCA_RTC_INTERRUPT_EN_REG QCA_RTC_BASE_REG + 0x54
1502 #define QCA_RTC_INTERRUPT_MASK_REG QCA_RTC_BASE_REG + 0x58
1505 * RTC registers BIT fields
1508 /* RESET_CONTROL register (RTC reset control) */
1509 #define QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT 0
1510 #define QCA_RTC_RST_CTRL_MAC_WARM_RST_MASK BIT(QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT)
1511 #define QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT 1
1512 #define QCA_RTC_RST_CTRL_MAC_COLD_RST_MASK BIT(QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT)
1513 #define QCA_RTC_RST_CTRL_WARM_RST_SHIFT 2
1514 #define QCA_RTC_RST_CTRL_WARM_RST_MASK BIT(QCA_RTC_RST_CTRL_WARM_RST_SHIFT)
1515 #define QCA_RTC_RST_CTRL_COLD_RST_SHIFT 3
1516 #define QCA_RTC_RST_CTRL_COLD_RST_MASK BIT(QCA_RTC_RST_CTRL_COLD_RST_SHIFT)
1518 /* RESET_CAUSE register (Reset cause) */
1519 #define QCA_RTC_RST_CAUSE_LAST_SHIFT 0
1520 #define QCA_RTC_RST_CAUSE_LAST_MASK BITS(QCA_RTC_RST_CAUSE_LAST_SHIFT, 2)
1522 #define QCA_RTC_RST_CAUSE_LAST_HARD_VAL 0
1523 #define QCA_RTC_RST_CAUSE_LAST_COLD_VAL 1
1524 #define QCA_RTC_RST_CAUSE_LAST_WARM_VAL 2
1526 /* RTC_SYNC_REGISTER register (RTC reset, force sleep and force wakeup) */
1527 #define QCA_RTC_SYNC_RST_RESET_SHIFT 0
1528 #define QCA_RTC_SYNC_RST_RESET_MASK BIT(QCA_RTC_SYNC_RST_RESET_SHIFT)
1530 /* RTC_SYNC_STATUS register (RTC sync/sleep status) */
1531 #define QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT 0
1532 #define QCA_RTC_SYNC_STATUS_SHUTDOWN_MASK BIT(QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT)
1533 #define QCA_RTC_SYNC_STATUS_ON_SHIFT 1
1534 #define QCA_RTC_SYNC_STATUS_ON_MASK BIT(QCA_RTC_SYNC_STATUS_ON_SHIFT)
1535 #define QCA_RTC_SYNC_STATUS_SLEEP_SHIFT 2
1536 #define QCA_RTC_SYNC_STATUS_SLEEP_MASK BIT(QCA_RTC_SYNC_STATUS_SLEEP_SHIFT)
1537 #define QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT 3
1538 #define QCA_RTC_SYNC_STATUS_WAKEUP_MASK BIT(QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT)
1539 #define QCA_RTC_SYNC_STATUS_WRESET_SHIFT 4
1540 #define QCA_RTC_SYNC_STATUS_WRESET_MASK BIT(QCA_RTC_SYNC_STATUS_WRESET_SHIFT)
1541 #define QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT 5
1542 #define QCA_RTC_SYNC_STATUS_PLL_CHANGING_MASK BIT(QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT)
1544 /* RTC_SYNC_FORCE_WAKE register (RTC force wake) */
1545 #define QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT 0
1546 #define QCA_RTC_SYNC_FORCE_WAKE_EN_MASK BIT(QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT)
1547 #define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT 1
1548 #define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_MASK BIT(QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT)
1551 * SPI serial flash registers
1553 #define QCA_SPI_FUNC_SEL_REG QCA_FLASH_BASE_REG + 0x00
1554 #define QCA_SPI_CTRL_REG QCA_FLASH_BASE_REG + 0x04
1555 #define QCA_SPI_IO_CTRL_REG QCA_FLASH_BASE_REG + 0x08
1556 #define QCA_SPI_READ_DATA_REG QCA_FLASH_BASE_REG + 0x0C
1557 #define QCA_SPI_SHIFT_DATAOUT_REG QCA_FLASH_BASE_REG + 0x10
1558 #define QCA_SPI_SHIFT_CNT_REG QCA_FLASH_BASE_REG + 0x14
1559 #define QCA_SPI_SHIFT_DATAIN_REG QCA_FLASH_BASE_REG + 0x18
1562 * SPI serial flash registers BIT fields
1565 /* SPI_FUNC_SELECT register (SPI function select) */
1566 #define QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT 0
1567 #define QCA_SPI_FUNC_SEL_FUNC_SEL_MASK BIT(QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT)
1569 /* SPI_CONTROL register (SPI control) */
1570 #define QCA_SPI_CTRL_CLK_DIV_SHIFT 0
1571 #define QCA_SPI_CTRL_CLK_DIV_MASK BITS(QCA_SPI_CTRL_CLK_DIV_SHIFT, 6)
1572 #define QCA_SPI_CTRL_REMAP_DIS_SHIFT 6
1573 #define QCA_SPI_CTRL_REMAP_DIS_MASK BIT(QCA_SPI_CTRL_REMAP_DIS_SHIFT)
1574 #define QCA_SPI_CTRL_SPI_RELOCATE_SHIFT 7
1575 #define QCA_SPI_CTRL_SPI_RELOCATE_MASK BIT(QCA_SPI_CTRL_SPI_RELOCATE_SHIFT)
1576 #define QCA_SPI_CTRL_TSHSL_CNT_SHIFT 8
1577 #define QCA_SPI_CTRL_TSHSL_CNT_MASK BITS(QCA_SPI_CTRL_TSHSL_CNT_SHIFT, 6)
1579 /* SPI_IO_CONTROL register (SPI I/O control) */
1580 #define QCA_SPI_IO_CTRL_IO_DO_SHIFT 0
1581 #define QCA_SPI_IO_CTRL_IO_DO_MASK BIT(QCA_SPI_IO_CTRL_IO_DO_SHIFT)
1582 #define QCA_SPI_IO_CTRL_IO_CLK_SHIFT 8
1583 #define QCA_SPI_IO_CTRL_IO_CLK_MASK BIT(QCA_SPI_IO_CTRL_IO_CLK_SHIFT)
1584 #define QCA_SPI_IO_CTRL_IO_CS0_SHIFT 16
1585 #define QCA_SPI_IO_CTRL_IO_CS0_MASK BIT(QCA_SPI_IO_CTRL_IO_CS0_SHIFT)
1586 #define QCA_SPI_IO_CTRL_IO_CS1_SHIFT 17
1587 #define QCA_SPI_IO_CTRL_IO_CS1_MASK BIT(QCA_SPI_IO_CTRL_IO_CS1_SHIFT)
1588 #define QCA_SPI_IO_CTRL_IO_CS2_SHIFT 18
1589 #define QCA_SPI_IO_CTRL_IO_CS2_MASK BIT(QCA_SPI_IO_CTRL_IO_CS2_SHIFT)
1591 /* SPI_SHIFT_CNT_ADDR register (SPI content to shift out or in) */
1592 #define QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT 0
1593 #define QCA_SPI_SHIFT_CNT_BITS_CNT_MASK BITS(QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT, 7)
1594 #define QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT 26
1595 #define QCA_SPI_SHIFT_CNT_TERMINATE_MASK BIT(QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT)
1596 #define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT 27
1597 #define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_MASK BIT(QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT)
1598 #define QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT 28
1599 #define QCA_SPI_SHIFT_CNT_CHNL_CS0_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT)
1600 #define QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT 29
1601 #define QCA_SPI_SHIFT_CNT_CHNL_CS1_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT)
1602 #define QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT 30
1603 #define QCA_SPI_SHIFT_CNT_CHNL_CS2_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT)
1604 #define QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT 31
1605 #define QCA_SPI_SHIFT_CNT_SHIFT_EN_MASK BIT(QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT)
1608 * Other useful defines
1611 /* Magic flag for indication that PLL/clocks config is stored in FLASH */
1612 #define QCA_PLL_IN_FLASH_MAGIC 0x504C4C73
1614 /* Maximum DRAM size: 256 MB */
1615 #define QCA_DRAM_MAX_SIZE_VAL (256 * 1024 * 1024)
1620 #ifndef __ASSEMBLY__
1621 inline u32 qca_xtal_is_40mhz(void);
1622 void qca_soc_name_rev(char *buf);
1623 void qca_full_chip_reset(void);
1624 void qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk, u32 *spi_clk, u32 *ref_clk);
1625 void qca_sf_bulk_erase(u32 bank);
1626 void qca_sf_write_page(u32 bank, u32 address, u32 length, u8 *data);
1627 u32 qca_sf_sect_erase(u32 bank, u32 address, u32 sect_size, u8 erase_cmd);
1628 u32 qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_cmd);
1629 u32 qca_sf_jedec_id(u32 bank);
1630 u32 qca_dram_type(void);
1631 u32 qca_dram_size(void);
1632 u32 qca_dram_ddr_width(void);
1633 void qca_dram_init(void);
1634 inline u32 qca_dram_cas_lat(void);
1635 inline u32 qca_dram_trcd_lat(void);
1636 inline u32 qca_dram_trp_lat(void);
1637 inline u32 qca_dram_tras_lat(void);
1638 #endif /* !__ASSEMBLY__ */
1641 * Read, write, set and clear macros
1643 #define qca_soc_reg_read(_addr) *(volatile unsigned int *)(KSEG1ADDR(_addr))
1644 #define qca_soc_reg_write(_addr, _val) ((*(volatile unsigned int *)KSEG1ADDR(_addr)) = (_val))
1646 #define qca_soc_reg_read_set(_addr, _mask) \
1647 qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) | (_mask)))
1649 #define qca_soc_reg_read_clear(_addr, _mask) \
1650 qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) & ~(_mask)))
1652 #endif /* _QCA_SOC_COMMON_H_ */