2 * Qualcomm/Atheros Wireless SOC common registers definitions
4 * Copyright (C) 2014 Piotr Dymacz <piotr@dymacz.pl>
5 * Copyright (C) 2008-2010 Atheros Communications Inc.
8 * Linux/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
10 * SPDX-License-Identifier:GPL-2.0
13 #ifndef _QCA_SOC_COMMON_H_
14 #define _QCA_SOC_COMMON_H_
16 #include <soc/soc_common.h>
21 #define QCA_APB_BASE_REG 0x18000000
22 #define QCA_FLASH_BASE_REG 0x1F000000
27 #define QCA_DDR_CTRL_BASE_REG QCA_APB_BASE_REG + 0x00000000
29 #if (SOC_TYPE & QCA_AR933X_SOC)
30 #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000
32 #define QCA_LSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000
33 #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00500000
36 #define QCA_USB_CFG_BASE_REG QCA_APB_BASE_REG + 0x00030000
37 #define QCA_GPIO_BASE_REG QCA_APB_BASE_REG + 0x00040000
38 #define QCA_PLL_BASE_REG QCA_APB_BASE_REG + 0x00050000
39 #define QCA_RST_BASE_REG QCA_APB_BASE_REG + 0x00060000
40 #define QCA_GMAC_BASE_REG QCA_APB_BASE_REG + 0x00070000
41 #define QCA_RTC_BASE_REG QCA_APB_BASE_REG + 0x00107000
42 #define QCA_PLL_SRIF_BASE_REG QCA_APB_BASE_REG + 0x00116000
44 #if (SOC_TYPE & QCA_AR933X_SOC)
45 #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x00090000
46 #elif (SOC_TYPE & QCA_AR934X_SOC) | \
47 (SOC_TYPE & QCA_AR955X_SOC)
48 #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x000A9000
54 #define QCA_DDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x000
55 #define QCA_DDR_CFG2_REG QCA_DDR_CTRL_BASE_REG + 0x004
56 #define QCA_DDR_MODE_REG QCA_DDR_CTRL_BASE_REG + 0x008
57 #define QCA_DDR_EXTENDED_MODE_REG QCA_DDR_CTRL_BASE_REG + 0x00C
58 #define QCA_DDR_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x010
59 #define QCA_DDR_REFRESH_REG QCA_DDR_CTRL_BASE_REG + 0x014
60 #define QCA_DDR_RD_DATA_THIS_CYCLE_REG QCA_DDR_CTRL_BASE_REG + 0x018
61 #define QCA_DDR_TAP_CTRL_0_REG QCA_DDR_CTRL_BASE_REG + 0x01C
62 #define QCA_DDR_TAP_CTRL_1_REG QCA_DDR_CTRL_BASE_REG + 0x020
64 #if (SOC_TYPE & QCA_AR933X_SOC)
65 #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x07C
66 #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x080
67 #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x084
69 #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x09C
70 #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x0A0
71 #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x0A4
72 #define QCA_DDR_WB_FLUSH_PCIE_REG QCA_DDR_CTRL_BASE_REG + 0x0A8
73 #define QCA_DDR_WB_FLUSH_WMAC_REG QCA_DDR_CTRL_BASE_REG + 0x0AC
74 #define QCA_DDR_WB_FLUSH_SRC1_REG QCA_DDR_CTRL_BASE_REG + 0x0B0
75 #define QCA_DDR_WB_FLUSH_SRC2_REG QCA_DDR_CTRL_BASE_REG + 0x0B4
78 #if (SOC_TYPE & QCA_AR933X_SOC)
79 #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x08C
80 #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x090
81 #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x094
82 #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x098
83 #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x09C
84 #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0A0
85 #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0A4
86 #define QCA_SDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0D8
88 #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0B8
89 #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x0BC
90 #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x0C0
91 #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x0C4
92 #define QCA_DDR_BURST2_REG QCA_DDR_CTRL_BASE_REG + 0x0C8
93 #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x0CC
94 #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0D0
95 #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0D4
96 #define QCA_DDR_CTRL_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x108
97 #define QCA_DDR_SELF_REFRESH_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x110
98 #define QCA_DDR_SELF_REFRESH_TIMER_REG QCA_DDR_CTRL_BASE_REG + 0x114
99 #define QCA_DDR_WMAC_FLUSH_REG QCA_DDR_CTRL_BASE_REG + 0x128
100 #define QCA_DDR_CFG3_REG QCA_DDR_CTRL_BASE_REG + 0x15C
104 * Low-Speed UART registers
106 #define QCA_LSUART_RBR_REG QCA_LSUART_BASE_REG + 0x00
107 #define QCA_LSUART_THR_REG QCA_LSUART_BASE_REG + 0x00
108 #define QCA_LSUART_DLL_REG QCA_LSUART_BASE_REG + 0x00
109 #define QCA_LSUART_DLH_REG QCA_LSUART_BASE_REG + 0x04
110 #define QCA_LSUART_IER_REG QCA_LSUART_BASE_REG + 0x04
111 #define QCA_LSUART_IIR_REG QCA_LSUART_BASE_REG + 0x08
112 #define QCA_LSUART_FCR_REG QCA_LSUART_BASE_REG + 0x08
113 #define QCA_LSUART_LCR_REG QCA_LSUART_BASE_REG + 0x0C
114 #define QCA_LSUART_MCR_REG QCA_LSUART_BASE_REG + 0x10
115 #define QCA_LSUART_LSR_REG QCA_LSUART_BASE_REG + 0x14
116 #define QCA_LSUART_MSR_REG QCA_LSUART_BASE_REG + 0x18
119 * Low-Speed UART registers BIT fields
122 /* RBR register (Receive buffer) */
123 #define QCA_LSUART_RBR_RBR_SHIFT 0
124 #define QCA_LSUART_RBR_RBR_MASK BITS(QCA_LSUART_RBR_RBR_SHIFT, 8)
126 /* THR register (Transmit holding) */
127 #define QCA_LSUART_THR_THR_SHIFT 0
128 #define QCA_LSUART_THR_THR_MASK BITS(QCA_LSUART_THR_THR_SHIFT, 8)
130 /* DLL register (Divisor latch low) */
131 #define QCA_LSUART_DLL_DLL_SHIFT 0
132 #define QCA_LSUART_DLL_DLL_MASK BITS(QCA_LSUART_DLL_DLL_SHIFT, 8)
134 /* DLH register (Divisor latch high) */
135 #define QCA_LSUART_DLH_DLH_SHIFT 0
136 #define QCA_LSUART_DLH_DLH_MASK BITS(QCA_LSUART_DLH_DLH_SHIFT, 8)
138 /* IER register (Interrupt enable) */
139 #define QCA_LSUART_IER_ERBFI_SHIFT 0
140 #define QCA_LSUART_IER_ERBFI_MASK (1 << QCA_LSUART_IER_ERBFI_SHIFT)
141 #define QCA_LSUART_IER_ETBEI_SHIFT 1
142 #define QCA_LSUART_IER_ETBEI_MASK (1 << QCA_LSUART_IER_ETBEI_SHIFT)
143 #define QCA_LSUART_IER_ELSI_SHIFT 2
144 #define QCA_LSUART_IER_ELSI_MASK (1 << QCA_LSUART_IER_ELSI_SHIFT)
145 #define QCA_LSUART_IER_EDDSI_SHIFT 3
146 #define QCA_LSUART_IER_EDDSI_MASK (1 << QCA_LSUART_IER_EDDSI_SHIFT)
148 /* IIR register (Interrupt identity) */
149 #define QCA_LSUART_IIR_IID_SHIFT 0
150 #define QCA_LSUART_IIR_IID_MASK BITS(QCA_LSUART_IIR_IID_SHIFT, 4)
151 #define QCA_LSUART_IIR_FIFO_STATUS_SHIFT 6
152 #define QCA_LSUART_IIR_FIFO_STATUS_MASK BITS(QCA_LSUART_IIR_FIFO_STATUS_SHIFT, 2)
154 /* FCR register (FIFO control) */
155 #define QCA_LSUART_FCR_FIFO_EN_SHIFT 0
156 #define QCA_LSUART_FCR_EDDSI_MASK (1 << QCA_LSUART_FCR_FIFO_EN_SHIFT)
157 #define QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT 1
158 #define QCA_LSUART_FCR_RCVR_FIFO_RST_MASK (1 << QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT)
159 #define QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT 2
160 #define QCA_LSUART_FCR_XMIT_FIFO_RST_MASK (1 << QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT)
161 #define QCA_LSUART_FCR_DMA_MODE_SHIFT 3
162 #define QCA_LSUART_FCR_DMA_MODE_MASK (1 << QCA_LSUART_FCR_DMA_MODE_SHIFT)
163 #define QCA_LSUART_FCR_RCVR_TRIG_SHIFT 6
164 #define QCA_LSUART_FCR_RCVR_TRIG_MASK BITS(QCA_LSUART_FCR_RCVR_TRIG_SHIFT, 2)
166 /* LCR register (Line control) */
167 #define QCA_LSUART_LCR_CLS_SHIFT 0
168 #define QCA_LSUART_LCR_CLS_MASK BITS(QCA_LSUART_LCR_CLS_SHIFT, 2)
169 #define QCA_LSUART_LCR_CLS_5BIT_VAL 0x0
170 #define QCA_LSUART_LCR_CLS_6BIT_VAL 0x1
171 #define QCA_LSUART_LCR_CLS_7BIT_VAL 0x2
172 #define QCA_LSUART_LCR_CLS_8BIT_VAL 0x3
173 #define QCA_LSUART_LCR_STOP_SHIFT 2
174 #define QCA_LSUART_LCR_STOP_MASK (1 << QCA_LSUART_LCR_STOP_SHIFT)
175 #define QCA_LSUART_LCR_PEN_SHIFT 3
176 #define QCA_LSUART_LCR_PEN_MASK (1 << QCA_LSUART_LCR_PEN_SHIFT)
177 #define QCA_LSUART_LCR_EPS_SHIFT 4
178 #define QCA_LSUART_LCR_EPS_MASK (1 << QCA_LSUART_LCR_EPS_SHIFT)
179 #define QCA_LSUART_LCR_BREAK_SHIFT 6
180 #define QCA_LSUART_LCR_BREAK_MASK (1 << QCA_LSUART_LCR_BREAK_SHIFT)
181 #define QCA_LSUART_LCR_DLAB_SHIFT 7
182 #define QCA_LSUART_LCR_DLAB_MASK (1 << QCA_LSUART_LCR_DLAB_SHIFT)
184 /* MCR register (Modem control) */
185 #define QCA_LSUART_MCR_DTR_SHIFT 0
186 #define QCA_LSUART_MCR_DTR_MASK (1 << QCA_LSUART_MCR_DTR_SHIFT)
187 #define QCA_LSUART_MCR_RTS_SHIFT 1
188 #define QCA_LSUART_MCR_RTS_MASK (1 << QCA_LSUART_MCR_RTS_SHIFT)
189 #define QCA_LSUART_MCR_OUT1_SHIFT 2
190 #define QCA_LSUART_MCR_OUT1_MASK (1 << QCA_LSUART_MCR_OUT1_SHIFT)
191 #define QCA_LSUART_MCR_OUT2_SHIFT 3
192 #define QCA_LSUART_MCR_OUT2_MASK (1 << QCA_LSUART_MCR_OUT2_SHIFT)
193 #define QCA_LSUART_MCR_LOOPBACK_SHIFT 5
194 #define QCA_LSUART_MCR_LOOPBACK_MASK (1 << QCA_LSUART_MCR_LOOPBACK_SHIFT)
196 /* LSR register (Line status) */
197 #define QCA_LSUART_LSR_DR_SHIFT 0
198 #define QCA_LSUART_LSR_DR_MASK (1 << QCA_LSUART_LSR_DR_SHIFT)
199 #define QCA_LSUART_LSR_OE_SHIFT 1
200 #define QCA_LSUART_LSR_OE_MASK (1 << QCA_LSUART_LSR_OE_SHIFT)
201 #define QCA_LSUART_LSR_PE_SHIFT 2
202 #define QCA_LSUART_LSR_PE_MASK (1 << QCA_LSUART_LSR_PE_SHIFT)
203 #define QCA_LSUART_LSR_FE_SHIFT 3
204 #define QCA_LSUART_LSR_FE_MASK (1 << QCA_LSUART_LSR_FE_SHIFT)
205 #define QCA_LSUART_LSR_BI_SHIFT 4
206 #define QCA_LSUART_LSR_BI_MASK (1 << QCA_LSUART_LSR_BI_SHIFT)
207 #define QCA_LSUART_LSR_THRE_SHIFT 5
208 #define QCA_LSUART_LSR_THRE_MASK (1 << QCA_LSUART_LSR_THRE_SHIFT)
209 #define QCA_LSUART_LSR_TEMT_SHIFT 6
210 #define QCA_LSUART_LSR_TEMT_MASK (1 << QCA_LSUART_LSR_TEMT_SHIFT)
211 #define QCA_LSUART_LSR_FERR_SHIFT 7
212 #define QCA_LSUART_LSR_FERR_MASK (1 << QCA_LSUART_LSR_FERR_SHIFT)
214 /* MCR register (Modem status) */
215 #define QCA_LSUART_MCR_DCTS_SHIFT 0
216 #define QCA_LSUART_MCR_DCTS_MASK (1 << QCA_LSUART_MCR_DCTS_SHIFT)
217 #define QCA_LSUART_MCR_DDSR_SHIFT 1
218 #define QCA_LSUART_MCR_DDSR_MASK (1 << QCA_LSUART_MCR_DDSR_SHIFT)
219 #define QCA_LSUART_MCR_TERI_SHIFT 2
220 #define QCA_LSUART_MCR_TERI_MASK (1 << QCA_LSUART_MCR_TERI_SHIFT)
221 #define QCA_LSUART_MCR_DDCD_SHIFT 3
222 #define QCA_LSUART_MCR_DDCD_MASK (1 << QCA_LSUART_MCR_DDCD_SHIFT)
223 #define QCA_LSUART_MCR_CTS_SHIFT 4
224 #define QCA_LSUART_MCR_CTS_MASK (1 << QCA_LSUART_MCR_CTS_SHIFT)
225 #define QCA_LSUART_MCR_DSR_SHIFT 5
226 #define QCA_LSUART_MCR_DSR_MASK (1 << QCA_LSUART_MCR_DSR_SHIFT)
227 #define QCA_LSUART_MCR_RI_SHIFT 6
228 #define QCA_LSUART_MCR_RI_MASK (1 << QCA_LSUART_MCR_RI_SHIFT)
229 #define QCA_LSUART_MCR_DCD_SHIFT 7
230 #define QCA_LSUART_MCR_DCD_MASK (1 << QCA_LSUART_MCR_DCD_SHIFT)
233 * High-Speed UART registers
235 #define QCA_HSUART_DATA_REG QCA_HSUART_BASE_REG + 0x00
236 #define QCA_HSUART_CS_REG QCA_HSUART_BASE_REG + 0x04
237 #define QCA_HSUART_CLK_REG QCA_HSUART_BASE_REG + 0x08
238 #define QCA_HSUART_INT_REG QCA_HSUART_BASE_REG + 0x0C
239 #define QCA_HSUART_INT_EN_REG QCA_HSUART_BASE_REG + 0x10
242 * High-Speed UART registers BIT fields
245 /* UART_DATA register (UART transmit and RX FIFO interface ) */
246 #define QCA_HSUART_DATA_TX_RX_DATA_SHIFT 0
247 #define QCA_HSUART_DATA_TX_RX_DATA_MASK BITS(QCA_HSUART_DATA_TX_RX_DATA_SHIFT, 8)
248 #define QCA_HSUART_DATA_RX_CSR_SHIFT 8
249 #define QCA_HSUART_DATA_RX_CSR_MASK (1 << QCA_HSUART_DATA_RX_CSR_SHIFT)
250 #define QCA_HSUART_DATA_TX_CSR_SHIFT 9
251 #define QCA_HSUART_DATA_TX_CSR_MASK (1 << QCA_HSUART_DATA_TX_CSR_SHIFT)
253 /* UART_CS register (UART configuration and status) */
254 #define QCA_HSUART_CS_PAR_MODE_SHIFT 0
255 #define QCA_HSUART_CS_PAR_MODE_MASK BITS(QCA_HSUART_CS_PAR_MODE_SHIFT, 2)
256 #define QCA_HSUART_CS_PAR_MODE_NO_VAL 0x0
257 #define QCA_HSUART_CS_PAR_MODE_ODD_VAL 0x2
258 #define QCA_HSUART_CS_PAR_MODE_OVEN_VAL 0x3
259 #define QCA_HSUART_CS_IFACE_MODE_SHIFT 2
260 #define QCA_HSUART_CS_IFACE_MODE_MASK BITS(QCA_HSUART_CS_IFACE_MODE_SHIFT, 2)
261 #define QCA_HSUART_CS_IFACE_MODE_DISABLE_VAL 0x0
262 #define QCA_HSUART_CS_IFACE_MODE_DTE_VAL 0x1
263 #define QCA_HSUART_CS_IFACE_MODE_DCE_VAL 0x2
264 #define QCA_HSUART_CS_FLOW_MODE_SHIFT 4
265 #define QCA_HSUART_CS_FLOW_MODE_MASK BITS(QCA_HSUART_CS_FLOW_MODE_SHIFT, 2)
266 #define QCA_HSUART_CS_FLOW_MODE_NO_VAL 0x0
267 #define QCA_HSUART_CS_FLOW_MODE_HW_VAL 0x2
268 #define QCA_HSUART_CS_FLOW_MODE_INV_VAL 0x3
269 #define QCA_HSUART_CS_DMA_EN_SHIFT 6
270 #define QCA_HSUART_CS_DMA_EN_MASK (1 << QCA_HSUART_CS_DMA_EN_SHIFT)
271 #define QCA_HSUART_CS_RX_READY_ORIDE_SHIFT 7
272 #define QCA_HSUART_CS_RX_READY_ORIDE_MASK (1 << QCA_HSUART_CS_RX_READY_ORIDE_SHIFT)
273 #define QCA_HSUART_CS_TX_READY_ORIDE_SHIFT 8
274 #define QCA_HSUART_CS_TX_READY_ORIDE_MASK (1 << QCA_HSUART_CS_TX_READY_ORIDE_SHIFT)
275 #define QCA_HSUART_CS_TX_READY_SHIFT 9
276 #define QCA_HSUART_CS_TX_READY_MASK (1 << QCA_HSUART_CS_TX_READY_SHIFT)
277 #define QCA_HSUART_CS_RX_BREAK_SHIFT 10
278 #define QCA_HSUART_CS_RX_BREAK_MASK (1 << QCA_HSUART_CS_RX_BREAK_SHIFT)
279 #define QCA_HSUART_CS_TX_BREAK_SHIFT 11
280 #define QCA_HSUART_CS_TX_BREAK_MASK (1 << QCA_HSUART_CS_TX_BREAK_SHIFT)
281 #define QCA_HSUART_CS_HOST_INT_SHIFT 12
282 #define QCA_HSUART_CS_HOST_INT_MASK (1 << QCA_HSUART_CS_HOST_INT_SHIFT)
283 #define QCA_HSUART_CS_HOST_INT_EN_SHIFT 13
284 #define QCA_HSUART_CS_HOST_INT_EN_MASK (1 << QCA_HSUART_CS_HOST_INT_EN_SHIFT)
285 #define QCA_HSUART_CS_TX_BUSY_SHIFT 14
286 #define QCA_HSUART_CS_TX_BUSY_MASK (1 << QCA_HSUART_CS_TX_BUSY_SHIFT)
287 #define QCA_HSUART_CS_RX_BUSY_SHIFT 15
288 #define QCA_HSUART_CS_RX_BUSY_MASK (1 << QCA_HSUART_CS_RX_BUSY_SHIFT)
290 /* UART_CLOCK register (UART clock) */
291 #define QCA_HSUART_CLK_STEP_SHIFT 0
292 #define QCA_HSUART_CLK_STEP_MASK BITS(QCA_HSUART_CLK_STEP_SHIFT, 16)
293 #define QCA_HSUART_CLK_STEP_MAX_VAL 0x3333
294 #define QCA_HSUART_CLK_SCALE_SHIFT 16
295 #define QCA_HSUART_CLK_SCALE_MASK BITS(QCA_HSUART_CLK_SCALE_SHIFT, 8)
296 #define QCA_HSUART_CLK_SCALE_MAX_VAL 0xFF
298 /* UART_INT register (UART interrupt/control status) */
299 #define QCA_HSUART_INT_RX_VALID_SHIFT 0
300 #define QCA_HSUART_INT_RX_VALID_MASK (1 << QCA_HSUART_INT_RX_VALID_SHIFT)
301 #define QCA_HSUART_INT_TX_READY_SHIFT 1
302 #define QCA_HSUART_INT_TX_READY_MASK (1 << QCA_HSUART_INT_TX_READY_SHIFT)
303 #define QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT 2
304 #define QCA_HSUART_INT_RX_FRAMING_ERR_MASK (1 << QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT)
305 #define QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT 3
306 #define QCA_HSUART_INT_RX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT)
307 #define QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT 4
308 #define QCA_HSUART_INT_TX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT)
309 #define QCA_HSUART_INT_RX_PARITY_ERR_SHIFT 5
310 #define QCA_HSUART_INT_RX_PARITY_ERR_MASK (1 << QCA_HSUART_INT_RX_PARITY_ERR_SHIFT)
311 #define QCA_HSUART_INT_RX_BREAK_ON_SHIFT 6
312 #define QCA_HSUART_INT_RX_BREAK_ON_MASK (1 << QCA_HSUART_INT_RX_BREAK_ON_SHIFT)
313 #define QCA_HSUART_INT_RX_BREAK_OFF_SHIFT 7
314 #define QCA_HSUART_INT_RX_BREAK_OFF_MASK (1 << QCA_HSUART_INT_RX_BREAK_OFF_SHIFT)
315 #define QCA_HSUART_INT_RX_FULL_SHIFT 8
316 #define QCA_HSUART_INT_RX_FULL_MASK (1 << QCA_HSUART_INT_RX_FULL_SHIFT)
317 #define QCA_HSUART_INT_TX_EMPTY_SHIFT 9
318 #define QCA_HSUART_INT_TX_EMPTY_MASK (1 << QCA_HSUART_INT_TX_EMPTY_SHIFT)
320 /* UART_INT_EN register (UART interrupt enable) */
321 #define QCA_HSUART_INT_EN_RX_VALID_SHIFT 0
322 #define QCA_HSUART_INT_EN_RX_VALID_MASK (1 << QCA_HSUART_INT_EN_RX_VALID_SHIFT)
323 #define QCA_HSUART_INT_EN_TX_READY_SHIFT 1
324 #define QCA_HSUART_INT_EN_TX_READY_MASK (1 << QCA_HSUART_INT_EN_TX_READY_SHIFT)
325 #define QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT 2
326 #define QCA_HSUART_INT_EN_RX_FRAMING_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT)
327 #define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT 3
328 #define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT)
329 #define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT 4
330 #define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT)
331 #define QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT 5
332 #define QCA_HSUART_INT_EN_RX_PARITY_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT)
333 #define QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT 6
334 #define QCA_HSUART_INT_EN_RX_BREAK_ON_MASK (1 << QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT)
335 #define QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT 7
336 #define QCA_HSUART_INT_EN_RX_BREAK_OFF_MASK (1 << QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT)
337 #define QCA_HSUART_INT_EN_RX_FULL_SHIFT 8
338 #define QCA_HSUART_INT_EN_RX_FULL_MASK (1 << QCA_HSUART_INT_EN_RX_FULL_SHIFT)
339 #define QCA_HSUART_INT_EN_TX_EMPTY_SHIFT 9
340 #define QCA_HSUART_INT_EN_TX_EMPTY_MASK (1 << QCA_HSUART_INT_EN_TX_EMPTY_SHIFT)
346 #if (SOC_TYPE & QCA_AR933X_SOC)
347 #define QCA_GPIO_COUNT 30
348 #elif (SOC_TYPE & QCA_AR934X_SOC)
349 #define QCA_GPIO_COUNT 23
350 #elif (SOC_TYPE & QCA_QCA953X_SOC)
351 #define QCA_GPIO_COUNT 18
352 #elif (SOC_TYPE & QCA_QCA955X_SOC)
353 #define QCA_GPIO_COUNT 24
356 #define QCA_GPIO_OE_REG QCA_GPIO_BASE_REG + 0x00
357 #define QCA_GPIO_IN_REG QCA_GPIO_BASE_REG + 0x04
358 #define QCA_GPIO_OUT_REG QCA_GPIO_BASE_REG + 0x08
359 #define QCA_GPIO_SET_REG QCA_GPIO_BASE_REG + 0x0C
360 #define QCA_GPIO_CLEAR_REG QCA_GPIO_BASE_REG + 0x10
361 #define QCA_GPIO_INT_EN_REG QCA_GPIO_BASE_REG + 0x14
362 #define QCA_GPIO_INT_TYPE_REG QCA_GPIO_BASE_REG + 0x18
363 #define QCA_GPIO_INT_POLARITY_REG QCA_GPIO_BASE_REG + 0x1C
364 #define QCA_GPIO_INT_PENDING_REG QCA_GPIO_BASE_REG + 0x20
365 #define QCA_GPIO_INT_MASK_REG QCA_GPIO_BASE_REG + 0x24
367 #if (SOC_TYPE & QCA_AR933X_SOC)
368 #define QCA_GPIO_FUNC_1_REG QCA_GPIO_BASE_REG + 0x28
369 #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x2C
370 #define QCA_GPIO_FUNC_2_REG QCA_GPIO_BASE_REG + 0x30
371 #define QCA_GPIO_WLAN_MUX_SET0_REG QCA_GPIO_BASE_REG + 0x34
372 #define QCA_GPIO_WLAN_MUX_SET1_REG QCA_GPIO_BASE_REG + 0x38
373 #define QCA_GPIO_WLAN_MUX_SET2_REG QCA_GPIO_BASE_REG + 0x3C
374 #define QCA_GPIO_WLAN_MUX_SET3_REG QCA_GPIO_BASE_REG + 0x40
376 #if (SOC_TYPE & QCA_QCA955X_SOC)
377 #define QCA_GPIO_SPARE_BITS_REG QCA_GPIO_BASE_REG + 0x28
379 #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x28
382 #define QCA_GPIO_OUT_FUNC0_REG QCA_GPIO_BASE_REG + 0x2C
383 #define QCA_GPIO_OUT_FUNC1_REG QCA_GPIO_BASE_REG + 0x30
384 #define QCA_GPIO_OUT_FUNC2_REG QCA_GPIO_BASE_REG + 0x34
385 #define QCA_GPIO_OUT_FUNC3_REG QCA_GPIO_BASE_REG + 0x38
386 #define QCA_GPIO_OUT_FUNC4_REG QCA_GPIO_BASE_REG + 0x3C
387 #define QCA_GPIO_OUT_FUNC5_REG QCA_GPIO_BASE_REG + 0x40
388 #define QCA_GPIO_IN_EN0_REG QCA_GPIO_BASE_REG + 0x44
389 #define QCA_GPIO_IN_EN1_REG QCA_GPIO_BASE_REG + 0x48
390 #define QCA_GPIO_IN_EN2_REG QCA_GPIO_BASE_REG + 0x4C
391 #define QCA_GPIO_IN_EN3_REG QCA_GPIO_BASE_REG + 0x50
392 #define QCA_GPIO_IN_EN4_REG QCA_GPIO_BASE_REG + 0x54
393 #define QCA_GPIO_IN_EN9_REG QCA_GPIO_BASE_REG + 0x68
394 #define QCA_GPIO_FUNC_REG QCA_GPIO_BASE_REG + 0x6C
398 * GPIO registers BIT fields
401 /* GPIO_FUNCTION_1/2 register (GPIO function) */
402 #if (SOC_TYPE & QCA_AR933X_SOC)
403 #define QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT 0
404 #define QCA_GPIO_FUNC_1_JTAG_DIS_MASK (1 << QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT)
405 #define QCA_GPIO_FUNC_1_UART_EN_SHIFT 1
406 #define QCA_GPIO_FUNC_1_UART_EN_MASK (1 << QCA_GPIO_FUNC_1_UART_EN_SHIFT)
407 #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT 2
408 #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_MASK (1 << QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT)
409 #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT 3
410 #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT)
411 #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT 4
412 #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT)
413 #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT 5
414 #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT)
415 #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT 6
416 #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT)
417 #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT 7
418 #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT)
419 #define QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT 13
420 #define QCA_GPIO_FUNC_1_SPI_CS_EN1_MASK (1 << QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT)
421 #define QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT 14
422 #define QCA_GPIO_FUNC_1_SPI_CS_EN2_MASK (1 << QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT)
423 #define QCA_GPIO_FUNC_1_SPI_EN_SHIFT 18
424 #define QCA_GPIO_FUNC_1_SPI_EN_MASK (1 << QCA_GPIO_FUNC_1_SPI_EN_SHIFT)
425 #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT 23
426 #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT)
427 #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT 24
428 #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT)
429 #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT 25
430 #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT)
431 #define QCA_GPIO_FUNC_1_I2S_EN_SHIFT 26
432 #define QCA_GPIO_FUNC_1_I2S_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_EN_SHIFT)
433 #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT 27
434 #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT)
435 #define QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT 29
436 #define QCA_GPIO_FUNC_1_I2S_22_18_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT)
437 #define QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT 30
438 #define QCA_GPIO_FUNC_1_SPDIF_EN_MASK (1 << QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT)
439 #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT 31
440 #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_MASK (1 << QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT)
442 #define QCA_GPIO_FUNC_2_MIC_DIS_SHIFT 0
443 #define QCA_GPIO_FUNC_2_MIC_DIS_MASK (1 << QCA_GPIO_FUNC_2_MIC_DIS_SHIFT)
444 #define QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT 1
445 #define QCA_GPIO_FUNC_2_I2S_ON_LED_MASK (1 << QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT)
446 #define QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT 2
447 #define QCA_GPIO_FUNC_2_SPDIF_ON23_MASK (1 << QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT)
448 #define QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT 3
449 #define QCA_GPIO_FUNC_2_I2SCK_ON1_MASK (1 << QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT)
450 #define QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT 4
451 #define QCA_GPIO_FUNC_2_I2SWS_ON0_MASK (1 << QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT)
452 #define QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT 5
453 #define QCA_GPIO_FUNC_2_I2SSD_ON12_MASK (1 << QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT)
454 #define QCA_GPIO_FUNC_2_WPS_DIS_SHIFT 8
455 #define QCA_GPIO_FUNC_2_WPS_DIS_MASK (1 << QCA_GPIO_FUNC_2_WPS_DIS_SHIFT)
456 #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT 9
457 #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_MASK (1 << QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT)
458 #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT 10
459 #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_MASK (1 << QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT)
460 #define QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT 11
461 #define QCA_GPIO_FUNC_2_USB_LED_ON1_MASK (1 << QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT)
462 #define QCA_GPIO_FUNC_2_LNA_ON28_SHIFT 12
463 #define QCA_GPIO_FUNC_2_LNA_ON28_MASK (1 << QCA_GPIO_FUNC_2_LNA_ON28_SHIFT)
464 #define QCA_GPIO_FUNC_2_SLIC_EN_SHIFT 13
465 #define QCA_GPIO_FUNC_2_SLIC_EN_MASK (1 << QCA_GPIO_FUNC_2_SLIC_EN_SHIFT)
466 #define QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT 14
467 #define QCA_GPIO_FUNC_2_SLIC_ON18_22_MASK (1 << QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT)
468 #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT 15
469 #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_MASK (1 << QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT)
470 #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT 16
471 #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_MASK BITS(QCA_GPIO_FUNC_2__SHIFT, 3)
477 #define QCA_GPIO_OUT_FUNCX_GPIOX_EN_SHIFT(_gpio) ((_gpio % 4) * 8)
478 #define QCA_GPIO_OUT_FUNCX_GPIOX_EN_MASK(_gpio) BIT(((_gpio % 4) * 8), 8)
480 #define QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT 0
481 #define QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT 0
482 #define QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT 0
483 #define QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT 0
484 #define QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT 0
485 #define QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT 0
486 #define QCA_GPIO_OUT_FUNCX_GPIO0_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT, 8)
487 #define QCA_GPIO_OUT_FUNCX_GPIO4_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT, 8)
488 #define QCA_GPIO_OUT_FUNCX_GPIO8_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT, 8)
489 #define QCA_GPIO_OUT_FUNCX_GPIO12_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT, 8)
490 #define QCA_GPIO_OUT_FUNCX_GPIO16_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT, 8)
491 #define QCA_GPIO_OUT_FUNCX_GPIO20_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT, 8)
493 #define QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT 8
494 #define QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT 8
495 #define QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT 8
496 #define QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT 8
497 #define QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT 8
498 #define QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT 8
499 #define QCA_GPIO_OUT_FUNCX_GPIO1_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT, 8)
500 #define QCA_GPIO_OUT_FUNCX_GPIO5_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT, 8)
501 #define QCA_GPIO_OUT_FUNCX_GPIO9_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT, 8)
502 #define QCA_GPIO_OUT_FUNCX_GPIO13_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT, 8)
503 #define QCA_GPIO_OUT_FUNCX_GPIO17_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT, 8)
504 #define QCA_GPIO_OUT_FUNCX_GPIO21_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT, 8)
506 #define QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT 16
507 #define QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT 16
508 #define QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT 16
509 #define QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT 16
510 #define QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT 16
511 #define QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT 16
512 #define QCA_GPIO_OUT_FUNCX_GPIO2_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT, 8)
513 #define QCA_GPIO_OUT_FUNCX_GPIO6_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT, 8)
514 #define QCA_GPIO_OUT_FUNCX_GPIO10_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT, 8)
515 #define QCA_GPIO_OUT_FUNCX_GPIO14_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT, 8)
516 #define QCA_GPIO_OUT_FUNCX_GPIO18_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT, 8)
517 #define QCA_GPIO_OUT_FUNCX_GPIO22_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT, 8)
519 #define QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT 24
520 #define QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT 24
521 #define QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT 24
522 #define QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT 24
523 #define QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT 24
524 #define QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT 24
525 #define QCA_GPIO_OUT_FUNCX_GPIO3_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT, 8)
526 #define QCA_GPIO_OUT_FUNCX_GPIO7_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT, 8)
527 #define QCA_GPIO_OUT_FUNCX_GPIO11_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT, 8)
528 #define QCA_GPIO_OUT_FUNCX_GPIO15_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT, 8)
529 #define QCA_GPIO_OUT_FUNCX_GPIO19_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT, 8)
530 #define QCA_GPIO_OUT_FUNCX_GPIO23_EN_MASK BITS(QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT, 8)
532 /* GPIO output select values (for MUX) */
533 #define QCA_GPIO_OUT_MUX_GPIO_VAL 0
534 #define QCA_GPIO_OUT_MUX_MII_EXT_MDI_VAL 1
535 #define QCA_GPIO_OUT_MUX_SYS_RST_L_VAL 1
536 #define QCA_GPIO_OUT_MUX_NAND_CS0_VAL 1
537 #define QCA_GPIO_OUT_MUX_BOOT_RXT_MDI_VAL 2
538 #define QCA_GPIO_OUT_MUX_SPI_CS0_VAL 9
540 /* 5-port ethernet switch activity LEDs */
541 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN1_VAL 26
542 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN2_VAL 27
543 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN3_VAL 28
544 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN4_VAL 29
545 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN5_VAL 30
547 /* 5-port ethernet switch collision detect LEDs */
548 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN1_VAL 31
549 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN2_VAL 32
550 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN3_VAL 33
551 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN4_VAL 34
552 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN5_VAL 35
554 /* 5-port ethernet switch full/half duplex LEDs */
555 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN1_VAL 36
556 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN2_VAL 37
557 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN3_VAL 38
558 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN4_VAL 39
559 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN5_VAL 40
561 /* 5-port ethernet switch link indicator LEDs */
562 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK1_VAL 41
563 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK2_VAL 42
564 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK3_VAL 43
565 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK4_VAL 44
566 #define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK5_VAL 45
568 #if (SOC_TYPE & QCA_AR934X_SOC)
569 #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL 4
570 #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL 5
571 #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL 6
572 #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL 7
573 #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL 8
574 #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL 10
575 #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL 11
576 #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL 12
577 #define QCA_GPIO_OUT_MUX_I2S_WS_VAL 13
578 #define QCA_GPIO_OUT_MUX_I2S_SD_VAL 14
579 #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL 15
580 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 16
581 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 17
582 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 18
583 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 19
584 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 20
585 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 21
586 #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL 22
587 #define QCA_GPIO_OUT_MUX_CLK_OBS7_VAL 23
588 #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL 24
589 #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL 25
590 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 46
591 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 47
592 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 48
593 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL 49
594 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 50
595 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 51
596 #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL 72
597 #define QCA_GPIO_OUT_MUX_BT_ANT_VAL 73
598 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 74
599 #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL 78
600 #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL_VAL 79
601 #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL_VAL 80
602 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 84
603 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 87
605 #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL 3
606 #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL 4
607 #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL 5
608 #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL 8
609 #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL 10
610 #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL 11
611 #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL 12
612 #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL 13
613 #define QCA_GPIO_OUT_MUX_I2S_WS_VAL 14
614 #define QCA_GPIO_OUT_MUX_I2S_SD_VAL 15
615 #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL 16
616 #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL 17
617 #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL 18
618 #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL 19
619 #define QCA_GPIO_OUT_MUX_HSUART_RXD_VAL 20 /* TODO: RXD is INPUT, mistake in QCA9558 datasheet? */
620 #define QCA_GPIO_OUT_MUX_HSUART_CTS_VAL 21 /* TODO: CTS is INPUT, mistake in QCA9558 datasheet? */
621 #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL 22
622 #define QCA_GPIO_OUT_MUX_SRIF_OUT_VAL 23
624 #if (SOC_TYPE & QCA_QCA955X_SOC)
625 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_VAL 24
626 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_VAL 25
627 #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_VAL 26
628 #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_VAL 27
629 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_INV_VAL 28
630 #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_INV_VAL 29
631 #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_INV_VAL 30
632 #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_INV_VAL 31
633 #define QCA_GPIO_OUT_MUX_GE1_MII_MDO_VAL 32
634 #define QCA_GPIO_OUT_MUX_GE1_MII_MDC_VAL 33
635 #define QCA_GPIO_OUT_MUX_SWCOM2_VAL 38
636 #define QCA_GPIO_OUT_MUX_SWCOM3_VAL 39
637 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL 40
638 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL 41
639 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 42
640 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 43
641 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 44
642 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL 45
643 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 46
644 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 47
645 #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL 68
646 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 70
647 #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_STROBE_VAL 71
648 #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_DATA_VAL 72
649 #define QCA_GPIO_OUT_MUX_NAND_CS1_VAL 73
650 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 74
651 #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL 75
652 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 76
653 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_EP_VAL 77
654 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL 78
655 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 79
656 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 80
657 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 81
658 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 82
659 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 83
660 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 84
663 #if (SOC_TYPE & QCA_QCA953X_SOC)
664 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL 48
665 #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL 49
666 #define QCA_GPIO_OUT_MUX_ATT_LED_VAL 50
667 #define QCA_GPIO_OUT_MUX_PWR_LED_VAL 51
668 #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL 52
669 #define QCA_GPIO_OUT_MUX_RX_CLEAR_INT_VAL 53
670 #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL 54
671 #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL 55
672 #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL 78
673 #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL 86
674 #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL 88
675 #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL 89
676 #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL 90
677 #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL 91
678 #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL 92
679 #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL 93
680 #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL 94
681 #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL 95
682 #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL 96
686 /* GPIO_IN_ENABLE0 register (GPIO in signals 0) */
687 #define QCA_GPIO_IN_EN0_SPI_MISO_SHIFT 0
688 #define QCA_GPIO_IN_EN0_SPI_MISO_MASK BITS(QCA_GPIO_IN_EN0_SPI_MISO_SHIFT, 8)
689 #define QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT 8
690 #define QCA_GPIO_IN_EN0_LSUART_RXD_MASK BITS(QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT ,8)
692 /* GPIO_IN_ENABLE1 register (GPIO in signals 1) */
693 #define QCA_GPIO_IN_EN1_I2S_WS_SHIFT 0
694 #define QCA_GPIO_IN_EN1_I2S_WS_MASK BITS(QCA_GPIO_IN_EN1_I2S_WS_SHIFT ,8)
695 #define QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT 8
696 #define QCA_GPIO_IN_EN1_I2S_MIC_SD_MASK BITS(QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT ,8)
697 #define QCA_GPIO_IN_EN1_I2S_CLK_SHIFT 16
698 #define QCA_GPIO_IN_EN1_I2S_CLK_MASK BITS(QCA_GPIO_IN_EN1_I2S_CLK_SHIFT ,8)
699 #define QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT 24
700 #define QCA_GPIO_IN_EN1_I2S_MCLK_MASK BITS(QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT ,8)
702 /* GPIO_IN_ENABLE9 register (GPIO in signals 9) */
703 #define QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT 16
704 #define QCA_GPIO_IN_EN9_HSUART_RXD_MASK BITS(QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT ,8)
705 #define QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT 24
706 #define QCA_GPIO_IN_EN9_HSUART_CTS_MASK BITS(QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT ,8)
708 /* GPIO_FUNCTION register (GPIO function) */
709 #define QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT 0
710 #define QCA_GPIO_FUNC_GPIO_SRIF_EN_MASK (1 << QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT)
711 #define QCA_GPIO_FUNC_JTAG_DIS_SHIFT 1
712 #define QCA_GPIO_FUNC_JTAG_DIS_MASK (1 << QCA_GPIO_FUNC_JTAG_DIS_SHIFT)
713 #define QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT 2
714 #define QCA_GPIO_FUNC_CLK_OBS0_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT)
715 #define QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT 3
716 #define QCA_GPIO_FUNC_CLK_OBS1_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT)
717 #define QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT 4
718 #define QCA_GPIO_FUNC_CLK_OBS2_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT)
719 #define QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT 5
720 #define QCA_GPIO_FUNC_CLK_OBS3_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT)
721 #define QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT 6
722 #define QCA_GPIO_FUNC_CLK_OBS4_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT)
723 #define QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT 7
724 #define QCA_GPIO_FUNC_CLK_OBS5_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT)
725 #define QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT 8
726 #define QCA_GPIO_FUNC_CLK_OBS6_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT)
727 #define QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT 9
728 #define QCA_GPIO_FUNC_CLK_OBS7_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT)
731 * PLL control registers
733 #define QCA_PLL_CPU_PLL_CFG_REG QCA_PLL_BASE_REG + 0x00
735 #if (SOC_TYPE & QCA_AR933X_SOC)
736 #define QCA_PLL_CPU_PLL_CFG2_REG QCA_PLL_BASE_REG + 0x04
737 #define QCA_PLL_CPU_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08
738 #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG QCA_PLL_BASE_REG + 0x10
739 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x14
740 #define QCA_PLL_ETHSW_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24
741 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C
742 #define QCA_PLL_USB_SUSPEND_REG QCA_PLL_BASE_REG + 0x40
743 #define QCA_PLL_WLAN_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x44
745 #define QCA_PLL_DDR_PLL_CFG_REG QCA_PLL_BASE_REG + 0x04
746 #define QCA_PLL_CPU_DDR_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08
748 #if (SOC_TYPE & QCA_QCA955X_SOC)
749 #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x0C
750 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x10
751 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x14
752 #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x18
753 #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x1C
754 #define QCA_PLL_SWITCH_CLK_SPARE_REG QCA_PLL_BASE_REG + 0x20
755 #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x24
756 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x28
757 #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x2C
758 #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x30
759 #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x34
760 #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x38
761 #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x40
762 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44
763 #define QCA_PLL_ETH_SGMII_CTRL_REG QCA_PLL_BASE_REG + 0x48
764 #define QCA_PLL_ETH_SGMII_SERDES_REG QCA_PLL_BASE_REG + 0x4C
765 #define QCA_PLL_SLIC_PWM_DIV_REG QCA_PLL_BASE_REG + 0x50
767 #define QCA_PLL_CPU_SYNC_REG QCA_PLL_BASE_REG + 0x0C
768 #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x10
769 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x14
770 #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x18
771 #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x1C
772 #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x20
773 #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24
775 #if (SOC_TYPE & QCA_AR9344_SOC)
776 #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28
778 #define QCA_PLL_CURR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28
781 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C
782 #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x30
783 #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x34
784 #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x38
785 #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x3C
786 #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x40
787 #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44
788 #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x48
793 * PLL control registers BIT fields
796 /* CPU_PLL_CONFIG register (CPU phase lock loop configuration) */
797 #if (SOC_TYPE & QCA_AR933X_SOC)
798 #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0
799 #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 10)
800 #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 10
801 #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
802 #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 16
803 #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
804 #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 21
805 #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK (1 << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)
806 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 23
807 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
809 #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0
810 #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 6)
811 #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 6
812 #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
813 #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 12
814 #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
815 #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 17
816 #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK BITS(QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT, 2)
817 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 19
818 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
821 #define QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT 30
822 #define QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK (1 << QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT)
823 #define QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT 31
824 #define QCA_PLL_CPU_PLL_CFG_UPDATING_MASK (1 << QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT)
826 /* CPU_PLL_CONFIG2 register (CPU phase lock loop configuration, AR933x only) */
827 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT 0
828 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_MASK BITS(QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT, 12)
830 /* CPU_CLOCK_CONTROL register (CPU clock control, AR933x only) */
831 #define QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT 2
832 #define QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK (1 << QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT)
833 #define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT 5
834 #define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT, 2)
835 #define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT 10
836 #define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT, 2)
837 #define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT 15
838 #define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT, 2)
840 /* ETHSW_CLOCK_CONTROL register (Ethernet switch clock control, AR933x only) */
841 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT 3
842 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_MASK (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT)
843 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT 4
844 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_MASK (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT)
846 /* ETH_XMII_CONTROL register (Ethernet XMII control) */
847 #define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT 0
848 #define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT, 8)
849 #define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT 8
850 #define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT, 8)
851 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT 16
852 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT, 8)
853 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT 24
854 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_MASK (1 << QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT)
855 #define QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT 25
856 #define QCA_PLL_ETH_XMII_CTRL_GIGE_MASK (1 << QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT)
857 #define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT 26
858 #define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT, 2)
859 #define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT 28
860 #define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT, 2)
861 #define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT 30
862 #define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_MASK (1 << QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT)
863 #define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT 31
864 #define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_MASK (1 << QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT)
866 /* SUSPEND register (USB suspend, AR933x only) */
867 #define QCA_PLL_USB_SUSPEND_EN_SHIFT 0
868 #define QCA_PLL_USB_SUSPEND_EN_MASK (1 << QCA_PLL_USB_SUSPEND_EN_SHIFT)
869 #define QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT 8
870 #define QCA_PLL_USB_SUSPEND_RESTART_TIME_MASK BITS(QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT, 20)
872 /* WLAN_CLOCK_CONTROL register (WLAN clock control, AR933x only) */
873 #define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT 0
874 #define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT)
875 #define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT 1
876 #define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT)
877 #define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT 2
878 #define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT)
879 #define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT 3
880 #define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT)
881 #define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT 4
882 #define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT)
883 #define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT 8
884 #define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT)
885 #define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT 9
886 #define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT)
887 #define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT 10
888 #define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT)
889 #define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT 12
890 #define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT)
892 /* DDR_PLL_CONFIG register (DDR PLL configuration) */
893 #define QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT 0
894 #define QCA_PLL_DDR_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT, 10)
895 #define QCA_PLL_DDR_PLL_CFG_NINT_SHIFT 10
896 #define QCA_PLL_DDR_PLL_CFG_NINT_MASK BITS(QCA_PLL_DDR_PLL_CFG_NINT_SHIFT, 6)
897 #define QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT 16
898 #define QCA_PLL_DDR_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT, 5)
899 #define QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT 21
900 #define QCA_PLL_DDR_PLL_CFG_RANGE_MASK BITS(QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT, 2)
901 #define QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT 23
902 #define QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT, 3)
903 #define QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT 30
904 #define QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK (1 << QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT)
905 #define QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT 31
906 #define QCA_PLL_DDR_PLL_CFG_UPDATING_MASK (1 << QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT)
908 /* CPU_DDR_CLOCK_CONTROL register (CPU DDR clock control) */
909 #define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT 1
910 #define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT)
911 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT 2
912 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT)
913 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT 3
914 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT)
915 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT 4
916 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT)
917 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
918 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT, 5)
919 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
920 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT, 5)
921 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
922 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT, 5)
923 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT 20
924 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT)
925 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT 21
926 #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT)
927 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT 22
928 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT)
929 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT 23
930 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT)
931 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT 24
932 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT)
934 /* DDR_PLL_DITHER register (DDR PLL dither parameter) */
935 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT 0
936 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT, 10)
937 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT 10
938 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 10)
939 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_SHIFT 20
940 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 7)
941 #define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT 27
942 #define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT, 4)
943 #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT 31
944 #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT)
946 #if (SOC_TYPE & QCA_AR933X_SOC)
947 /* PLL_DITHER_FRAC register (CPU PLL dither FRAC) */
948 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT 0
949 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT, 10)
950 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT 10
951 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT, 10)
952 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT 20
953 #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT, 10)
955 /* PLL_DITHER register (CPU PLL dither) */
956 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 0
957 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 14)
958 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31
959 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT)
961 /* CPU_PLL_DITHER register (CPU PLL dither parameter) */
962 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT 0
963 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 6)
964 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT 6
965 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
966 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 12
967 #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
968 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 18
969 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6)
970 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31
971 #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT)
975 * PLL SRIF registers (not available in AR933x)
977 #define QCA_PLL_SRIF_CPU_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x1C0
978 #define QCA_PLL_SRIF_CPU_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x1C4
979 #define QCA_PLL_SRIF_CPU_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x1C8
980 #define QCA_PLL_SRIF_AUD_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x200
981 #define QCA_PLL_SRIF_AUD_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x204
982 #define QCA_PLL_SRIF_AUD_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x208
983 #define QCA_PLL_SRIF_DDR_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x240
984 #define QCA_PLL_SRIF_DDR_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x244
985 #define QCA_PLL_SRIF_DDR_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x248
986 #define QCA_PLL_SRIF_PCIE_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0xC00
987 #define QCA_PLL_SRIF_PCIE_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0xC04
988 #define QCA_PLL_SRIF_PCIE_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0xC08
991 * PLL SRIF registers BIT fields (not available in AR933x)
994 /* DPLL1 (common for CPU, AUD, DDR and PCIE) */
995 #define QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT 0
996 #define QCA_PLL_SRIF_DPLL1_NFRAC_MASK BITS(QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT, 18)
997 #define QCA_PLL_SRIF_DPLL1_NINT_SHIFT 18
998 #define QCA_PLL_SRIF_DPLL1_NINT_MASK BITS(QCA_PLL_SRIF_DPLL1_NINT_SHIFT, 9)
999 #define QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT 27
1000 #define QCA_PLL_SRIF_DPLL1_REFDIV_MASK BITS(QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT, 5)
1002 /* DPLL2 (common for CPU, AUD, DDR and PCIE) */
1003 #if (SOC_TYPE & QCA_QCA953X_SOC)
1004 #define QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT 0
1005 #define QCA_PLL_SRIF_DPLL2_RST_TEST_MASK (1 << QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT)
1006 #define QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT 1
1007 #define QCA_PLL_SRIF_DPLL2_SEL_CNT_MASK (1 << QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT)
1008 #define QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT 2
1009 #define QCA_PLL_SRIF_DPLL2_TEST_IN_MASK BITS(QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT, 10)
1010 #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT 12
1011 #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_MASK BITS(QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT, 7)
1012 #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 19
1013 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 3)
1014 #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 22
1015 #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
1016 #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT 23
1017 #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_MASK (1 << QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT)
1018 #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT 24
1019 #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_MASK (1 << QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT)
1020 #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 25
1021 #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 4)
1022 #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 29
1023 #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 2)
1024 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 31
1025 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
1027 #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 13
1028 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2)
1029 #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 16
1030 #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
1031 #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 19
1032 #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7)
1033 #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 26
1034 #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KI_SHIFT, 4)
1035 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 30
1036 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
1037 #define QCA_PLL_SRIF_DPLL2_RANGE_SHIFT 31
1038 #define QCA_PLL_SRIF_DPLL2_RANGE_MASK (1 << QCA_PLL_SRIF_DPLL2_RANGE_SHIFT)
1041 /* DPLL3 (common for CPU, AUD, DDR and PCIE) */
1042 #define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT 23
1043 #define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_MASK BITS(QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT, 7)
1046 * Reset control registers
1048 #define QCA_RST_GENERAL_TIMER1_REG QCA_RST_BASE_REG + 0x00
1049 #define QCA_RST_GENERAL_TIMER1_RELOAD_REG QCA_RST_BASE_REG + 0x04
1050 #define QCA_RST_WATCHDOG_TIMER_CTRL_REG QCA_RST_BASE_REG + 0x08
1051 #define QCA_RST_WATCHDOG_TIMER_REG QCA_RST_BASE_REG + 0x0C
1052 #define QCA_RST_MISC_INTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x10
1053 #define QCA_RST_MISC_INTERRUPT_MASK_REG QCA_RST_BASE_REG + 0x14
1054 #define QCA_RST_GLOBALINTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x18
1055 #define QCA_RST_RST_REG QCA_RST_BASE_REG + 0x1C
1056 #define QCA_RST_REVISION_ID_REG QCA_RST_BASE_REG + 0x90
1057 #define QCA_RST_GENERAL_TIMER2_REG QCA_RST_BASE_REG + 0x94
1058 #define QCA_RST_GENERAL_TIMER2_RELOAD_REG QCA_RST_BASE_REG + 0x98
1059 #define QCA_RST_GENERAL_TIMER3_REG QCA_RST_BASE_REG + 0x9C
1060 #define QCA_RST_GENERAL_TIMER3_RELOAD_REG QCA_RST_BASE_REG + 0xA0
1061 #define QCA_RST_GENERAL_TIMER4_REG QCA_RST_BASE_REG + 0xA4
1062 #define QCA_RST_GENERAL_TIMER4_RELOAD_REG QCA_RST_BASE_REG + 0xA8
1064 #if (SOC_TYPE & QCA_AR933X_SOC)
1065 #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xAC
1067 #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xB0
1071 * Reset control registers BIT fields
1074 /* RST_BOOTSTRAP (Reset bootstrap) */
1075 #if (SOC_TYPE & QCA_AR933X_SOC)
1076 #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 0
1078 #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 4
1080 #define QCA_RST_BOOTSTRAP_REF_CLK_MASK (1 << QCA_RST_BOOTSTRAP_REF_CLK_SHIFT)
1081 #define QCA_RST_BOOTSTRAP_REF_CLK_25M_VAL 0x0
1082 #define QCA_RST_BOOTSTRAP_REF_CLK_40M_VAL 0x1
1084 #if (SOC_TYPE & QCA_AR933X_SOC)
1085 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 12
1086 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
1087 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 0
1088 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1
1089 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 2
1090 #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT 16
1091 #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK (1 << QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT)
1092 #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT 17
1093 #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_MASK (1 << QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT)
1094 #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT 18
1095 #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_MASK (1 << QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT)
1097 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 0
1099 /* v2 does not support SDR, but we can read reserved bit and make it universal */
1100 #if (SOC_TYPE & QCA_QCA953X_SOC)
1101 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
1103 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK (1 << QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT)
1106 #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 3
1107 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1
1108 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 0
1112 #define QCA_RST_RESET_I2C_RST_SHIFT 0
1113 #define QCA_RST_RESET_I2C_RST_MASK (1 << QCA_RST_RESET_I2C_RST_SHIFT)
1114 #define QCA_RST_RESET_MBOX_RST_SHIFT 1
1115 #define QCA_RST_RESET_MBOX_RST_MASK (1 << QCA_RST_RESET_MBOX_RST_SHIFT)
1116 #define QCA_RST_RESET_LUT_RST_SHIFT 2
1117 #define QCA_RST_RESET_LUT_RST_MASK (1 << QCA_RST_RESET_LUT_RST_SHIFT)
1118 #define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT 3
1119 #define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_MASK (1 << QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT)
1120 #define QCA_RST_RESET_USB_PHY_RST_SHIFT 4
1121 #define QCA_RST_RESET_USB_PHY_RST_MASK (1 << QCA_RST_RESET_USB_PHY_RST_SHIFT)
1122 #define QCA_RST_RESET_USB_HOST_RST_SHIFT 5
1123 #define QCA_RST_RESET_USB_HOST_RST_MASK (1 << QCA_RST_RESET_USB_HOST_RST_SHIFT)
1125 #if (SOC_TYPE & QCA_AR933X_SOC)
1126 #define QCA_RST_RESET_SLIC_RST_SHIFT 6
1127 #define QCA_RST_RESET_SLIC_RST_MASK (1 << QCA_RST_RESET_SLIC_RST_SHIFT)
1129 #define QCA_RST_RESET_PCIE_RST_SHIFT 6
1130 #define QCA_RST_RESET_PCIE_RST_MASK (1 << QCA_RST_RESET_PCIE_RST_SHIFT)
1131 #define QCA_RST_RESET_SLIC_RST_SHIFT 30
1132 #define QCA_RST_RESET_SLIC_RST_MASK (1 << QCA_RST_RESET_SLIC_RST_SHIFT)
1135 #define QCA_RST_RESET_PCIE_PHY_RST_SHIFT 7
1136 #define QCA_RST_RESET_PCIE_PHY_RST_MASK (1 << QCA_RST_RESET_PCIE_PHY_RST_SHIFT)
1138 #if (SOC_TYPE & QCA_QCA955X_SOC)
1139 #define QCA_RST_RESET_ETH_SGMII_RST_SHIFT 8
1140 #define QCA_RST_RESET_ETH_SGMII_RST_MASK (1 << QCA_RST_RESET_ETH_SGMII_RST_SHIFT)
1142 #define QCA_RST_RESET_ETH_SWITCH_RST_SHIFT 8
1143 #define QCA_RST_RESET_ETH_SWITCH_RST_MASK (1 << QCA_RST_RESET_ETH_SWITCH_RST_SHIFT)
1146 #define QCA_RST_RESET_GE0_MAC_RST_SHIFT 9
1147 #define QCA_RST_RESET_GE0_MAC_RST_MASK (1 << QCA_RST_RESET_GE0_MAC_RST_SHIFT)
1148 #define QCA_RST_RESET_HOST_DMA_INT_SHIFT 10
1149 #define QCA_RST_RESET_HOST_DMA_INT_MASK (1 << QCA_RST_RESET_HOST_DMA_INT_SHIFT)
1151 #if (SOC_TYPE & QCA_AR933X_SOC)
1152 #define QCA_RST_RESET_WLAN_RST_SHIFT 11
1153 #define QCA_RST_RESET_WLAN_RST_MASK (1 << QCA_RST_RESET_WLAN_RST_SHIFT)
1155 #define QCA_RST_RESET_USB_PHY_ARST_SHIFT 11
1156 #define QCA_RST_RESET_USB_PHY_ARST_MASK (1 << QCA_RST_RESET_USB_PHY_ARST_SHIFT)
1159 #if (SOC_TYPE & QCA_AR933X_SOC)
1160 #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 14
1161 #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK (1 << QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
1163 #if (SOC_TYPE & QCA_QCA955X_SOC)
1164 #define QCA_RST_RESET_ETH_SGMII_ARST_SHIFT 12
1165 #define QCA_RST_RESET_ETH_SGMII_ARST_MASK (1 << QCA_RST_RESET_ETH_SGMII_ARST_SHIFT)
1167 #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 12
1168 #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK (1 << QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
1171 #define QCA_RST_RESET_NANDF_RST_SHIFT 14
1172 #define QCA_RST_RESET_NANDF_RST_MASK (1 << QCA_RST_RESET_NANDF_RST_SHIFT)
1175 #define QCA_RST_RESET_GE1_MAC_RST_SHIFT 13
1176 #define QCA_RST_RESET_GE1_MAC_RST_MASK (1 << QCA_RST_RESET_GE1_MAC_RST_SHIFT)
1177 #define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT 15
1178 #define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_MASK (1 << QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT)
1179 #define QCA_RST_RESET_DDR_RST_SHIFT 16
1180 #define QCA_RST_RESET_DDR_RST_MASK (1 << QCA_RST_RESET_DDR_RST_SHIFT)
1181 #define QCA_RST_RESET_HSUART_RST_SHIFT 17
1182 #define QCA_RST_RESET_HSUART_RST_MASK (1 << QCA_RST_RESET_HSUART_RST_SHIFT)
1183 #define QCA_RST_RESET_PCIEEP_RST_SHIFT 18
1184 #define QCA_RST_RESET_PCIEEP_RST_MASK (1 << QCA_RST_RESET_PCIEEP_RST_SHIFT)
1185 #define QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT 19
1186 #define QCA_RST_RESET_HOST_DMA_RST_INT_MASK (1 << QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT)
1187 #define QCA_RST_RESET_CPU_COLD_RST_SHIFT 20
1188 #define QCA_RST_RESET_CPU_COLD_RST_MASK (1 << QCA_RST_RESET_CPU_COLD_RST_SHIFT)
1189 #define QCA_RST_RESET_CPU_NMI_SHIFT 21
1190 #define QCA_RST_RESET_CPU_NMI_MASK (1 << QCA_RST_RESET_CPU_NMI_SHIFT)
1191 #define QCA_RST_RESET_GE0_MDIO_RST_SHIFT 22
1192 #define QCA_RST_RESET_GE0_MDIO_RST_MASK (1 << QCA_RST_RESET_GE0_MDIO_RST_SHIFT)
1193 #define QCA_RST_RESET_GE1_MDIO_RST_SHIFT 23
1194 #define QCA_RST_RESET_GE1_MDIO_RST_MASK (1 << QCA_RST_RESET_GE1_MDIO_RST_SHIFT)
1195 #define QCA_RST_RESET_FULL_CHIP_RST_SHIFT 24
1196 #define QCA_RST_RESET_FULL_CHIP_RST_MASK (1 << QCA_RST_RESET_FULL_CHIP_RST_SHIFT)
1197 #define QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT 25
1198 #define QCA_RST_RESET_CHECKSUM_ACC_RST_MASK (1 << QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT)
1199 #define QCA_RST_RESET_PCIEEP_RST_INT_SHIFT 26
1200 #define QCA_RST_RESET_PCIEEP_RST_INT_MASK (1 << QCA_RST_RESET_PCIEEP_RST_INT_SHIFT)
1201 #define QCA_RST_RESET_RTC_RST_SHIFT 27
1202 #define QCA_RST_RESET_RTC_RST_MASK (1 << QCA_RST_RESET_RTC_RST_SHIFT)
1203 #define QCA_RST_RESET_EXT_RST_SHIFT 28
1204 #define QCA_RST_RESET_EXT_RST_MASK (1 << QCA_RST_RESET_EXT_RST_SHIFT)
1206 #if (SOC_TYPE & QCA_AR934X_SOC) | \
1207 (SOC_TYPE & QCA_QCA955X_SOC)
1208 #define QCA_RST_RESET_HOST_DMA_RST_SHIFT 29
1209 #define QCA_RST_RESET_HOST_DMA_RST_MASK (1 << QCA_RST_RESET_HOST_DMA_RST_SHIFT)
1211 #define QCA_RST_RESET_USB_EXT_PWR_SHIFT 29
1212 #define QCA_RST_RESET_USB_EXT_PWR_MASK (1 << QCA_RST_RESET_USB_EXT_PWR_SHIFT)
1215 #define QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT 31
1216 #define QCA_RST_RESET_HOST_DMA_RST_STATUS_MASK (1 << QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT)
1218 /* RST_REVISION_ID (Chip revision ID) */
1219 #define QCA_RST_REVISION_ID_MAJOR_SHIFT 4
1220 #define QCA_RST_REVISION_ID_MAJOR_MASK BITS(QCA_RST_REVISION_ID_MAJOR_SHIFT, 12)
1222 #if (SOC_TYPE & QCA_AR933X_SOC)
1223 #define QCA_RST_REVISION_ID_REV_SHIFT 0
1224 #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 2)
1226 #define QCA_RST_REVISION_ID_REV_SHIFT 0
1227 #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 4)
1230 #define QCA_RST_REVISION_ID_MAJOR_AR9330_VAL 0x0110
1231 #define QCA_RST_REVISION_ID_MAJOR_AR9331_VAL 0x1110
1232 #define QCA_RST_REVISION_ID_MAJOR_AR9341_VAL 0x0120
1233 #define QCA_RST_REVISION_ID_MAJOR_AR9344_VAL 0x2120
1234 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL 0x0140
1235 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL 0x0160
1236 #define QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL 0x1130
1241 #define QCA_RTC_RST_CTRL_REG QCA_RTC_BASE_REG + 0x00
1242 #define QCA_RTC_XTAL_CTRL_REG QCA_RTC_BASE_REG + 0x04
1243 #define QCA_RTC_WLAN_PLL_CTRL_REG QCA_RTC_BASE_REG + 0x14
1244 #define QCA_RTC_PLL_SETTLE_REG QCA_RTC_BASE_REG + 0x18
1245 #define QCA_RTC_XTAL_SETTLE_REG QCA_RTC_BASE_REG + 0x1C
1246 #define QCA_RTC_CLK_OUT_REG QCA_RTC_BASE_REG + 0x20
1247 #define QCA_RTC_RST_CAUSE_REG QCA_RTC_BASE_REG + 0x28
1248 #define QCA_RTC_SYS_SLEEP_REG QCA_RTC_BASE_REG + 0x2C
1249 #define QCA_RTC_KEEP_AWAKE_REG QCA_RTC_BASE_REG + 0x34
1250 #define QCA_RTC_DERIVED_RTC_CLK_REG QCA_RTC_BASE_REG + 0x38
1251 #define QCA_RTC_PLL_CTRL2_REG QCA_RTC_BASE_REG + 0x3C
1252 #define QCA_RTC_SYNC_RST_REG QCA_RTC_BASE_REG + 0x40
1253 #define QCA_RTC_SYNC_STATUS_REG QCA_RTC_BASE_REG + 0x44
1254 #define QCA_RTC_SYNC_DERIVED_REG QCA_RTC_BASE_REG + 0x48
1255 #define QCA_RTC_SYNC_FORCE_WAKE_REG QCA_RTC_BASE_REG + 0x4C
1256 #define QCA_RTC_INTERRUPT_CAUSE_REG QCA_RTC_BASE_REG + 0x50
1257 #define QCA_RTC_INTERRUPT_EN_REG QCA_RTC_BASE_REG + 0x54
1258 #define QCA_RTC_INTERRUPT_MASK_REG QCA_RTC_BASE_REG + 0x58
1261 * RTC registers BIT fields
1264 /* RESET_CONTROL register (RTC reset control) */
1265 #define QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT 0
1266 #define QCA_RTC_RST_CTRL_MAC_WARM_RST_MASK (1 << QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT)
1267 #define QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT 1
1268 #define QCA_RTC_RST_CTRL_MAC_COLD_RST_MASK (1 << QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT)
1269 #define QCA_RTC_RST_CTRL_WARM_RST_SHIFT 2
1270 #define QCA_RTC_RST_CTRL_WARM_RST_MASK (1 << QCA_RTC_RST_CTRL_WARM_RST_SHIFT)
1271 #define QCA_RTC_RST_CTRL_COLD_RST_SHIFT 3
1272 #define QCA_RTC_RST_CTRL_COLD_RST_MASK (1 << QCA_RTC_RST_CTRL_COLD_RST_SHIFT)
1274 /* RESET_CAUSE register (Reset cause) */
1275 #define QCA_RTC_RST_CAUSE_LAST_SHIFT 0
1276 #define QCA_RTC_RST_CAUSE_LAST_MASK BITS(QCA_RTC_RST_CAUSE_LAST_SHIFT, 2)
1278 #define QCA_RTC_RST_CAUSE_LAST_HARD_VAL 0
1279 #define QCA_RTC_RST_CAUSE_LAST_COLD_VAL 1
1280 #define QCA_RTC_RST_CAUSE_LAST_WARM_VAL 2
1282 /* RTC_SYNC_REGISTER register (RTC reset, force sleep and force wakeup) */
1283 #define QCA_RTC_SYNC_RST_RESET_SHIFT 0
1284 #define QCA_RTC_SYNC_RST_RESET_MASK (1 << QCA_RTC_SYNC_RST_RESET_SHIFT)
1286 /* RTC_SYNC_STATUS register (RTC sync/sleep status) */
1287 #define QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT 0
1288 #define QCA_RTC_SYNC_STATUS_SHUTDOWN_MASK (1 << QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT)
1289 #define QCA_RTC_SYNC_STATUS_ON_SHIFT 1
1290 #define QCA_RTC_SYNC_STATUS_ON_MASK (1 << QCA_RTC_SYNC_STATUS_ON_SHIFT)
1291 #define QCA_RTC_SYNC_STATUS_SLEEP_SHIFT 2
1292 #define QCA_RTC_SYNC_STATUS_SLEEP_MASK (1 << QCA_RTC_SYNC_STATUS_SLEEP_SHIFT)
1293 #define QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT 3
1294 #define QCA_RTC_SYNC_STATUS_WAKEUP_MASK (1 << QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT)
1295 #define QCA_RTC_SYNC_STATUS_WRESET_SHIFT 4
1296 #define QCA_RTC_SYNC_STATUS_WRESET_MASK (1 << QCA_RTC_SYNC_STATUS_WRESET_SHIFT)
1297 #define QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT 5
1298 #define QCA_RTC_SYNC_STATUS_PLL_CHANGING_MASK (1 << QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT)
1300 /* RTC_SYNC_FORCE_WAKE register (RTC force wake) */
1301 #define QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT 0
1302 #define QCA_RTC_SYNC_FORCE_WAKE_EN_MASK (1 << QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT)
1303 #define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT 1
1304 #define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_MASK (1 << QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT)
1307 * SPI serial flash registers
1309 #define QCA_SPI_FUNC_SEL_REG QCA_FLASH_BASE_REG + 0x00
1310 #define QCA_SPI_CTRL_REG QCA_FLASH_BASE_REG + 0x04
1311 #define QCA_SPI_IO_CTRL_REG QCA_FLASH_BASE_REG + 0x08
1312 #define QCA_SPI_READ_DATA_REG QCA_FLASH_BASE_REG + 0x0C
1313 #define QCA_SPI_SHIFT_DATAOUT_REG QCA_FLASH_BASE_REG + 0x10
1314 #define QCA_SPI_SHIFT_CNT_REG QCA_FLASH_BASE_REG + 0x14
1315 #define QCA_SPI_SHIFT_DATAIN_REG QCA_FLASH_BASE_REG + 0x18
1318 * SPI serial flash registers BIT fields
1321 /* SPI_FUNC_SELECT register (SPI function select) */
1322 #define QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT 0
1323 #define QCA_SPI_FUNC_SEL_FUNC_SEL_MASK (1 << QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT)
1325 /* SPI_CONTROL register (SPI control) */
1326 #define QCA_SPI_CTRL_CLK_DIV_SHIFT 0
1327 #define QCA_SPI_CTRL_CLK_DIV_MASK BITS(QCA_SPI_CTRL_CLK_DIV_SHIFT, 6)
1328 #define QCA_SPI_CTRL_REMAP_DIS_SHIFT 6
1329 #define QCA_SPI_CTRL_REMAP_DIS_MASK (1 << QCA_SPI_CTRL_REMAP_DIS_SHIFT)
1330 #define QCA_SPI_CTRL_SPI_RELOCATE_SHIFT 7
1331 #define QCA_SPI_CTRL_SPI_RELOCATE_MASK (1 << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT)
1332 #define QCA_SPI_CTRL_TSHSL_CNT_SHIFT 8
1333 #define QCA_SPI_CTRL_TSHSL_CNT_MASK BITS(QCA_SPI_CTRL_TSHSL_CNT_SHIFT, 6)
1335 /* SPI_IO_CONTROL register (SPI I/O control) */
1336 #define QCA_SPI_IO_CTRL_IO_DO_SHIFT 0
1337 #define QCA_SPI_IO_CTRL_IO_DO_MASK (1 << QCA_SPI_IO_CTRL_IO_DO_SHIFT)
1338 #define QCA_SPI_IO_CTRL_IO_CLK_SHIFT 8
1339 #define QCA_SPI_IO_CTRL_IO_CLK_MASK (1 << QCA_SPI_IO_CTRL_IO_CLK_SHIFT)
1340 #define QCA_SPI_IO_CTRL_IO_CS0_SHIFT 16
1341 #define QCA_SPI_IO_CTRL_IO_CS0_MASK (1 << QCA_SPI_IO_CTRL_IO_CS0_SHIFT)
1342 #define QCA_SPI_IO_CTRL_IO_CS1_SHIFT 17
1343 #define QCA_SPI_IO_CTRL_IO_CS1_MASK (1 << QCA_SPI_IO_CTRL_IO_CS1_SHIFT)
1344 #define QCA_SPI_IO_CTRL_IO_CS2_SHIFT 18
1345 #define QCA_SPI_IO_CTRL_IO_CS2_MASK (1 << QCA_SPI_IO_CTRL_IO_CS2_SHIFT)
1347 /* SPI_SHIFT_CNT_ADDR register (SPI content to shift out or in) */
1348 #define QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT 0
1349 #define QCA_SPI_SHIFT_CNT_BITS_CNT_MASK BITS(QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT, 7)
1350 #define QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT 26
1351 #define QCA_SPI_SHIFT_CNT_TERMINATE_MASK (1 << QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT)
1352 #define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT 27
1353 #define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_MASK (1 << QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT)
1354 #define QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT 28
1355 #define QCA_SPI_SHIFT_CNT_CHNL_CS0_MASK (1 << QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT)
1356 #define QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT 29
1357 #define QCA_SPI_SHIFT_CNT_CHNL_CS1_MASK (1 << QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT)
1358 #define QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT 30
1359 #define QCA_SPI_SHIFT_CNT_CHNL_CS2_MASK (1 << QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT)
1360 #define QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT 31
1361 #define QCA_SPI_SHIFT_CNT_SHIFT_EN_MASK (1 << QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT)
1364 * Other useful defines
1367 /* Magic flag for indication that PLL/clocks config is stored in FLASH */
1368 #define QCA_PLL_IN_FLASH_MAGIC 0x504C4C73
1373 #ifndef __ASSEMBLY__
1374 inline u32 qca_xtal_is_40mhz(void);
1375 inline u32 qca_mem_type(void);
1376 void qca_soc_name_rev(char *buf);
1377 void qca_full_chip_reset(void);
1378 void qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk, u32 *spi_clk, u32 *ref_clk);
1379 void qca_sf_bulk_erase(u32 bank);
1380 void qca_sf_write_page(u32 bank, u32 address, u32 length, u8 *data);
1381 u32 qca_sf_sect_erase(u32 bank, u32 address, u32 sect_size, u8 erase_cmd);
1382 u32 qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_cmd);
1383 u32 qca_sf_jedec_id(u32 bank);
1384 #endif /* !__ASSEMBLY__ */
1387 * Read, write, set and clear macros
1389 #define qca_soc_reg_read(_addr) *(volatile unsigned int *)(KSEG1ADDR(_addr))
1390 #define qca_soc_reg_write(_addr, _val) ((*(volatile unsigned int *)KSEG1ADDR(_addr)) = (_val))
1392 #define qca_soc_reg_read_set(_addr, _mask) \
1393 qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) | (_mask)))
1395 #define qca_soc_reg_read_clear(_addr, _mask) \
1396 qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) & ~(_mask)))
1398 #endif /* _QCA_SOC_COMMON_H_ */
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