Add and fix DRAM register defines and two func prototypes in common QC/A header

[oweals/u-boot_mod.git] / u-boot / include / soc / qca_soc_common.h

/*
 * Qualcomm/Atheros Wireless SOC common registers definitions
 *
 * Copyright (C) 2014 Piotr Dymacz <piotr@dymacz.pl>
 * Copyright (C) 2008-2010 Atheros Communications Inc.
 *
 * Partially based on:
 * Linux/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 *
 * SPDX-License-Identifier:GPL-2.0
 */

#ifndef _QCA_SOC_COMMON_H_
#define _QCA_SOC_COMMON_H_

#include <soc/soc_common.h>

/*
 * Address map
 */
#define QCA_APB_BASE_REG                        0x18000000
#define QCA_FLASH_BASE_REG                      0x1F000000

/*
 * APB block
 */
#define QCA_DDR_CTRL_BASE_REG           QCA_APB_BASE_REG + 0x00000000

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_HSUART_BASE_REG             QCA_APB_BASE_REG + 0x00020000
#else
        #define QCA_LSUART_BASE_REG             QCA_APB_BASE_REG + 0x00020000
        #define QCA_HSUART_BASE_REG             QCA_APB_BASE_REG + 0x00500000
#endif

#define QCA_USB_CFG_BASE_REG            QCA_APB_BASE_REG + 0x00030000
#define QCA_GPIO_BASE_REG                       QCA_APB_BASE_REG + 0x00040000
#define QCA_PLL_BASE_REG                        QCA_APB_BASE_REG + 0x00050000
#define QCA_RST_BASE_REG                        QCA_APB_BASE_REG + 0x00060000
#define QCA_GMAC_BASE_REG                       QCA_APB_BASE_REG + 0x00070000
#define QCA_RTC_BASE_REG                        QCA_APB_BASE_REG + 0x00107000
#define QCA_PLL_SRIF_BASE_REG           QCA_APB_BASE_REG + 0x00116000

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_SLIC_BASE_REG               QCA_APB_BASE_REG + 0x00090000
#elif (SOC_TYPE & QCA_AR934X_SOC) | \
          (SOC_TYPE & QCA_AR955X_SOC)
        #define QCA_SLIC_BASE_REG               QCA_APB_BASE_REG + 0x000A9000
#endif

/*
 * DDR registers
 */
#define QCA_DDR_CFG_REG                                                 QCA_DDR_CTRL_BASE_REG + 0x000
#define QCA_DDR_CFG2_REG                                                QCA_DDR_CTRL_BASE_REG + 0x004
#define QCA_DDR_MR_REG                                                  QCA_DDR_CTRL_BASE_REG + 0x008
#define QCA_DDR_EMR_REG                                                 QCA_DDR_CTRL_BASE_REG + 0x00C
#define QCA_DDR_CTRL_REG                                                QCA_DDR_CTRL_BASE_REG + 0x010
#define QCA_DDR_REFRESH_REG                                             QCA_DDR_CTRL_BASE_REG + 0x014
#define QCA_DDR_RD_DATA_THIS_CYCLE_REG                  QCA_DDR_CTRL_BASE_REG + 0x018
#define QCA_DDR_TAP_CTRL_0_REG                                  QCA_DDR_CTRL_BASE_REG + 0x01C
#define QCA_DDR_TAP_CTRL_1_REG                                  QCA_DDR_CTRL_BASE_REG + 0x020
#define QCA_DDR_TAP_CTRL_2_REG                                  QCA_DDR_CTRL_BASE_REG + 0x024
#define QCA_DDR_TAP_CTRL_3_REG                                  QCA_DDR_CTRL_BASE_REG + 0x028

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_DDR_WB_FLUSH_GE0_REG                        QCA_DDR_CTRL_BASE_REG + 0x07C
        #define QCA_DDR_WB_FLUSH_GE1_REG                        QCA_DDR_CTRL_BASE_REG + 0x080
        #define QCA_DDR_WB_FLUSH_USB_REG                        QCA_DDR_CTRL_BASE_REG + 0x084
#else
        #define QCA_DDR_WB_FLUSH_GE0_REG                        QCA_DDR_CTRL_BASE_REG + 0x09C
        #define QCA_DDR_WB_FLUSH_GE1_REG                        QCA_DDR_CTRL_BASE_REG + 0x0A0
        #define QCA_DDR_WB_FLUSH_USB_REG                        QCA_DDR_CTRL_BASE_REG + 0x0A4
        #define QCA_DDR_WB_FLUSH_PCIE_REG                       QCA_DDR_CTRL_BASE_REG + 0x0A8
        #define QCA_DDR_WB_FLUSH_WMAC_REG                       QCA_DDR_CTRL_BASE_REG + 0x0AC
        #define QCA_DDR_WB_FLUSH_SRC1_REG                       QCA_DDR_CTRL_BASE_REG + 0x0B0
        #define QCA_DDR_WB_FLUSH_SRC2_REG                       QCA_DDR_CTRL_BASE_REG + 0x0B4
#endif

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_DDR_DDR2_CFG_REG                            QCA_DDR_CTRL_BASE_REG + 0x08C
        #define QCA_DDR_EMR2_REG                                        QCA_DDR_CTRL_BASE_REG + 0x090
        #define QCA_DDR_EMR3_REG                                        QCA_DDR_CTRL_BASE_REG + 0x094
        #define QCA_DDR_BURST_REG                                       QCA_DDR_CTRL_BASE_REG + 0x098
        #define QCA_AHB_MASTER_TOUT_MAX_REG                     QCA_DDR_CTRL_BASE_REG + 0x09C
        #define QCA_AHB_MASTER_TOUT_CURR_REG            QCA_DDR_CTRL_BASE_REG + 0x0A0
        #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG        QCA_DDR_CTRL_BASE_REG + 0x0A4
        #define QCA_SDR_CFG_REG                                         QCA_DDR_CTRL_BASE_REG + 0x0D8
#else
        #define QCA_DDR_DDR2_CFG_REG                            QCA_DDR_CTRL_BASE_REG + 0x0B8
        #define QCA_DDR_EMR2_REG                                        QCA_DDR_CTRL_BASE_REG + 0x0BC
        #define QCA_DDR_EMR3_REG                                        QCA_DDR_CTRL_BASE_REG + 0x0C0
        #define QCA_DDR_BURST_REG                                       QCA_DDR_CTRL_BASE_REG + 0x0C4
        #define QCA_DDR_BURST2_REG                                      QCA_DDR_CTRL_BASE_REG + 0x0C8
        #define QCA_AHB_MASTER_TOUT_MAX_REG                     QCA_DDR_CTRL_BASE_REG + 0x0CC
        #define QCA_AHB_MASTER_TOUT_CURR_REG            QCA_DDR_CTRL_BASE_REG + 0x0D0
        #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG        QCA_DDR_CTRL_BASE_REG + 0x0D4
        #define QCA_DDR_CTRL_CFG_REG                            QCA_DDR_CTRL_BASE_REG + 0x108
        #define QCA_DDR_SELF_REFRESH_CTRL_REG           QCA_DDR_CTRL_BASE_REG + 0x110
        #define QCA_DDR_SELF_REFRESH_TIMER_REG          QCA_DDR_CTRL_BASE_REG + 0x114
        #define QCA_DDR_WMAC_FLUSH_REG                          QCA_DDR_CTRL_BASE_REG + 0x128
        #define QCA_DDR_CFG3_REG                                        QCA_DDR_CTRL_BASE_REG + 0x15C
#endif

/*
 * DDR registers BIT fields
 */

/* DDR_CONFIG register (DDR DRAM configuration) */
#define QCA_DDR_CFG_TRAS_SHIFT                                  0
#define QCA_DDR_CFG_TRAS_MASK                                   BITS(QCA_DDR_CFG_TRAS_SHIFT, 5)
#define QCA_DDR_CFG_TRCD_SHIFT                                  5
#define QCA_DDR_CFG_TRCD_MASK                                   BITS(QCA_DDR_CFG_TRCD_SHIFT, 4)
#define QCA_DDR_CFG_TRP_SHIFT                                   9
#define QCA_DDR_CFG_TRP_MASK                                    BITS(QCA_DDR_CFG_TRP_SHIFT, 4)
#define QCA_DDR_CFG_TRRD_SHIFT                                  13
#define QCA_DDR_CFG_TRRD_MASK                                   BITS(QCA_DDR_CFG_TRRD_SHIFT, 4)
#define QCA_DDR_CFG_TRFC_SHIFT                                  17
#define QCA_DDR_CFG_TRFC_MASK                                   BITS(QCA_DDR_CFG_TRFC_SHIFT, 6)
#define QCA_DDR_CFG_TMRD_SHIFT                                  23
#define QCA_DDR_CFG_TMRD_MASK                                   BITS(QCA_DDR_CFG_TMRD_SHIFT, 4)
#define QCA_DDR_CFG_CAS_3LSB_SHIFT                              27
#define QCA_DDR_CFG_CAS_3LSB_MASK                               BITS(QCA_DDR_CFG_CAS_3LSB_SHIFT, 3)
#define QCA_DDR_CFG_PAGE_CLOSE_SHIFT                    30
#define QCA_DDR_CFG_PAGE_CLOSE_MASK                             (1 << QCA_DDR_CFG_PAGE_CLOSE_SHIFT)
#define QCA_DDR_CFG_CAS_MSB_SHIFT                               31
#define QCA_DDR_CFG_CAS_MSB_MASK                                (1 << QCA_DDR_CFG_CAS_MSB_SHIFT)

/* DDR_CONFIG2 register (DDR DRAM configuration 2) */
#define QCA_DDR_CFG2_BURST_LEN_SHIFT                    0
#define QCA_DDR_CFG2_BURST_LEN_MASK                             BITS(QCA_DDR_CFG2_BURST_LEN_SHIFT, 4)
#define QCA_DDR_CFG2_BURST_TYPE_SHIFT                   4
#define QCA_DDR_CFG2_BURST_TYPE_MASK                    (1 << QCA_DDR_CFG2_BURST_TYPE_SHIFT)
#define QCA_DDR_CFG2_CTRL_OE_EN_SHIFT                   5
#define QCA_DDR_CFG2_CTRL_OE_EN_MASK                    (1 << QCA_DDR_CFG2_CTRL_OE_EN_SHIFT)
#define QCA_DDR_CFG2_PHASE_SEL_SHIFT                    6
#define QCA_DDR_CFG2_PHASE_SEL_MASK                             (1 << QCA_DDR_CFG2_PHASE_SEL_SHIFT)
#define QCA_DDR_CFG2_CKE_SHIFT                                  7
#define QCA_DDR_CFG2_CKE_MASK                                   (1 << QCA_DDR_CFG2_CKE_SHIFT)
#define QCA_DDR_CFG2_TWR_SHIFT                                  8
#define QCA_DDR_CFG2_TWR_MASK                                   BITS(QCA_DDR_CFG2_TWR_SHIFT, 4)
#define QCA_DDR_CFG2_TRTW_SHIFT                                 12
#define QCA_DDR_CFG2_TRTW_MASK                                  BITS(QCA_DDR_CFG2_TRTW_SHIFT, 5)
#define QCA_DDR_CFG2_TRTP_SHIFT                                 17
#define QCA_DDR_CFG2_TRTP_MASK                                  BITS(QCA_DDR_CFG2_TRTP_SHIFT, 4)
#define QCA_DDR_CFG2_TWTR_SHIFT                                 21
#define QCA_DDR_CFG2_TWTR_MASK                                  BITS(QCA_DDR_CFG2_TWTR_SHIFT, 5)
#define QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT    26
#define QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK             BITS(QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT, 4)
#define QCA_DDR_CFG2_SWAP_A26_A27_SHIFT                 30
#define QCA_DDR_CFG2_SWAP_A26_A27_MASK                  (1 << QCA_DDR_CFG2_SWAP_A26_A27_SHIFT)
#define QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT               31
#define QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK                (1 << QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT)

/* DDR_MODE register (DDR mode register value) */
#define QCA_DDR_MR_VALUE_SHIFT                                  0
#define QCA_DDR_MR_VALUE_MASK                                   BITS(QCA_DDR_MR_VALUE_SHIFT, 14)


/* DDR_EMR registers (DDR extended mode register 1/2/3 values) */
#define QCA_DDR_EMR_VALUE_SHIFT                                 0
#define QCA_DDR_EMR_VALUE_MASK                                  BITS(QCA_DDR_EMR_VALUE_SHIFT, 14)

/* DDR_CONTROL register (DDR control) */
#define QCA_DDR_CTRL_FORCE_MRS_SHIFT                    0
#define QCA_DDR_CTRL_FORCE_MRS_MASK                             (1 << QCA_DDR_CTRL_FORCE_MRS_SHIFT)
#define QCA_DDR_CTRL_FORCE_EMRS_SHIFT                   1
#define QCA_DDR_CTRL_FORCE_EMRS_MASK                    (1 << QCA_DDR_CTRL_FORCE_EMRS_SHIFT)
#define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT   2
#define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK    (1 << QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT)
#define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT  3
#define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK   (1 << QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT)
#define QCA_DDR_CTRL_FORCE_EMR2S_SHIFT                  4
#define QCA_DDR_CTRL_FORCE_EMR2S_MASK                   (1 << QCA_DDR_CTRL_FORCE_EMR2S_SHIFT)
#define QCA_DDR_CTRL_FORCE_EMR3S_SHIFT                  5
#define QCA_DDR_CTRL_FORCE_EMR3S_MASK                   (1 << QCA_DDR_CTRL_FORCE_EMR3S_SHIFT)

/* DDR_REFRESH register (DDR refresh control and configuration) */
#define QCA_DDR_REFRESH_PERIOD_SHIFT                    0
#define QCA_DDR_REFRESH_PERIOD_MASK                             BITS(QCA_DDR_REFRESH_PERIOD_SHIFT, 14)
#define QCA_DDR_REFRESH_EN_SHIFT                                14
#define QCA_DDR_REFRESH_EN_MASK                                 (1 << QCA_DDR_REFRESH_EN_SHIFT)

/* DDR_RD_DATA_THIS_CYCLE register (DDR read data capture bit mask) */
#define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT    0
#define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_MASK             BITS(QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT, 32)

/* TAP_CONTROL_X registers (DQS delay tap control for byte X) */
#if (SOC_TYPE & QCA_AR933X_SOC) | \
        (SOC_TYPE & QCA_AR934X_SOC)
        #define QCA_DDR_TAP_CTRL_TAP_L_SHIFT            0
        #define QCA_DDR_TAP_CTRL_TAP_L_MASK                     BITS(QCA_DDR_TAP_CTRL_TAP_L_SHIFT, 5)
        #define QCA_DDR_TAP_CTRL_TAP_H_SHIFT            8
        #define QCA_DDR_TAP_CTRL_TAP_H_MASK                     BITS(QCA_DDR_TAP_CTRL_TAP_H_SHIFT, 2)
        #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT     16
        #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_MASK      (1 << QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT)
#else
        #define QCA_DDR_TAP_CTRL_TAP_SHIFT                      0
        #define QCA_DDR_TAP_CTRL_TAP_MASK                       BITS(QCA_DDR_TAP_CTRL_TAP_SHIFT, 6)
#endif

/* DDR_DDR2_CONFIG register (DDR2 configuration) */
#define QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT                  0
#define QCA_DDR_DDR2_CFG_DDR2_EN_MASK                   (1 << QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT)
#define QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT                2
#define QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK                 BITS(QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT, 6)
#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT         10
        #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK          BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 3)
#else
        #define QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT         10
        #define QCA_DDR_DDR2_CFG_DDR2_TWL_MASK          BITS(QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT, 4)
#endif

/* DDR_CTRL_CFG (DDR controller configuration) */
#define QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT                 0
#define QCA_DDR_CTRL_CFG_SDRAM_EN_MASK                  (1 << QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT)
#define QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT               1
#define QCA_DDR_CTRL_CFG_HALF_WIDTH_MASK                (1 << QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT)
#define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT             2
#define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_MASK              (1 << QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT)
#define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT             3
#define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_MASK              (1 << QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT)
#define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT    4
#define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_MASK             (1 << QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT)
#define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT             6
#define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_MASK              (1 << QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT)

/* DDR_CONFIG3 register (DDR DRAM configuration 3) */
#define QCA_DDR_CFG3_TRFC_LSB_SHIFT                             0
#define QCA_DDR_CFG3_TRFC_LSB_MASK                              BITS(QCA_DDR_CFG3_TRFC_LSB_SHIFT, 2)
#define QCA_DDR_CFG3_TRAS_MSB_SHIFT                             2
#define QCA_DDR_CFG3_TRAS_MSB_MASK                              (1 << QCA_DDR_CFG3_TRAS_MSB_SHIFT)
#define QCA_DDR_CFG3_TWR_MSB_SHIFT                              3
#define QCA_DDR_CFG3_TWR_MSB_MASK                               (1 << QCA_DDR_CFG3_TWR_MSB_SHIFT)

/*
 * Low-Speed UART registers
 */
#define QCA_LSUART_RBR_REG              QCA_LSUART_BASE_REG + 0x00
#define QCA_LSUART_THR_REG              QCA_LSUART_BASE_REG + 0x00
#define QCA_LSUART_DLL_REG              QCA_LSUART_BASE_REG + 0x00
#define QCA_LSUART_DLH_REG              QCA_LSUART_BASE_REG + 0x04
#define QCA_LSUART_IER_REG              QCA_LSUART_BASE_REG + 0x04
#define QCA_LSUART_IIR_REG              QCA_LSUART_BASE_REG + 0x08
#define QCA_LSUART_FCR_REG              QCA_LSUART_BASE_REG + 0x08
#define QCA_LSUART_LCR_REG              QCA_LSUART_BASE_REG + 0x0C
#define QCA_LSUART_MCR_REG              QCA_LSUART_BASE_REG + 0x10
#define QCA_LSUART_LSR_REG              QCA_LSUART_BASE_REG + 0x14
#define QCA_LSUART_MSR_REG              QCA_LSUART_BASE_REG + 0x18

/*
 * Low-Speed UART registers BIT fields
 */

/* RBR register (Receive buffer) */
#define QCA_LSUART_RBR_RBR_SHIFT                                0
#define QCA_LSUART_RBR_RBR_MASK                                 BITS(QCA_LSUART_RBR_RBR_SHIFT, 8)

/* THR register (Transmit holding) */
#define QCA_LSUART_THR_THR_SHIFT                                0
#define QCA_LSUART_THR_THR_MASK                                 BITS(QCA_LSUART_THR_THR_SHIFT, 8)

/* DLL register (Divisor latch low) */
#define QCA_LSUART_DLL_DLL_SHIFT                                0
#define QCA_LSUART_DLL_DLL_MASK                                 BITS(QCA_LSUART_DLL_DLL_SHIFT, 8)

/* DLH register (Divisor latch high) */
#define QCA_LSUART_DLH_DLH_SHIFT                                0
#define QCA_LSUART_DLH_DLH_MASK                                 BITS(QCA_LSUART_DLH_DLH_SHIFT, 8)

/* IER register (Interrupt enable) */
#define QCA_LSUART_IER_ERBFI_SHIFT                              0
#define QCA_LSUART_IER_ERBFI_MASK                               (1 << QCA_LSUART_IER_ERBFI_SHIFT)
#define QCA_LSUART_IER_ETBEI_SHIFT                              1
#define QCA_LSUART_IER_ETBEI_MASK                               (1 << QCA_LSUART_IER_ETBEI_SHIFT)
#define QCA_LSUART_IER_ELSI_SHIFT                               2
#define QCA_LSUART_IER_ELSI_MASK                                (1 << QCA_LSUART_IER_ELSI_SHIFT)
#define QCA_LSUART_IER_EDDSI_SHIFT                              3
#define QCA_LSUART_IER_EDDSI_MASK                               (1 << QCA_LSUART_IER_EDDSI_SHIFT)

/* IIR register (Interrupt identity) */
#define QCA_LSUART_IIR_IID_SHIFT                                0
#define QCA_LSUART_IIR_IID_MASK                                 BITS(QCA_LSUART_IIR_IID_SHIFT, 4)
#define QCA_LSUART_IIR_FIFO_STATUS_SHIFT                6
#define QCA_LSUART_IIR_FIFO_STATUS_MASK                 BITS(QCA_LSUART_IIR_FIFO_STATUS_SHIFT, 2)

/* FCR register (FIFO control) */
#define QCA_LSUART_FCR_FIFO_EN_SHIFT                    0
#define QCA_LSUART_FCR_EDDSI_MASK                               (1 << QCA_LSUART_FCR_FIFO_EN_SHIFT)
#define QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT              1
#define QCA_LSUART_FCR_RCVR_FIFO_RST_MASK               (1 << QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT)
#define QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT              2
#define QCA_LSUART_FCR_XMIT_FIFO_RST_MASK               (1 << QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT)
#define QCA_LSUART_FCR_DMA_MODE_SHIFT                   3
#define QCA_LSUART_FCR_DMA_MODE_MASK                    (1 << QCA_LSUART_FCR_DMA_MODE_SHIFT)
#define QCA_LSUART_FCR_RCVR_TRIG_SHIFT                  6
#define QCA_LSUART_FCR_RCVR_TRIG_MASK                   BITS(QCA_LSUART_FCR_RCVR_TRIG_SHIFT, 2)

/* LCR register (Line control) */
#define QCA_LSUART_LCR_CLS_SHIFT                                0
#define QCA_LSUART_LCR_CLS_MASK                                 BITS(QCA_LSUART_LCR_CLS_SHIFT, 2)
#define QCA_LSUART_LCR_CLS_5BIT_VAL                             0x0
#define QCA_LSUART_LCR_CLS_6BIT_VAL                             0x1
#define QCA_LSUART_LCR_CLS_7BIT_VAL                             0x2
#define QCA_LSUART_LCR_CLS_8BIT_VAL                             0x3
#define QCA_LSUART_LCR_STOP_SHIFT                               2
#define QCA_LSUART_LCR_STOP_MASK                                (1 << QCA_LSUART_LCR_STOP_SHIFT)
#define QCA_LSUART_LCR_PEN_SHIFT                                3
#define QCA_LSUART_LCR_PEN_MASK                                 (1 << QCA_LSUART_LCR_PEN_SHIFT)
#define QCA_LSUART_LCR_EPS_SHIFT                                4
#define QCA_LSUART_LCR_EPS_MASK                                 (1 << QCA_LSUART_LCR_EPS_SHIFT)
#define QCA_LSUART_LCR_BREAK_SHIFT                              6
#define QCA_LSUART_LCR_BREAK_MASK                               (1 << QCA_LSUART_LCR_BREAK_SHIFT)
#define QCA_LSUART_LCR_DLAB_SHIFT                               7
#define QCA_LSUART_LCR_DLAB_MASK                                (1 << QCA_LSUART_LCR_DLAB_SHIFT)

/* MCR register (Modem control) */
#define QCA_LSUART_MCR_DTR_SHIFT                                0
#define QCA_LSUART_MCR_DTR_MASK                                 (1 << QCA_LSUART_MCR_DTR_SHIFT)
#define QCA_LSUART_MCR_RTS_SHIFT                                1
#define QCA_LSUART_MCR_RTS_MASK                                 (1 << QCA_LSUART_MCR_RTS_SHIFT)
#define QCA_LSUART_MCR_OUT1_SHIFT                               2
#define QCA_LSUART_MCR_OUT1_MASK                                (1 << QCA_LSUART_MCR_OUT1_SHIFT)
#define QCA_LSUART_MCR_OUT2_SHIFT                               3
#define QCA_LSUART_MCR_OUT2_MASK                                (1 << QCA_LSUART_MCR_OUT2_SHIFT)
#define QCA_LSUART_MCR_LOOPBACK_SHIFT                   5
#define QCA_LSUART_MCR_LOOPBACK_MASK                    (1 << QCA_LSUART_MCR_LOOPBACK_SHIFT)

/* LSR register (Line status) */
#define QCA_LSUART_LSR_DR_SHIFT                                 0
#define QCA_LSUART_LSR_DR_MASK                                  (1 << QCA_LSUART_LSR_DR_SHIFT)
#define QCA_LSUART_LSR_OE_SHIFT                                 1
#define QCA_LSUART_LSR_OE_MASK                                  (1 << QCA_LSUART_LSR_OE_SHIFT)
#define QCA_LSUART_LSR_PE_SHIFT                                 2
#define QCA_LSUART_LSR_PE_MASK                                  (1 << QCA_LSUART_LSR_PE_SHIFT)
#define QCA_LSUART_LSR_FE_SHIFT                                 3
#define QCA_LSUART_LSR_FE_MASK                                  (1 << QCA_LSUART_LSR_FE_SHIFT)
#define QCA_LSUART_LSR_BI_SHIFT                                 4
#define QCA_LSUART_LSR_BI_MASK                                  (1 << QCA_LSUART_LSR_BI_SHIFT)
#define QCA_LSUART_LSR_THRE_SHIFT                               5
#define QCA_LSUART_LSR_THRE_MASK                                (1 << QCA_LSUART_LSR_THRE_SHIFT)
#define QCA_LSUART_LSR_TEMT_SHIFT                               6
#define QCA_LSUART_LSR_TEMT_MASK                                (1 << QCA_LSUART_LSR_TEMT_SHIFT)
#define QCA_LSUART_LSR_FERR_SHIFT                               7
#define QCA_LSUART_LSR_FERR_MASK                                (1 << QCA_LSUART_LSR_FERR_SHIFT)

/* MCR register (Modem status) */
#define QCA_LSUART_MCR_DCTS_SHIFT                               0
#define QCA_LSUART_MCR_DCTS_MASK                                (1 << QCA_LSUART_MCR_DCTS_SHIFT)
#define QCA_LSUART_MCR_DDSR_SHIFT                               1
#define QCA_LSUART_MCR_DDSR_MASK                                (1 << QCA_LSUART_MCR_DDSR_SHIFT)
#define QCA_LSUART_MCR_TERI_SHIFT                               2
#define QCA_LSUART_MCR_TERI_MASK                                (1 << QCA_LSUART_MCR_TERI_SHIFT)
#define QCA_LSUART_MCR_DDCD_SHIFT                               3
#define QCA_LSUART_MCR_DDCD_MASK                                (1 << QCA_LSUART_MCR_DDCD_SHIFT)
#define QCA_LSUART_MCR_CTS_SHIFT                                4
#define QCA_LSUART_MCR_CTS_MASK                                 (1 << QCA_LSUART_MCR_CTS_SHIFT)
#define QCA_LSUART_MCR_DSR_SHIFT                                5
#define QCA_LSUART_MCR_DSR_MASK                                 (1 << QCA_LSUART_MCR_DSR_SHIFT)
#define QCA_LSUART_MCR_RI_SHIFT                                 6
#define QCA_LSUART_MCR_RI_MASK                                  (1 << QCA_LSUART_MCR_RI_SHIFT)
#define QCA_LSUART_MCR_DCD_SHIFT                                7
#define QCA_LSUART_MCR_DCD_MASK                                 (1 << QCA_LSUART_MCR_DCD_SHIFT)

/*
 * High-Speed UART registers
 */
#define QCA_HSUART_DATA_REG                                             QCA_HSUART_BASE_REG + 0x00
#define QCA_HSUART_CS_REG                                               QCA_HSUART_BASE_REG + 0x04
#define QCA_HSUART_CLK_REG                                              QCA_HSUART_BASE_REG + 0x08
#define QCA_HSUART_INT_REG                                              QCA_HSUART_BASE_REG + 0x0C
#define QCA_HSUART_INT_EN_REG                                   QCA_HSUART_BASE_REG + 0x10

/*
 * High-Speed UART registers BIT fields
 */

/* UART_DATA register (UART transmit and RX FIFO interface ) */
#define QCA_HSUART_DATA_TX_RX_DATA_SHIFT                0
#define QCA_HSUART_DATA_TX_RX_DATA_MASK                 BITS(QCA_HSUART_DATA_TX_RX_DATA_SHIFT, 8)
#define QCA_HSUART_DATA_RX_CSR_SHIFT                    8
#define QCA_HSUART_DATA_RX_CSR_MASK                             (1 << QCA_HSUART_DATA_RX_CSR_SHIFT)
#define QCA_HSUART_DATA_TX_CSR_SHIFT                    9
#define QCA_HSUART_DATA_TX_CSR_MASK                             (1 << QCA_HSUART_DATA_TX_CSR_SHIFT)

/* UART_CS register (UART configuration and status) */
#define QCA_HSUART_CS_PAR_MODE_SHIFT                    0
#define QCA_HSUART_CS_PAR_MODE_MASK                             BITS(QCA_HSUART_CS_PAR_MODE_SHIFT, 2)
#define QCA_HSUART_CS_PAR_MODE_NO_VAL                   0x0
#define QCA_HSUART_CS_PAR_MODE_ODD_VAL                  0x2
#define QCA_HSUART_CS_PAR_MODE_OVEN_VAL                 0x3
#define QCA_HSUART_CS_IFACE_MODE_SHIFT                  2
#define QCA_HSUART_CS_IFACE_MODE_MASK                   BITS(QCA_HSUART_CS_IFACE_MODE_SHIFT, 2)
#define QCA_HSUART_CS_IFACE_MODE_DISABLE_VAL    0x0
#define QCA_HSUART_CS_IFACE_MODE_DTE_VAL                0x1
#define QCA_HSUART_CS_IFACE_MODE_DCE_VAL                0x2
#define QCA_HSUART_CS_FLOW_MODE_SHIFT                   4
#define QCA_HSUART_CS_FLOW_MODE_MASK                    BITS(QCA_HSUART_CS_FLOW_MODE_SHIFT, 2)
#define QCA_HSUART_CS_FLOW_MODE_NO_VAL                  0x0
#define QCA_HSUART_CS_FLOW_MODE_HW_VAL                  0x2
#define QCA_HSUART_CS_FLOW_MODE_INV_VAL                 0x3
#define QCA_HSUART_CS_DMA_EN_SHIFT                              6
#define QCA_HSUART_CS_DMA_EN_MASK                               (1 << QCA_HSUART_CS_DMA_EN_SHIFT)
#define QCA_HSUART_CS_RX_READY_ORIDE_SHIFT              7
#define QCA_HSUART_CS_RX_READY_ORIDE_MASK               (1 << QCA_HSUART_CS_RX_READY_ORIDE_SHIFT)
#define QCA_HSUART_CS_TX_READY_ORIDE_SHIFT              8
#define QCA_HSUART_CS_TX_READY_ORIDE_MASK               (1 << QCA_HSUART_CS_TX_READY_ORIDE_SHIFT)
#define QCA_HSUART_CS_TX_READY_SHIFT                    9
#define QCA_HSUART_CS_TX_READY_MASK                             (1 << QCA_HSUART_CS_TX_READY_SHIFT)
#define QCA_HSUART_CS_RX_BREAK_SHIFT                    10
#define QCA_HSUART_CS_RX_BREAK_MASK                             (1 << QCA_HSUART_CS_RX_BREAK_SHIFT)
#define QCA_HSUART_CS_TX_BREAK_SHIFT                    11
#define QCA_HSUART_CS_TX_BREAK_MASK                             (1 << QCA_HSUART_CS_TX_BREAK_SHIFT)
#define QCA_HSUART_CS_HOST_INT_SHIFT                    12
#define QCA_HSUART_CS_HOST_INT_MASK                             (1 << QCA_HSUART_CS_HOST_INT_SHIFT)
#define QCA_HSUART_CS_HOST_INT_EN_SHIFT                 13
#define QCA_HSUART_CS_HOST_INT_EN_MASK                  (1 << QCA_HSUART_CS_HOST_INT_EN_SHIFT)
#define QCA_HSUART_CS_TX_BUSY_SHIFT                             14
#define QCA_HSUART_CS_TX_BUSY_MASK                              (1 << QCA_HSUART_CS_TX_BUSY_SHIFT)
#define QCA_HSUART_CS_RX_BUSY_SHIFT                             15
#define QCA_HSUART_CS_RX_BUSY_MASK                              (1 << QCA_HSUART_CS_RX_BUSY_SHIFT)

/* UART_CLOCK register (UART clock) */
#define QCA_HSUART_CLK_STEP_SHIFT                               0
#define QCA_HSUART_CLK_STEP_MASK                                BITS(QCA_HSUART_CLK_STEP_SHIFT, 16)
#define QCA_HSUART_CLK_STEP_MAX_VAL                             0x3333
#define QCA_HSUART_CLK_SCALE_SHIFT                              16
#define QCA_HSUART_CLK_SCALE_MASK                               BITS(QCA_HSUART_CLK_SCALE_SHIFT, 8)
#define QCA_HSUART_CLK_SCALE_MAX_VAL                    0xFF

/* UART_INT register (UART interrupt/control status) */
#define QCA_HSUART_INT_RX_VALID_SHIFT                   0
#define QCA_HSUART_INT_RX_VALID_MASK                    (1 << QCA_HSUART_INT_RX_VALID_SHIFT)
#define QCA_HSUART_INT_TX_READY_SHIFT                   1
#define QCA_HSUART_INT_TX_READY_MASK                    (1 << QCA_HSUART_INT_TX_READY_SHIFT)
#define QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT             2
#define QCA_HSUART_INT_RX_FRAMING_ERR_MASK              (1 << QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT)
#define QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT    3
#define QCA_HSUART_INT_RX_OVERFLOW_ERR_MASK             (1 << QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT)
#define QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT    4
#define QCA_HSUART_INT_TX_OVERFLOW_ERR_MASK             (1 << QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT)
#define QCA_HSUART_INT_RX_PARITY_ERR_SHIFT              5
#define QCA_HSUART_INT_RX_PARITY_ERR_MASK               (1 << QCA_HSUART_INT_RX_PARITY_ERR_SHIFT)
#define QCA_HSUART_INT_RX_BREAK_ON_SHIFT                6
#define QCA_HSUART_INT_RX_BREAK_ON_MASK                 (1 << QCA_HSUART_INT_RX_BREAK_ON_SHIFT)
#define QCA_HSUART_INT_RX_BREAK_OFF_SHIFT               7
#define QCA_HSUART_INT_RX_BREAK_OFF_MASK                (1 << QCA_HSUART_INT_RX_BREAK_OFF_SHIFT)
#define QCA_HSUART_INT_RX_FULL_SHIFT                    8
#define QCA_HSUART_INT_RX_FULL_MASK                             (1 << QCA_HSUART_INT_RX_FULL_SHIFT)
#define QCA_HSUART_INT_TX_EMPTY_SHIFT                   9
#define QCA_HSUART_INT_TX_EMPTY_MASK                    (1 << QCA_HSUART_INT_TX_EMPTY_SHIFT)

/* UART_INT_EN register (UART interrupt enable) */
#define QCA_HSUART_INT_EN_RX_VALID_SHIFT                0
#define QCA_HSUART_INT_EN_RX_VALID_MASK                 (1 << QCA_HSUART_INT_EN_RX_VALID_SHIFT)
#define QCA_HSUART_INT_EN_TX_READY_SHIFT                1
#define QCA_HSUART_INT_EN_TX_READY_MASK                 (1 << QCA_HSUART_INT_EN_TX_READY_SHIFT)
#define QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT  2
#define QCA_HSUART_INT_EN_RX_FRAMING_ERR_MASK   (1 << QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT)
#define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT 3
#define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_MASK  (1 << QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT)
#define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT 4
#define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_MASK  (1 << QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT)
#define QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT   5
#define QCA_HSUART_INT_EN_RX_PARITY_ERR_MASK    (1 << QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT)
#define QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT             6
#define QCA_HSUART_INT_EN_RX_BREAK_ON_MASK              (1 << QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT)
#define QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT    7
#define QCA_HSUART_INT_EN_RX_BREAK_OFF_MASK             (1 << QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT)
#define QCA_HSUART_INT_EN_RX_FULL_SHIFT                 8
#define QCA_HSUART_INT_EN_RX_FULL_MASK                  (1 << QCA_HSUART_INT_EN_RX_FULL_SHIFT)
#define QCA_HSUART_INT_EN_TX_EMPTY_SHIFT                9
#define QCA_HSUART_INT_EN_TX_EMPTY_MASK                 (1 << QCA_HSUART_INT_EN_TX_EMPTY_SHIFT)


/*
 * GPIO registers
 */
#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_GPIO_COUNT                                          30
#elif (SOC_TYPE & QCA_AR934X_SOC)
        #define QCA_GPIO_COUNT                                          23
#elif (SOC_TYPE & QCA_QCA953X_SOC)
        #define QCA_GPIO_COUNT                                          18
#elif (SOC_TYPE & QCA_QCA955X_SOC)
        #define QCA_GPIO_COUNT                                          24
#endif

#define QCA_GPIO_OE_REG                                                 QCA_GPIO_BASE_REG + 0x00
#define QCA_GPIO_IN_REG                                                 QCA_GPIO_BASE_REG + 0x04
#define QCA_GPIO_OUT_REG                                                QCA_GPIO_BASE_REG + 0x08
#define QCA_GPIO_SET_REG                                                QCA_GPIO_BASE_REG + 0x0C
#define QCA_GPIO_CLEAR_REG                                              QCA_GPIO_BASE_REG + 0x10
#define QCA_GPIO_INT_EN_REG                                             QCA_GPIO_BASE_REG + 0x14
#define QCA_GPIO_INT_TYPE_REG                                   QCA_GPIO_BASE_REG + 0x18
#define QCA_GPIO_INT_POLARITY_REG                               QCA_GPIO_BASE_REG + 0x1C
#define QCA_GPIO_INT_PENDING_REG                                QCA_GPIO_BASE_REG + 0x20
#define QCA_GPIO_INT_MASK_REG                                   QCA_GPIO_BASE_REG + 0x24

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_GPIO_FUNC_1_REG                                     QCA_GPIO_BASE_REG + 0x28
        #define QCA_GPIO_IN_ETH_SWITCH_LED_REG          QCA_GPIO_BASE_REG + 0x2C
        #define QCA_GPIO_FUNC_2_REG                                     QCA_GPIO_BASE_REG + 0x30
        #define QCA_GPIO_WLAN_MUX_SET0_REG                      QCA_GPIO_BASE_REG + 0x34
        #define QCA_GPIO_WLAN_MUX_SET1_REG                      QCA_GPIO_BASE_REG + 0x38
        #define QCA_GPIO_WLAN_MUX_SET2_REG                      QCA_GPIO_BASE_REG + 0x3C
        #define QCA_GPIO_WLAN_MUX_SET3_REG                      QCA_GPIO_BASE_REG + 0x40
#else
        #if (SOC_TYPE & QCA_QCA955X_SOC)
                #define QCA_GPIO_SPARE_BITS_REG                 QCA_GPIO_BASE_REG + 0x28
        #else
                #define QCA_GPIO_IN_ETH_SWITCH_LED_REG  QCA_GPIO_BASE_REG + 0x28
        #endif

        #define QCA_GPIO_OUT_FUNC0_REG                          QCA_GPIO_BASE_REG + 0x2C
        #define QCA_GPIO_OUT_FUNC1_REG                          QCA_GPIO_BASE_REG + 0x30
        #define QCA_GPIO_OUT_FUNC2_REG                          QCA_GPIO_BASE_REG + 0x34
        #define QCA_GPIO_OUT_FUNC3_REG                          QCA_GPIO_BASE_REG + 0x38
        #define QCA_GPIO_OUT_FUNC4_REG                          QCA_GPIO_BASE_REG + 0x3C
        #define QCA_GPIO_OUT_FUNC5_REG                          QCA_GPIO_BASE_REG + 0x40
        #define QCA_GPIO_IN_EN0_REG                                     QCA_GPIO_BASE_REG + 0x44
        #define QCA_GPIO_IN_EN1_REG                                     QCA_GPIO_BASE_REG + 0x48
        #define QCA_GPIO_IN_EN2_REG                                     QCA_GPIO_BASE_REG + 0x4C
        #define QCA_GPIO_IN_EN3_REG                                     QCA_GPIO_BASE_REG + 0x50
        #define QCA_GPIO_IN_EN4_REG                                     QCA_GPIO_BASE_REG + 0x54
        #define QCA_GPIO_IN_EN9_REG                                     QCA_GPIO_BASE_REG + 0x68
        #define QCA_GPIO_FUNC_REG                                       QCA_GPIO_BASE_REG + 0x6C
#endif

/*
 * GPIO registers BIT fields
 */

/* GPIO_FUNCTION_1/2 register (GPIO function) */
#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT                  0
        #define QCA_GPIO_FUNC_1_JTAG_DIS_MASK                   (1 << QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT)
        #define QCA_GPIO_FUNC_1_UART_EN_SHIFT                   1
        #define QCA_GPIO_FUNC_1_UART_EN_MASK                    (1 << QCA_GPIO_FUNC_1_UART_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT   2
        #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_MASK    (1 << QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT    3
        #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_MASK             (1 << QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT    4
        #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_MASK             (1 << QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT    5
        #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_MASK             (1 << QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT    6
        #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_MASK             (1 << QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT    7
        #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_MASK             (1 << QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT                13
        #define QCA_GPIO_FUNC_1_SPI_CS_EN1_MASK                 (1 << QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT)
        #define QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT                14
        #define QCA_GPIO_FUNC_1_SPI_CS_EN2_MASK                 (1 << QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT)
        #define QCA_GPIO_FUNC_1_SPI_EN_SHIFT                    18
        #define QCA_GPIO_FUNC_1_SPI_EN_MASK                             (1 << QCA_GPIO_FUNC_1_SPI_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT    23
        #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_MASK             (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT)
        #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT   24
        #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_MASK    (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT)
        #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT   25
        #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_MASK    (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT)
        #define QCA_GPIO_FUNC_1_I2S_EN_SHIFT                    26
        #define QCA_GPIO_FUNC_1_I2S_EN_MASK                             (1 << QCA_GPIO_FUNC_1_I2S_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT               27
        #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_MASK                (1 << QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT              29
        #define QCA_GPIO_FUNC_1_I2S_22_18_EN_MASK               (1 << QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT                  30
        #define QCA_GPIO_FUNC_1_SPDIF_EN_MASK                   (1 << QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT)
        #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT              31
        #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_MASK               (1 << QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT)

        #define QCA_GPIO_FUNC_2_MIC_DIS_SHIFT                   0
        #define QCA_GPIO_FUNC_2_MIC_DIS_MASK                    (1 << QCA_GPIO_FUNC_2_MIC_DIS_SHIFT)
        #define QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT                1
        #define QCA_GPIO_FUNC_2_I2S_ON_LED_MASK                 (1 << QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT)
        #define QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT                2
        #define QCA_GPIO_FUNC_2_SPDIF_ON23_MASK                 (1 << QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT)
        #define QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT                 3
        #define QCA_GPIO_FUNC_2_I2SCK_ON1_MASK                  (1 << QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT)
        #define QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT                 4
        #define QCA_GPIO_FUNC_2_I2SWS_ON0_MASK                  (1 << QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT)
        #define QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT                5
        #define QCA_GPIO_FUNC_2_I2SSD_ON12_MASK                 (1 << QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT)
        #define QCA_GPIO_FUNC_2_WPS_DIS_SHIFT                   8
        #define QCA_GPIO_FUNC_2_WPS_DIS_MASK                    (1 << QCA_GPIO_FUNC_2_WPS_DIS_SHIFT)
        #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT             9
        #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_MASK              (1 << QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT)
        #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT              10
        #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_MASK               (1 << QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT)
        #define QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT               11
        #define QCA_GPIO_FUNC_2_USB_LED_ON1_MASK                (1 << QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT)
        #define QCA_GPIO_FUNC_2_LNA_ON28_SHIFT                  12
        #define QCA_GPIO_FUNC_2_LNA_ON28_MASK                   (1 << QCA_GPIO_FUNC_2_LNA_ON28_SHIFT)
        #define QCA_GPIO_FUNC_2_SLIC_EN_SHIFT                   13
        #define QCA_GPIO_FUNC_2_SLIC_EN_MASK                    (1 << QCA_GPIO_FUNC_2_SLIC_EN_SHIFT)
        #define QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT              14
        #define QCA_GPIO_FUNC_2_SLIC_ON18_22_MASK               (1 << QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT)
        #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT   15
        #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_MASK    (1 << QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT)
        #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT   16
        #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_MASK    BITS(QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT, 3)
#endif

/*
 * GPIO MUX
 */
#define QCA_GPIO_OUT_FUNCX_GPIOX_EN_SHIFT(_gpio)        ((_gpio % 4) * 8)
#define QCA_GPIO_OUT_FUNCX_GPIOX_EN_MASK(_gpio)         BIT(((_gpio % 4) * 8), 8)

#define QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT                       0
#define QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT                       0
#define QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT                       0
#define QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT                      0
#define QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT                      0
#define QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT                      0
#define QCA_GPIO_OUT_FUNCX_GPIO0_EN_MASK                        BITS(QCA_GPIO_OUT_FUNCX_GPIO0_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO4_EN_MASK                        BITS(QCA_GPIO_OUT_FUNCX_GPIO4_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO8_EN_MASK                        BITS(QCA_GPIO_OUT_FUNCX_GPIO8_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO12_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO12_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO16_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO16_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO20_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO20_EN_SHIFT, 8)

#define QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT                       8
#define QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT                       8
#define QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT                       8
#define QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT                      8
#define QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT                      8
#define QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT                      8
#define QCA_GPIO_OUT_FUNCX_GPIO1_EN_MASK                        BITS(QCA_GPIO_OUT_FUNCX_GPIO1_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO5_EN_MASK                        BITS(QCA_GPIO_OUT_FUNCX_GPIO5_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO9_EN_MASK                        BITS(QCA_GPIO_OUT_FUNCX_GPIO9_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO13_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO13_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO17_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO17_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO21_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO21_EN_SHIFT, 8)

#define QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT                       16
#define QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT                       16
#define QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT                      16
#define QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT                      16
#define QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT                      16
#define QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT                      16
#define QCA_GPIO_OUT_FUNCX_GPIO2_EN_MASK                        BITS(QCA_GPIO_OUT_FUNCX_GPIO2_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO6_EN_MASK                        BITS(QCA_GPIO_OUT_FUNCX_GPIO6_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO10_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO10_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO14_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO14_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO18_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO18_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO22_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO22_EN_SHIFT, 8)

#define QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT                       24
#define QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT                       24
#define QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT                      24
#define QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT                      24
#define QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT                      24
#define QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT                      24
#define QCA_GPIO_OUT_FUNCX_GPIO3_EN_MASK                        BITS(QCA_GPIO_OUT_FUNCX_GPIO3_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO7_EN_MASK                        BITS(QCA_GPIO_OUT_FUNCX_GPIO7_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO11_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO11_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO15_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO15_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO19_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO19_EN_SHIFT, 8)
#define QCA_GPIO_OUT_FUNCX_GPIO23_EN_MASK                       BITS(QCA_GPIO_OUT_FUNCX_GPIO23_EN_SHIFT, 8)

/* GPIO output select values (for MUX) */
#define QCA_GPIO_OUT_MUX_GPIO_VAL                                                       0
#define QCA_GPIO_OUT_MUX_MII_EXT_MDI_VAL                                        1
#define QCA_GPIO_OUT_MUX_SYS_RST_L_VAL                                          1
#define QCA_GPIO_OUT_MUX_NAND_CS0_VAL                                           1
#define QCA_GPIO_OUT_MUX_BOOT_RXT_MDI_VAL                                       2
#define QCA_GPIO_OUT_MUX_SPI_CS0_VAL                                            9

/* 5-port ethernet switch activity LEDs */
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN1_VAL                           26
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN2_VAL                           27
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN3_VAL                           28
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN4_VAL                           29
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_ACTN5_VAL                           30

/* 5-port ethernet switch collision detect LEDs */
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN1_VAL                           31
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN2_VAL                           32
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN3_VAL                           33
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN4_VAL                           34
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_COLN5_VAL                           35

/* 5-port ethernet switch full/half duplex LEDs */
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN1_VAL                           36
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN2_VAL                           37
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN3_VAL                           38
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN4_VAL                           39
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_DUPN5_VAL                           40

/* 5-port ethernet switch link indicator LEDs */
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK1_VAL                           41
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK2_VAL                           42
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK3_VAL                           43
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK4_VAL                           44
#define QCA_GPIO_OUT_MUX_ETH_SW_LED_LINK5_VAL                           45

#if (SOC_TYPE & QCA_AR934X_SOC)
        #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL                              4
        #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL                                5
        #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL                               6
        #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL                                    7
        #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL                                    8
        #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL                                    10
        #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL                                   11
        #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL                                    12
        #define QCA_GPIO_OUT_MUX_I2S_WS_VAL                                             13
        #define QCA_GPIO_OUT_MUX_I2S_SD_VAL                                             14
        #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL                                   15
        #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL                                   16
        #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL                                   17
        #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL                                   18
        #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL                                   19
        #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL                                   20
        #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL                                   21
        #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL                                   22
        #define QCA_GPIO_OUT_MUX_CLK_OBS7_VAL                                   23
        #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL                                 24
        #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL                                  25
        #define QCA_GPIO_OUT_MUX_ATT_LED_VAL                                    46
        #define QCA_GPIO_OUT_MUX_PWR_LED_VAL                                    47
        #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL                                   48
        #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL                               49
        #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL                             50
        #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL                               51
        #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL                              72
        #define QCA_GPIO_OUT_MUX_BT_ANT_VAL                                             73
        #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL                 74
        #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL                                 78
        #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL_VAL                             79
        #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL_VAL                             80
        #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL                                  84
        #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL                                87
#else
        #define QCA_GPIO_OUT_MUX_SLIC_DATA_OUT_VAL                              3
        #define QCA_GPIO_OUT_MUX_SLIC_PCM_FS_VAL                                4
        #define QCA_GPIO_OUT_MUX_SLIC_PCM_CLK_VAL                               5
        #define QCA_GPIO_OUT_MUX_SPI_CLK_VAL                                    8
        #define QCA_GPIO_OUT_MUX_SPI_CS1_VAL                                    10
        #define QCA_GPIO_OUT_MUX_SPI_CS2_VAL                                    11
        #define QCA_GPIO_OUT_MUX_SPI_MOSI_VAL                                   12
        #define QCA_GPIO_OUT_MUX_I2S_CLK_VAL                                    13
        #define QCA_GPIO_OUT_MUX_I2S_WS_VAL                                             14
        #define QCA_GPIO_OUT_MUX_I2S_SD_VAL                                             15
        #define QCA_GPIO_OUT_MUX_I2S_MCLK_VAL                                   16
        #define QCA_GPIO_OUT_MUX_SPDIF_OUT_VAL                                  17
        #define QCA_GPIO_OUT_MUX_HSUART_TXD_VAL                                 18
        #define QCA_GPIO_OUT_MUX_HSUART_RTS_VAL                                 19
        #define QCA_GPIO_OUT_MUX_HSUART_RXD_VAL                                 20      /* TODO: RXD is INPUT, mistake in QCA9558 datasheet? */
        #define QCA_GPIO_OUT_MUX_HSUART_CTS_VAL                                 21      /* TODO: CTS is INPUT, mistake in QCA9558 datasheet? */
        #define QCA_GPIO_OUT_MUX_LSUART_TXD_VAL                                 22
        #define QCA_GPIO_OUT_MUX_SRIF_OUT_VAL                                   23

        #if (SOC_TYPE & QCA_QCA955X_SOC)
                #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_VAL           24
                #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_VAL           25
                #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_VAL           26
                #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_VAL           27
                #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED0_INV_VAL       28
                #define QCA_GPIO_OUT_MUX_SGMII_LED_SPEED1_INV_VAL       29
                #define QCA_GPIO_OUT_MUX_SGMII_LED_DUPLEX_INV_VAL       30
                #define QCA_GPIO_OUT_MUX_SGMII_LED_LINKUP_INV_VAL       31
                #define QCA_GPIO_OUT_MUX_GE1_MII_MDO_VAL                        32
                #define QCA_GPIO_OUT_MUX_GE1_MII_MDC_VAL                        33
                #define QCA_GPIO_OUT_MUX_SWCOM2_VAL                                     38
                #define QCA_GPIO_OUT_MUX_SWCOM3_VAL                                     39
                #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL        40
                #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL        41
                #define QCA_GPIO_OUT_MUX_ATT_LED_VAL                            42
                #define QCA_GPIO_OUT_MUX_PWR_LED_VAL                            43
                #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL                           44
                #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXT_VAL                       45
                #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL                     46
                #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL                       47
                #define QCA_GPIO_OUT_MUX_WMAC_GLUE_WOW_VAL                      68
                #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL         70
                #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_STROBE_VAL     71
                #define QCA_GPIO_OUT_MUX_SMART_ANT_SHIFT_DATA_VAL       72
                #define QCA_GPIO_OUT_MUX_NAND_CS1_VAL                           73
                #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL                        74
                #define QCA_GPIO_OUT_MUX_ETH_TX_ERR_VAL                         75
                #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL                          76
                #define QCA_GPIO_OUT_MUX_CLK_REQ_N_EP_VAL                       77
                #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL                       78
                #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL                           79
                #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL                           80
                #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL                           81
                #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL                           82
                #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL                           83
                #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL                           84
        #endif

        #if (SOC_TYPE & QCA_QCA953X_SOC)
                #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT2_VAL        48
                #define QCA_GPIO_OUT_MUX_SMART_ANT_CTRL_BIT3_VAL        49
                #define QCA_GPIO_OUT_MUX_ATT_LED_VAL                            50
                #define QCA_GPIO_OUT_MUX_PWR_LED_VAL                            51
                #define QCA_GPIO_OUT_MUX_TX_FRAME_VAL                           52
                #define QCA_GPIO_OUT_MUX_RX_CLEAR_INT_VAL                       53
                #define QCA_GPIO_OUT_MUX_LED_NETWORK_EN_VAL                     54
                #define QCA_GPIO_OUT_MUX_LED_POWER_EN_VAL                       55
                #define QCA_GPIO_OUT_MUX_RX_CLEAR_EXTENSION_VAL         78
                #define QCA_GPIO_OUT_MUX_USB_SUSPEND_VAL                        86
                #define QCA_GPIO_OUT_MUX_DDR_DQ_OE_VAL                          88
                #define QCA_GPIO_OUT_MUX_CLK_REQ_N_RC_VAL                       89
                #define QCA_GPIO_OUT_MUX_CLK_OBS0_VAL                           90
                #define QCA_GPIO_OUT_MUX_CLK_OBS1_VAL                           91
                #define QCA_GPIO_OUT_MUX_CLK_OBS2_VAL                           92
                #define QCA_GPIO_OUT_MUX_CLK_OBS3_VAL                           93
                #define QCA_GPIO_OUT_MUX_CLK_OBS4_VAL                           94
                #define QCA_GPIO_OUT_MUX_CLK_OBS5_VAL                           95
                #define QCA_GPIO_OUT_MUX_CLK_OBS6_VAL                           96
        #endif
#endif

/* GPIO_IN_ENABLE0 register (GPIO in signals 0) */
#define QCA_GPIO_IN_EN0_SPI_MISO_SHIFT                          0
#define QCA_GPIO_IN_EN0_SPI_MISO_MASK                           BITS(QCA_GPIO_IN_EN0_SPI_MISO_SHIFT, 8)
#define QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT                        8
#define QCA_GPIO_IN_EN0_LSUART_RXD_MASK                         BITS(QCA_GPIO_IN_EN0_LSUART_RXD_SHIFT ,8)

/* GPIO_IN_ENABLE1 register (GPIO in signals 1) */
#define QCA_GPIO_IN_EN1_I2S_WS_SHIFT                            0
#define QCA_GPIO_IN_EN1_I2S_WS_MASK                                     BITS(QCA_GPIO_IN_EN1_I2S_WS_SHIFT ,8)
#define QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT                        8
#define QCA_GPIO_IN_EN1_I2S_MIC_SD_MASK                         BITS(QCA_GPIO_IN_EN1_I2S_MIC_SD_SHIFT ,8)
#define QCA_GPIO_IN_EN1_I2S_CLK_SHIFT                           16
#define QCA_GPIO_IN_EN1_I2S_CLK_MASK                            BITS(QCA_GPIO_IN_EN1_I2S_CLK_SHIFT ,8)
#define QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT                          24
#define QCA_GPIO_IN_EN1_I2S_MCLK_MASK                           BITS(QCA_GPIO_IN_EN1_I2S_MCLK_SHIFT ,8)

/* GPIO_IN_ENABLE9 register (GPIO in signals 9) */
#define QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT                        16
#define QCA_GPIO_IN_EN9_HSUART_RXD_MASK                         BITS(QCA_GPIO_IN_EN9_HSUART_RXD_SHIFT ,8)
#define QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT                        24
#define QCA_GPIO_IN_EN9_HSUART_CTS_MASK                         BITS(QCA_GPIO_IN_EN9_HSUART_CTS_SHIFT ,8)

/* GPIO_FUNCTION register (GPIO function) */
#define QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT                        0
#define QCA_GPIO_FUNC_GPIO_SRIF_EN_MASK                         (1 << QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT)
#define QCA_GPIO_FUNC_JTAG_DIS_SHIFT                            1
#define QCA_GPIO_FUNC_JTAG_DIS_MASK                                     (1 << QCA_GPIO_FUNC_JTAG_DIS_SHIFT)
#define QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT                         2
#define QCA_GPIO_FUNC_CLK_OBS0_EN_MASK                          (1 << QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT)
#define QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT                         3
#define QCA_GPIO_FUNC_CLK_OBS1_EN_MASK                          (1 << QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT)
#define QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT                         4
#define QCA_GPIO_FUNC_CLK_OBS2_EN_MASK                          (1 << QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT)
#define QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT                         5
#define QCA_GPIO_FUNC_CLK_OBS3_EN_MASK                          (1 << QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT)
#define QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT                         6
#define QCA_GPIO_FUNC_CLK_OBS4_EN_MASK                          (1 << QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT)
#define QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT                         7
#define QCA_GPIO_FUNC_CLK_OBS5_EN_MASK                          (1 << QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT)
#define QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT                         8
#define QCA_GPIO_FUNC_CLK_OBS6_EN_MASK                          (1 << QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT)
#define QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT                         9
#define QCA_GPIO_FUNC_CLK_OBS7_EN_MASK                          (1 << QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT)

/*
 * PLL control registers
 */
#define QCA_PLL_CPU_PLL_CFG_REG                                                 QCA_PLL_BASE_REG + 0x00

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_PLL_CPU_PLL_CFG2_REG                                        QCA_PLL_BASE_REG + 0x04
        #define QCA_PLL_CPU_CLK_CTRL_REG                                        QCA_PLL_BASE_REG + 0x08
        #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG                         QCA_PLL_BASE_REG + 0x10
        #define QCA_PLL_CPU_PLL_DITHER_REG                                      QCA_PLL_BASE_REG + 0x14
        #define QCA_PLL_ETHSW_CLK_CTRL_REG                                      QCA_PLL_BASE_REG + 0x24
        #define QCA_PLL_ETH_XMII_CTRL_REG                                       QCA_PLL_BASE_REG + 0x2C
        #define QCA_PLL_USB_SUSPEND_REG                                         QCA_PLL_BASE_REG + 0x40
        #define QCA_PLL_WLAN_CLK_CTRL_REG                                       QCA_PLL_BASE_REG + 0x44
#else
        #define QCA_PLL_DDR_PLL_CFG_REG                                         QCA_PLL_BASE_REG + 0x04
        #define QCA_PLL_CPU_DDR_CLK_CTRL_REG                            QCA_PLL_BASE_REG + 0x08

        #if (SOC_TYPE & QCA_QCA955X_SOC)
                #define QCA_PLL_PCIE_PLL_CFG_REG                                QCA_PLL_BASE_REG + 0x0C
                #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG             QCA_PLL_BASE_REG + 0x10
                #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG             QCA_PLL_BASE_REG + 0x14
                #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG                QCA_PLL_BASE_REG + 0x18
                #define QCA_PLL_LDO_POWER_CTRL_REG                              QCA_PLL_BASE_REG + 0x1C
                #define QCA_PLL_SWITCH_CLK_SPARE_REG                    QCA_PLL_BASE_REG + 0x20
                #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG                QCA_PLL_BASE_REG + 0x24
                #define QCA_PLL_ETH_XMII_CTRL_REG                               QCA_PLL_BASE_REG + 0x28
                #define QCA_PLL_AUDIO_PLL_CFG_REG                               QCA_PLL_BASE_REG + 0x2C
                #define QCA_PLL_AUDIO_PLL_MODUL_REG                             QCA_PLL_BASE_REG + 0x30
                #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG                QCA_PLL_BASE_REG + 0x34
                #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG                QCA_PLL_BASE_REG + 0x38
                #define QCA_PLL_DDR_PLL_DITHER_REG                              QCA_PLL_BASE_REG + 0x40
                #define QCA_PLL_CPU_PLL_DITHER_REG                              QCA_PLL_BASE_REG + 0x44
                #define QCA_PLL_ETH_SGMII_CTRL_REG                              QCA_PLL_BASE_REG + 0x48
                #define QCA_PLL_ETH_SGMII_SERDES_REG                    QCA_PLL_BASE_REG + 0x4C
                #define QCA_PLL_SLIC_PWM_DIV_REG                                QCA_PLL_BASE_REG + 0x50
        #else
                #define QCA_PLL_CPU_SYNC_REG                                    QCA_PLL_BASE_REG + 0x0C
                #define QCA_PLL_PCIE_PLL_CFG_REG                                QCA_PLL_BASE_REG + 0x10
                #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG             QCA_PLL_BASE_REG + 0x14
                #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG             QCA_PLL_BASE_REG + 0x18
                #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG                QCA_PLL_BASE_REG + 0x1C
                #define QCA_PLL_LDO_POWER_CTRL_REG                              QCA_PLL_BASE_REG + 0x20
                #define QCA_PLL_SWITCH_CLK_CTRL_REG                             QCA_PLL_BASE_REG + 0x24

        #if (SOC_TYPE & QCA_AR9344_SOC)
                #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG                QCA_PLL_BASE_REG + 0x28
        #else
                #define QCA_PLL_CURR_PLL_DITHER_REG                             QCA_PLL_BASE_REG + 0x28
        #endif

                #define QCA_PLL_ETH_XMII_CTRL_REG                               QCA_PLL_BASE_REG + 0x2C
                #define QCA_PLL_AUDIO_PLL_CFG_REG                               QCA_PLL_BASE_REG + 0x30
                #define QCA_PLL_AUDIO_PLL_MODUL_REG                             QCA_PLL_BASE_REG + 0x34
                #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG                QCA_PLL_BASE_REG + 0x38
                #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG                QCA_PLL_BASE_REG + 0x3C
                #define QCA_PLL_BB_PLL_CFG_REG                                  QCA_PLL_BASE_REG + 0x40
                #define QCA_PLL_DDR_PLL_DITHER_REG                              QCA_PLL_BASE_REG + 0x44
                #define QCA_PLL_CPU_PLL_DITHER_REG                              QCA_PLL_BASE_REG + 0x48
        #endif
#endif

/*
 * PLL control registers BIT fields
 */

/* CPU_PLL_CONFIG register (CPU phase lock loop configuration) */
#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT                                 0
        #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK                                  BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 10)
        #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT                                  10
        #define QCA_PLL_CPU_PLL_CFG_NINT_MASK                                   BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
        #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT                                16
        #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK                                 BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
        #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT                                 21
        #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK                                  (1 << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)
        #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT                                23
        #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK                                 BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
#else
        #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT                                 0
        #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK                                  BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 6)
        #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT                                  6
        #define QCA_PLL_CPU_PLL_CFG_NINT_MASK                                   BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6)
        #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT                                12
        #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK                                 BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5)
        #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT                                 17
        #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK                                  BITS(QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT, 2)
        #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT                                19
        #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK                                 BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3)
#endif

#define QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT                                        30
#define QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK                                         (1 << QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT)
#define QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT                                      31
#define QCA_PLL_CPU_PLL_CFG_UPDATING_MASK                                       (1 << QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT)

/* CPU_PLL_CONFIG2 register (CPU phase lock loop configuration, AR933x only) */
#define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT                          0
#define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_MASK                           BITS(QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT, 12)

/* CPU_CLOCK_CONTROL register (CPU clock control, AR933x only) */
#define QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT                                       2
#define QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK                                        (1 << QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT)
#define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT                         5
#define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK                          BITS(QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT, 2)
#define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT                         10
#define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK                          BITS(QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT, 2)
#define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT                         15
#define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK                          BITS(QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT, 2)

/* ETHSW_CLOCK_CONTROL register (Ethernet switch clock control, AR933x only) */
#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT                        3
#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_MASK                         (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT)
#define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT                       4
#define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_MASK                        (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT)

/* ETH_XMII_CONTROL register (Ethernet XMII control) */
#define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT                          0
#define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_MASK                           BITS(QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT, 8)
#define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT                          8
#define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_MASK                           BITS(QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT, 8)
#define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT                          16
#define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_MASK                           BITS(QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT, 8)
#define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT                        24
#define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_MASK                         (1 << QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT)
#define QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT                                        25
#define QCA_PLL_ETH_XMII_CTRL_GIGE_MASK                                         (1 << QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT)
#define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT                            26
#define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_MASK                                     BITS(QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT, 2)
#define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT                            28
#define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_MASK                                     BITS(QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT, 2)
#define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT                           30
#define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_MASK                            (1 << QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT)
#define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT                           31
#define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_MASK                            (1 << QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT)

/* SUSPEND register (USB suspend, AR933x only) */
#define QCA_PLL_USB_SUSPEND_EN_SHIFT                                            0
#define QCA_PLL_USB_SUSPEND_EN_MASK                                                     (1 << QCA_PLL_USB_SUSPEND_EN_SHIFT)
#define QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT                          8
#define QCA_PLL_USB_SUSPEND_RESTART_TIME_MASK                           BITS(QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT, 20)

/* WLAN_CLOCK_CONTROL register (WLAN clock control, AR933x only) */
#define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT                        0
#define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_MASK                         (1 << QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT)
#define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT                            1
#define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_MASK                                     (1 << QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT)
#define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT                           2
#define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_MASK                            (1 << QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT)
#define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT                          3
#define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_MASK                           (1 << QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT)
#define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT                         4
#define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_MASK                          (1 << QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT)
#define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT            8
#define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_MASK                     (1 << QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT)
#define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT         9
#define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_MASK          (1 << QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT)
#define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT          10
#define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_MASK           (1 << QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT)
#define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT                          12
#define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_MASK                           (1 << QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT)

/* DDR_PLL_CONFIG register (DDR PLL configuration) */
#define QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT                                         0
#define QCA_PLL_DDR_PLL_CFG_NFRAC_MASK                                          BITS(QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT, 10)
#define QCA_PLL_DDR_PLL_CFG_NINT_SHIFT                                          10
#define QCA_PLL_DDR_PLL_CFG_NINT_MASK                                           BITS(QCA_PLL_DDR_PLL_CFG_NINT_SHIFT, 6)
#define QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT                                        16
#define QCA_PLL_DDR_PLL_CFG_REFDIV_MASK                                         BITS(QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT, 5)
#define QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT                                         21
#define QCA_PLL_DDR_PLL_CFG_RANGE_MASK                                          BITS(QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT, 2)
#define QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT                                        23
#define QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK                                         BITS(QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT, 3)
#define QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT                                        30
#define QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK                                         (1 << QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT)
#define QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT                                      31
#define QCA_PLL_DDR_PLL_CFG_UPDATING_MASK                                       (1 << QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT)

/* CPU_DDR_CLOCK_CONTROL register (CPU DDR clock control) */
#define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT                       1
#define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_MASK                        (1 << QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT)
#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT           2
#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK            (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT)
#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT           3
#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK            (1 << QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT)
#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT           4
#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK            (1 << QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT)
#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT                     5
#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK                      BITS(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT, 5)
#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT                     10
#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK                      BITS(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT, 5)
#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT                     15
#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK                      BITS(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT, 5)
#define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT       20
#define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK        (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT)
#define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT       21
#define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK        (1 << QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT)
#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT       22
#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_MASK        (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT)
#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT     23
#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_MASK      (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT)
#define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT       24
#define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK        (1 << QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT)

/* DDR_PLL_DITHER register (DDR PLL dither parameter) */
#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT                          0
#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_MASK                           BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT, 10)
#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT                          10
#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK                           BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 10)
#define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_SHIFT                         20
#define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_MASK                          BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 7)
#define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT                         27
#define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_MASK                          BITS(QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT, 4)
#define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT                          31
#define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK                           (1 << QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT)

#if (SOC_TYPE & QCA_AR933X_SOC)
        /* PLL_DITHER_FRAC register (CPU PLL dither FRAC) */
        #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT             0
        #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_MASK              BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT, 10)
        #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT             10
        #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK              BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT, 10)
        #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT    20
        #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_MASK             BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT, 10)

        /* PLL_DITHER register (CPU PLL dither) */
        #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT                 0
        #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK                  BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 14)
        #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT                  31
        #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK                   (1 << QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT)
#else
        /* CPU_PLL_DITHER register (CPU PLL dither parameter) */
        #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT                  0
        #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK                   BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 6)
        #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT                  6
        #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK                   BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
        #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT                 12
        #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK                  BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6)
        #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT                 18
        #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK                  BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6)
        #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT                  31
        #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK                   (1 << QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT)
#endif

/*
 * PLL SRIF registers (not available in AR933x)
 */
#define QCA_PLL_SRIF_CPU_DPLL1_REG                              QCA_PLL_SRIF_BASE_REG + 0x1C0
#define QCA_PLL_SRIF_CPU_DPLL2_REG                              QCA_PLL_SRIF_BASE_REG + 0x1C4
#define QCA_PLL_SRIF_CPU_DPLL3_REG                              QCA_PLL_SRIF_BASE_REG + 0x1C8
#define QCA_PLL_SRIF_AUD_DPLL1_REG                              QCA_PLL_SRIF_BASE_REG + 0x200
#define QCA_PLL_SRIF_AUD_DPLL2_REG                              QCA_PLL_SRIF_BASE_REG + 0x204
#define QCA_PLL_SRIF_AUD_DPLL3_REG                              QCA_PLL_SRIF_BASE_REG + 0x208
#define QCA_PLL_SRIF_DDR_DPLL1_REG                              QCA_PLL_SRIF_BASE_REG + 0x240
#define QCA_PLL_SRIF_DDR_DPLL2_REG                              QCA_PLL_SRIF_BASE_REG + 0x244
#define QCA_PLL_SRIF_DDR_DPLL3_REG                              QCA_PLL_SRIF_BASE_REG + 0x248
#define QCA_PLL_SRIF_PCIE_DPLL1_REG                             QCA_PLL_SRIF_BASE_REG + 0xC00
#define QCA_PLL_SRIF_PCIE_DPLL2_REG                             QCA_PLL_SRIF_BASE_REG + 0xC04
#define QCA_PLL_SRIF_PCIE_DPLL3_REG                             QCA_PLL_SRIF_BASE_REG + 0xC08

/*
 * PLL SRIF registers BIT fields (not available in AR933x)
 */

/* DPLL1 (common for CPU, AUD, DDR and PCIE) */
#define QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT                  0
#define QCA_PLL_SRIF_DPLL1_NFRAC_MASK                   BITS(QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT, 18)
#define QCA_PLL_SRIF_DPLL1_NINT_SHIFT                   18
#define QCA_PLL_SRIF_DPLL1_NINT_MASK                    BITS(QCA_PLL_SRIF_DPLL1_NINT_SHIFT, 9)
#define QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT                 27
#define QCA_PLL_SRIF_DPLL1_REFDIV_MASK                  BITS(QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT, 5)

/* DPLL2 (common for CPU, AUD, DDR and PCIE) */
#if (SOC_TYPE & QCA_QCA953X_SOC)
        #define QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT               0
        #define QCA_PLL_SRIF_DPLL2_RST_TEST_MASK                (1 << QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT)
        #define QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT                1
        #define QCA_PLL_SRIF_DPLL2_SEL_CNT_MASK                 (1 << QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT)
        #define QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT                2
        #define QCA_PLL_SRIF_DPLL2_TEST_IN_MASK                 BITS(QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT, 10)
        #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT    12
        #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_MASK             BITS(QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT, 7)
        #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT                 19
        #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK                  BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 3)
        #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT                 22
        #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK                  (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
        #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT               23
        #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_MASK                (1 << QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT)
        #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT             24
        #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_MASK              (1 << QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT)
        #define QCA_PLL_SRIF_DPLL2_KD_SHIFT                             25
        #define QCA_PLL_SRIF_DPLL2_KD_MASK                              BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 4)
        #define QCA_PLL_SRIF_DPLL2_KI_SHIFT                             29
        #define QCA_PLL_SRIF_DPLL2_KI_MASK                              BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 2)
        #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT              31
        #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK               (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
#else
        #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT                 13
        #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK                  BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2)
        #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT                 16
        #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK                  (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
        #define QCA_PLL_SRIF_DPLL2_KD_SHIFT                             19
        #define QCA_PLL_SRIF_DPLL2_KD_MASK                              BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7)
        #define QCA_PLL_SRIF_DPLL2_KI_SHIFT                             26
        #define QCA_PLL_SRIF_DPLL2_KI_MASK                              BITS(QCA_PLL_SRIF_DPLL2_KI_SHIFT, 4)
        #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT              30
        #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK               (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
        #define QCA_PLL_SRIF_DPLL2_RANGE_SHIFT                  31
        #define QCA_PLL_SRIF_DPLL2_RANGE_MASK                   (1 << QCA_PLL_SRIF_DPLL2_RANGE_SHIFT)
#endif

/* DPLL3 (common for CPU, AUD, DDR and PCIE) */
#define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT    23
#define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_MASK             BITS(QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT, 7)

/*
 * Reset control registers
 */
#define QCA_RST_GENERAL_TIMER1_REG                              QCA_RST_BASE_REG + 0x00
#define QCA_RST_GENERAL_TIMER1_RELOAD_REG               QCA_RST_BASE_REG + 0x04
#define QCA_RST_WATCHDOG_TIMER_CTRL_REG                 QCA_RST_BASE_REG + 0x08
#define QCA_RST_WATCHDOG_TIMER_REG                              QCA_RST_BASE_REG + 0x0C
#define QCA_RST_MISC_INTERRUPT_STATUS_REG               QCA_RST_BASE_REG + 0x10
#define QCA_RST_MISC_INTERRUPT_MASK_REG                 QCA_RST_BASE_REG + 0x14
#define QCA_RST_GLOBALINTERRUPT_STATUS_REG              QCA_RST_BASE_REG + 0x18
#define QCA_RST_RST_REG                                                 QCA_RST_BASE_REG + 0x1C
#define QCA_RST_REVISION_ID_REG                                 QCA_RST_BASE_REG + 0x90
#define QCA_RST_GENERAL_TIMER2_REG                              QCA_RST_BASE_REG + 0x94
#define QCA_RST_GENERAL_TIMER2_RELOAD_REG               QCA_RST_BASE_REG + 0x98
#define QCA_RST_GENERAL_TIMER3_REG                              QCA_RST_BASE_REG + 0x9C
#define QCA_RST_GENERAL_TIMER3_RELOAD_REG               QCA_RST_BASE_REG + 0xA0
#define QCA_RST_GENERAL_TIMER4_REG                              QCA_RST_BASE_REG + 0xA4
#define QCA_RST_GENERAL_TIMER4_RELOAD_REG               QCA_RST_BASE_REG + 0xA8

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_BOOTSTRAP_REG                           QCA_RST_BASE_REG + 0xAC
#else
        #define QCA_RST_BOOTSTRAP_REG                           QCA_RST_BASE_REG + 0xB0
#endif

/*
 * Reset control registers BIT fields
 */

/* RST_BOOTSTRAP (Reset bootstrap) */
#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT                 0
#else
        #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT                 4
#endif
#define QCA_RST_BOOTSTRAP_REF_CLK_MASK                          (1 << QCA_RST_BOOTSTRAP_REF_CLK_SHIFT)
#define QCA_RST_BOOTSTRAP_REF_CLK_25M_VAL                       0x0
#define QCA_RST_BOOTSTRAP_REF_CLK_40M_VAL                       0x1

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT                12
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK                 BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL              0
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL             1
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL             2
        #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT    16
        #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK             (1 << QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT)
        #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT   17
        #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_MASK    (1 << QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT)
        #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT    18
        #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_MASK             (1 << QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT)
#else
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT                0

        /* v2 does not support SDR, but we can read reserved bit and make it universal */
        #if (SOC_TYPE & QCA_QCA953X_SOC)
                #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK         BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
        #else
                #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK         (1 << QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT)
        #endif

        #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL              3
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL             1
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL             0

        #define QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT                2
        #define QCA_RST_BOOTSTRAP_BOOT_SEL_MASK                 (1 << QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT)
        #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT    3
        #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_MASK             (1 << QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT)
        #define QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT               5
        #define QCA_RST_BOOTSTRAP_JTAG_MODE_MASK                (1 << QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT)
#endif

/* RST_RESET */
#define QCA_RST_RESET_I2C_RST_SHIFT                                             0
#define QCA_RST_RESET_I2C_RST_MASK                                              (1 << QCA_RST_RESET_I2C_RST_SHIFT)
#define QCA_RST_RESET_MBOX_RST_SHIFT                                    1
#define QCA_RST_RESET_MBOX_RST_MASK                                             (1 << QCA_RST_RESET_MBOX_RST_SHIFT)
#define QCA_RST_RESET_LUT_RST_SHIFT                                             2
#define QCA_RST_RESET_LUT_RST_MASK                                              (1 << QCA_RST_RESET_LUT_RST_SHIFT)
#define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT               3
#define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_MASK                (1 << QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT)
#define QCA_RST_RESET_USB_PHY_RST_SHIFT                                 4
#define QCA_RST_RESET_USB_PHY_RST_MASK                                  (1 << QCA_RST_RESET_USB_PHY_RST_SHIFT)
#define QCA_RST_RESET_USB_HOST_RST_SHIFT                                5
#define QCA_RST_RESET_USB_HOST_RST_MASK                                 (1 << QCA_RST_RESET_USB_HOST_RST_SHIFT)

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_RESET_SLIC_RST_SHIFT                            6
        #define QCA_RST_RESET_SLIC_RST_MASK                                     (1 << QCA_RST_RESET_SLIC_RST_SHIFT)
#else
        #define QCA_RST_RESET_PCIE_RST_SHIFT                            6
        #define QCA_RST_RESET_PCIE_RST_MASK                                     (1 << QCA_RST_RESET_PCIE_RST_SHIFT)
        #define QCA_RST_RESET_SLIC_RST_SHIFT                            30
        #define QCA_RST_RESET_SLIC_RST_MASK                                     (1 << QCA_RST_RESET_SLIC_RST_SHIFT)
#endif

#define QCA_RST_RESET_PCIE_PHY_RST_SHIFT                                7
#define QCA_RST_RESET_PCIE_PHY_RST_MASK                                 (1 << QCA_RST_RESET_PCIE_PHY_RST_SHIFT)

#if (SOC_TYPE & QCA_QCA955X_SOC)
        #define QCA_RST_RESET_ETH_SGMII_RST_SHIFT                       8
        #define QCA_RST_RESET_ETH_SGMII_RST_MASK                        (1 << QCA_RST_RESET_ETH_SGMII_RST_SHIFT)
#else
        #define QCA_RST_RESET_ETH_SWITCH_RST_SHIFT                      8
        #define QCA_RST_RESET_ETH_SWITCH_RST_MASK                       (1 << QCA_RST_RESET_ETH_SWITCH_RST_SHIFT)
#endif

#define QCA_RST_RESET_GE0_MAC_RST_SHIFT                                 9
#define QCA_RST_RESET_GE0_MAC_RST_MASK                                  (1 << QCA_RST_RESET_GE0_MAC_RST_SHIFT)
#define QCA_RST_RESET_HOST_DMA_INT_SHIFT                                10
#define QCA_RST_RESET_HOST_DMA_INT_MASK                                 (1 << QCA_RST_RESET_HOST_DMA_INT_SHIFT)

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_RESET_WLAN_RST_SHIFT                            11
        #define QCA_RST_RESET_WLAN_RST_MASK                                     (1 << QCA_RST_RESET_WLAN_RST_SHIFT)
#else
        #define QCA_RST_RESET_USB_PHY_ARST_SHIFT                        11
        #define QCA_RST_RESET_USB_PHY_ARST_MASK                         (1 << QCA_RST_RESET_USB_PHY_ARST_SHIFT)
#endif

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT                     14
        #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK                      (1 << QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
#else
        #if (SOC_TYPE & QCA_QCA955X_SOC)
                #define QCA_RST_RESET_ETH_SGMII_ARST_SHIFT              12
                #define QCA_RST_RESET_ETH_SGMII_ARST_MASK               (1 << QCA_RST_RESET_ETH_SGMII_ARST_SHIFT)
        #else
                #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT             12
                #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK              (1 << QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
        #endif

        #define QCA_RST_RESET_NANDF_RST_SHIFT                           14
        #define QCA_RST_RESET_NANDF_RST_MASK                            (1 << QCA_RST_RESET_NANDF_RST_SHIFT)
#endif

#define QCA_RST_RESET_GE1_MAC_RST_SHIFT                                 13
#define QCA_RST_RESET_GE1_MAC_RST_MASK                                  (1 << QCA_RST_RESET_GE1_MAC_RST_SHIFT)
#define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT                  15
#define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_MASK                   (1 << QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT)
#define QCA_RST_RESET_DDR_RST_SHIFT                                             16
#define QCA_RST_RESET_DDR_RST_MASK                                              (1 << QCA_RST_RESET_DDR_RST_SHIFT)
#define QCA_RST_RESET_HSUART_RST_SHIFT                                  17
#define QCA_RST_RESET_HSUART_RST_MASK                                   (1 << QCA_RST_RESET_HSUART_RST_SHIFT)
#define QCA_RST_RESET_PCIEEP_RST_SHIFT                                  18
#define QCA_RST_RESET_PCIEEP_RST_MASK                                   (1 << QCA_RST_RESET_PCIEEP_RST_SHIFT)
#define QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT                    19
#define QCA_RST_RESET_HOST_DMA_RST_INT_MASK                             (1 << QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT)
#define QCA_RST_RESET_CPU_COLD_RST_SHIFT                                20
#define QCA_RST_RESET_CPU_COLD_RST_MASK                                 (1 << QCA_RST_RESET_CPU_COLD_RST_SHIFT)
#define QCA_RST_RESET_CPU_NMI_SHIFT                                             21
#define QCA_RST_RESET_CPU_NMI_MASK                                              (1 << QCA_RST_RESET_CPU_NMI_SHIFT)
#define QCA_RST_RESET_GE0_MDIO_RST_SHIFT                                22
#define QCA_RST_RESET_GE0_MDIO_RST_MASK                                 (1 << QCA_RST_RESET_GE0_MDIO_RST_SHIFT)
#define QCA_RST_RESET_GE1_MDIO_RST_SHIFT                                23
#define QCA_RST_RESET_GE1_MDIO_RST_MASK                                 (1 << QCA_RST_RESET_GE1_MDIO_RST_SHIFT)
#define QCA_RST_RESET_FULL_CHIP_RST_SHIFT                               24
#define QCA_RST_RESET_FULL_CHIP_RST_MASK                                (1 << QCA_RST_RESET_FULL_CHIP_RST_SHIFT)
#define QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT                    25
#define QCA_RST_RESET_CHECKSUM_ACC_RST_MASK                             (1 << QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT)
#define QCA_RST_RESET_PCIEEP_RST_INT_SHIFT                              26
#define QCA_RST_RESET_PCIEEP_RST_INT_MASK                               (1 << QCA_RST_RESET_PCIEEP_RST_INT_SHIFT)
#define QCA_RST_RESET_RTC_RST_SHIFT                                             27
#define QCA_RST_RESET_RTC_RST_MASK                                              (1 << QCA_RST_RESET_RTC_RST_SHIFT)
#define QCA_RST_RESET_EXT_RST_SHIFT                                             28
#define QCA_RST_RESET_EXT_RST_MASK                                              (1 << QCA_RST_RESET_EXT_RST_SHIFT)

#if (SOC_TYPE & QCA_AR934X_SOC) | \
        (SOC_TYPE & QCA_QCA955X_SOC)
        #define QCA_RST_RESET_HOST_DMA_RST_SHIFT                        29
        #define QCA_RST_RESET_HOST_DMA_RST_MASK                         (1 << QCA_RST_RESET_HOST_DMA_RST_SHIFT)
#else
        #define QCA_RST_RESET_USB_EXT_PWR_SHIFT                         29
        #define QCA_RST_RESET_USB_EXT_PWR_MASK                          (1 << QCA_RST_RESET_USB_EXT_PWR_SHIFT)
#endif

#define QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT                 31
#define QCA_RST_RESET_HOST_DMA_RST_STATUS_MASK                  (1 << QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT)

/* RST_REVISION_ID (Chip revision ID) */
#define QCA_RST_REVISION_ID_MAJOR_SHIFT                         4
#define QCA_RST_REVISION_ID_MAJOR_MASK                          BITS(QCA_RST_REVISION_ID_MAJOR_SHIFT, 12)

#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_REVISION_ID_REV_SHIFT                   0
        #define QCA_RST_REVISION_ID_REV_MASK                    BITS(QCA_RST_REVISION_ID_REV_SHIFT, 2)
#else
        #define QCA_RST_REVISION_ID_REV_SHIFT                   0
        #define QCA_RST_REVISION_ID_REV_MASK                    BITS(QCA_RST_REVISION_ID_REV_SHIFT, 4)
#endif

#define QCA_RST_REVISION_ID_MAJOR_AR9330_VAL            0x0110
#define QCA_RST_REVISION_ID_MAJOR_AR9331_VAL            0x1110
#define QCA_RST_REVISION_ID_MAJOR_AR9341_VAL            0x0120
#define QCA_RST_REVISION_ID_MAJOR_AR9344_VAL            0x2120
#define QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL           0x0140
#define QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL        0x0160
#define QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL           0x1130

/*
 * RTC registers
 */
#define QCA_RTC_RST_CTRL_REG                                    QCA_RTC_BASE_REG + 0x00
#define QCA_RTC_XTAL_CTRL_REG                                   QCA_RTC_BASE_REG + 0x04
#define QCA_RTC_WLAN_PLL_CTRL_REG                               QCA_RTC_BASE_REG + 0x14
#define QCA_RTC_PLL_SETTLE_REG                                  QCA_RTC_BASE_REG + 0x18
#define QCA_RTC_XTAL_SETTLE_REG                                 QCA_RTC_BASE_REG + 0x1C
#define QCA_RTC_CLK_OUT_REG                                             QCA_RTC_BASE_REG + 0x20
#define QCA_RTC_RST_CAUSE_REG                                   QCA_RTC_BASE_REG + 0x28
#define QCA_RTC_SYS_SLEEP_REG                                   QCA_RTC_BASE_REG + 0x2C
#define QCA_RTC_KEEP_AWAKE_REG                                  QCA_RTC_BASE_REG + 0x34
#define QCA_RTC_DERIVED_RTC_CLK_REG                             QCA_RTC_BASE_REG + 0x38
#define QCA_RTC_PLL_CTRL2_REG                                   QCA_RTC_BASE_REG + 0x3C
#define QCA_RTC_SYNC_RST_REG                                    QCA_RTC_BASE_REG + 0x40
#define QCA_RTC_SYNC_STATUS_REG                                 QCA_RTC_BASE_REG + 0x44
#define QCA_RTC_SYNC_DERIVED_REG                                QCA_RTC_BASE_REG + 0x48
#define QCA_RTC_SYNC_FORCE_WAKE_REG                             QCA_RTC_BASE_REG + 0x4C
#define QCA_RTC_INTERRUPT_CAUSE_REG                             QCA_RTC_BASE_REG + 0x50
#define QCA_RTC_INTERRUPT_EN_REG                                QCA_RTC_BASE_REG + 0x54
#define QCA_RTC_INTERRUPT_MASK_REG                              QCA_RTC_BASE_REG + 0x58

/*
 * RTC registers BIT fields
 */

/* RESET_CONTROL register (RTC reset control) */
#define QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT             0
#define QCA_RTC_RST_CTRL_MAC_WARM_RST_MASK              (1 << QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT)
#define QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT             1
#define QCA_RTC_RST_CTRL_MAC_COLD_RST_MASK              (1 << QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT)
#define QCA_RTC_RST_CTRL_WARM_RST_SHIFT                 2
#define QCA_RTC_RST_CTRL_WARM_RST_MASK                  (1 << QCA_RTC_RST_CTRL_WARM_RST_SHIFT)
#define QCA_RTC_RST_CTRL_COLD_RST_SHIFT                 3
#define QCA_RTC_RST_CTRL_COLD_RST_MASK                  (1 << QCA_RTC_RST_CTRL_COLD_RST_SHIFT)

/* RESET_CAUSE register (Reset cause) */
#define QCA_RTC_RST_CAUSE_LAST_SHIFT                    0
#define QCA_RTC_RST_CAUSE_LAST_MASK                             BITS(QCA_RTC_RST_CAUSE_LAST_SHIFT, 2)

#define QCA_RTC_RST_CAUSE_LAST_HARD_VAL                 0
#define QCA_RTC_RST_CAUSE_LAST_COLD_VAL                 1
#define QCA_RTC_RST_CAUSE_LAST_WARM_VAL                 2

/* RTC_SYNC_REGISTER register (RTC reset, force sleep and force wakeup) */
#define QCA_RTC_SYNC_RST_RESET_SHIFT                    0
#define QCA_RTC_SYNC_RST_RESET_MASK                             (1 << QCA_RTC_SYNC_RST_RESET_SHIFT)

/* RTC_SYNC_STATUS register (RTC sync/sleep status) */
#define QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT              0
#define QCA_RTC_SYNC_STATUS_SHUTDOWN_MASK               (1 << QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT)
#define QCA_RTC_SYNC_STATUS_ON_SHIFT                    1
#define QCA_RTC_SYNC_STATUS_ON_MASK                             (1 << QCA_RTC_SYNC_STATUS_ON_SHIFT)
#define QCA_RTC_SYNC_STATUS_SLEEP_SHIFT                 2
#define QCA_RTC_SYNC_STATUS_SLEEP_MASK                  (1 << QCA_RTC_SYNC_STATUS_SLEEP_SHIFT)
#define QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT                3
#define QCA_RTC_SYNC_STATUS_WAKEUP_MASK                 (1 << QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT)
#define QCA_RTC_SYNC_STATUS_WRESET_SHIFT                4
#define QCA_RTC_SYNC_STATUS_WRESET_MASK                 (1 << QCA_RTC_SYNC_STATUS_WRESET_SHIFT)
#define QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT  5
#define QCA_RTC_SYNC_STATUS_PLL_CHANGING_MASK   (1 << QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT)

/* RTC_SYNC_FORCE_WAKE register (RTC force wake) */
#define QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT                0
#define QCA_RTC_SYNC_FORCE_WAKE_EN_MASK                 (1 << QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT)
#define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT   1
#define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_MASK    (1 << QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT)

/*
 * SPI serial flash registers
 */
#define QCA_SPI_FUNC_SEL_REG                            QCA_FLASH_BASE_REG + 0x00
#define QCA_SPI_CTRL_REG                                        QCA_FLASH_BASE_REG + 0x04
#define QCA_SPI_IO_CTRL_REG                                     QCA_FLASH_BASE_REG + 0x08
#define QCA_SPI_READ_DATA_REG                           QCA_FLASH_BASE_REG + 0x0C
#define QCA_SPI_SHIFT_DATAOUT_REG                       QCA_FLASH_BASE_REG + 0x10
#define QCA_SPI_SHIFT_CNT_REG                           QCA_FLASH_BASE_REG + 0x14
#define QCA_SPI_SHIFT_DATAIN_REG                        QCA_FLASH_BASE_REG + 0x18

/*
 * SPI serial flash registers BIT fields
 */

/* SPI_FUNC_SELECT register (SPI function select) */
#define QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT         0
#define QCA_SPI_FUNC_SEL_FUNC_SEL_MASK          (1 << QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT)

/* SPI_CONTROL register (SPI control) */
#define QCA_SPI_CTRL_CLK_DIV_SHIFT                      0
#define QCA_SPI_CTRL_CLK_DIV_MASK                       BITS(QCA_SPI_CTRL_CLK_DIV_SHIFT, 6)
#define QCA_SPI_CTRL_REMAP_DIS_SHIFT            6
#define QCA_SPI_CTRL_REMAP_DIS_MASK                     (1 << QCA_SPI_CTRL_REMAP_DIS_SHIFT)
#define QCA_SPI_CTRL_SPI_RELOCATE_SHIFT         7
#define QCA_SPI_CTRL_SPI_RELOCATE_MASK          (1 << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT)
#define QCA_SPI_CTRL_TSHSL_CNT_SHIFT            8
#define QCA_SPI_CTRL_TSHSL_CNT_MASK                     BITS(QCA_SPI_CTRL_TSHSL_CNT_SHIFT, 6)

/* SPI_IO_CONTROL register (SPI I/O control) */
#define QCA_SPI_IO_CTRL_IO_DO_SHIFT                     0
#define QCA_SPI_IO_CTRL_IO_DO_MASK                      (1 << QCA_SPI_IO_CTRL_IO_DO_SHIFT)
#define QCA_SPI_IO_CTRL_IO_CLK_SHIFT            8
#define QCA_SPI_IO_CTRL_IO_CLK_MASK                     (1 << QCA_SPI_IO_CTRL_IO_CLK_SHIFT)
#define QCA_SPI_IO_CTRL_IO_CS0_SHIFT            16
#define QCA_SPI_IO_CTRL_IO_CS0_MASK                     (1 << QCA_SPI_IO_CTRL_IO_CS0_SHIFT)
#define QCA_SPI_IO_CTRL_IO_CS1_SHIFT            17
#define QCA_SPI_IO_CTRL_IO_CS1_MASK                     (1 << QCA_SPI_IO_CTRL_IO_CS1_SHIFT)
#define QCA_SPI_IO_CTRL_IO_CS2_SHIFT            18
#define QCA_SPI_IO_CTRL_IO_CS2_MASK                     (1 << QCA_SPI_IO_CTRL_IO_CS2_SHIFT)

/* SPI_SHIFT_CNT_ADDR register (SPI content to shift out or in) */
#define QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT                0
#define QCA_SPI_SHIFT_CNT_BITS_CNT_MASK                 BITS(QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT, 7)
#define QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT               26
#define QCA_SPI_SHIFT_CNT_TERMINATE_MASK                (1 << QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT)
#define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT             27
#define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_MASK              (1 << QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT)
#define QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT                28
#define QCA_SPI_SHIFT_CNT_CHNL_CS0_MASK                 (1 << QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT)
#define QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT                29
#define QCA_SPI_SHIFT_CNT_CHNL_CS1_MASK                 (1 << QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT)
#define QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT                30
#define QCA_SPI_SHIFT_CNT_CHNL_CS2_MASK                 (1 << QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT)
#define QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT                31
#define QCA_SPI_SHIFT_CNT_SHIFT_EN_MASK                 (1 << QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT)

/*
 * Other useful defines
 */

/* Magic flag for indication that PLL/clocks config is stored in FLASH */
#define QCA_PLL_IN_FLASH_MAGIC          0x504C4C73

/* Maximum DRAM size: 256 MB */
#define QCA_DRAM_MAX_SIZE_VAL           (256 * 1024 * 1024)

/*
 * Functions
 */
#ifndef __ASSEMBLY__
inline u32 qca_xtal_is_40mhz(void);
void   qca_soc_name_rev(char *buf);
void   qca_full_chip_reset(void);
void   qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk, u32 *spi_clk, u32 *ref_clk);
void   qca_sf_bulk_erase(u32 bank);
void   qca_sf_write_page(u32 bank, u32 address, u32 length, u8 *data);
u32    qca_sf_sect_erase(u32 bank, u32 address, u32 sect_size, u8 erase_cmd);
u32    qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_cmd);
u32    qca_sf_jedec_id(u32 bank);
u32    qca_dram_type(void);
u32    qca_dram_size(void);
u32    qca_dram_cas_lat(void);
u32    qca_dram_ddr_width(void);
void   qca_dram_init(void);
#endif /* !__ASSEMBLY__ */

/*
 * Read, write, set and clear macros
 */
#define qca_soc_reg_read(_addr)                 *(volatile unsigned int *)(KSEG1ADDR(_addr))
#define qca_soc_reg_write(_addr, _val)  ((*(volatile unsigned int *)KSEG1ADDR(_addr)) = (_val))

#define qca_soc_reg_read_set(_addr, _mask)      \
                qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) | (_mask)))

#define qca_soc_reg_read_clear(_addr, _mask)    \
                qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) & ~(_mask)))

#endif /* _QCA_SOC_COMMON_H_ */