u-boot/include/soc/qca_dram.h

   1 /*
   2  * Qualcomm/Atheros WiSoCs DRAM related functions and defines
   3  *
   4  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0
   7  */
   8
   9 #ifndef _QCA_DRAM_H_
  10 #define _QCA_DRAM_H_
  11
  12 /*
  13  * Prepare DDR SDRAM mode register value
  14  * For now use always burst length == 8
  15  */
  16 #define DDR_SDRAM_MR_BURST_LEN_SHIFT                    0
  17 #define DDR_SDRAM_MR_BURST_LEN_MASK                             BITS(DDR_SDRAM_MR_BURST_LEN_SHIFT, 3)
  18 #define DDR_SDRAM_MR_BURST_INTERLEAVE_SHIFT             3
  19 #define DDR_SDRAM_MR_BURST_INTERLEAVE_MASK              (1 << DDR_SDRAM_MR_BURST_INTERLEAVE_SHIFT)
  20 #define DDR_SDRAM_MR_CAS_LAT_SHIFT                              4
  21 #define DDR_SDRAM_MR_CAS_LAT_MASK                               BITS(DDR_SDRAM_MR_CAS_LAT_SHIFT, 3)
  22 #define DDR_SDRAM_MR_DLL_RESET_SHIFT                    8
  23 #define DDR_SDRAM_MR_DLL_RESET_MASK                             (1 << DDR_SDRAM_MR_DLL_RESET_SHIFT)
  24 #define DDR_SDRAM_MR_WR_RECOVERY_SHIFT                  9
  25 #define DDR_SDRAM_MR_WR_RECOVERY_MASK                   BITS(DDR_SDRAM_MR_WR_RECOVERY_SHIFT, 3)
  26
  27 #define _ddr_sdram_mr_val(_burst_i, \
  28                                                   _cas_lat, \
  29                                                   _dll_res, \
  30                                                   _wr_rcov) \
  31                                                                         \
  32         ((0x3            << DDR_SDRAM_MR_BURST_LEN_SHIFT)   & DDR_SDRAM_MR_BURST_LEN_MASK)   |\
  33         ((_cas_lat       << DDR_SDRAM_MR_CAS_LAT_SHIFT)     & DDR_SDRAM_MR_CAS_LAT_MASK)     |\
  34         ((_dll_res       << DDR_SDRAM_MR_DLL_RESET_SHIFT)   & DDR_SDRAM_MR_DLL_RESET_MASK)   |\
  35         (((_wr_rcov - 1) << DDR_SDRAM_MR_WR_RECOVERY_SHIFT) & DDR_SDRAM_MR_WR_RECOVERY_MASK) |\
  36         ((_burst_i       << DDR_SDRAM_MR_BURST_INTERLEAVE_SHIFT) & DDR_SDRAM_MR_BURST_INTERLEAVE_MASK)
  37
  38 /* Prepare DDR SDRAM extended mode register value */
  39 #define DDR_SDRAM_EMR_DLL_EN_SHIFT                              0
  40 #define DDR_SDRAM_EMR_DLL_EN_MASK                               (1 << DDR_SDRAM_EMR_DLL_EN_SHIFT)
  41 #define DDR_SDRAM_EMR_WEAK_STRENGTH_SHIFT               1
  42 #define DDR_SDRAM_EMR_WEAK_STRENGTH_MASK                (1 << DDR_SDRAM_EMR_WEAK_STRENGTH_SHIFT)
  43 #define DDR_SDRAM_EMR_OCD_PRG_SHIFT                             7
  44 #define DDR_SDRAM_EMR_OCD_PRG_MASK                              BITS(DDR_SDRAM_EMR_OCD_PRG_SHIFT, 3)
  45 #define DDR_SDRAM_EMR_OCD_EXIT_VAL                              0
  46 #define DDR_SDRAM_EMR_OCD_DEFAULT_VAL                   7
  47 #define DDR_SDRAM_EMR_NDQS_DIS_SHIFT                    10
  48 #define DDR_SDRAM_EMR_NDQS_DIS_MASK                             (1 << DDR_SDRAM_EMR_NDQS_DIS_SHIFT)
  49 #define DDR_SDRAM_EMR_RDQS_EN_SHIFT                             11
  50 #define DDR_SDRAM_EMR_RDQS_EN_MASK                              (1 << DDR_SDRAM_EMR_RDQS_EN_SHIFT)
  51 #define DDR_SDRAM_EMR_OBUF_DIS_SHIFT                    12
  52 #define DDR_SDRAM_EMR_OBUF_DIS_MASK                             (1 << DDR_SDRAM_EMR_OBUF_DIS_SHIFT)
  53
  54 #define _ddr_sdram_emr_val(_dll_dis,  \
  55                                                    _drv_weak, \
  56                                                    _ocd_prg,  \
  57                                                    _ndqs_dis, \
  58                                                    _rdqs_en,  \
  59                                                    _obuf_dis) \
  60                                                                           \
  61         ((_dll_dis  << DDR_SDRAM_EMR_DLL_EN_SHIFT)   & DDR_SDRAM_EMR_DLL_EN_MASK)   |\
  62         ((_ocd_prg  << DDR_SDRAM_EMR_OCD_PRG_SHIFT)  & DDR_SDRAM_EMR_OCD_PRG_MASK)  |\
  63         ((_ndqs_dis << DDR_SDRAM_EMR_NDQS_DIS_SHIFT) & DDR_SDRAM_EMR_NDQS_DIS_MASK) |\
  64         ((_rdqs_en  << DDR_SDRAM_EMR_RDQS_EN_SHIFT)  & DDR_SDRAM_EMR_RDQS_EN_MASK)  |\
  65         ((_obuf_dis << DDR_SDRAM_EMR_OBUF_DIS_SHIFT) & DDR_SDRAM_EMR_OBUF_DIS_MASK) |\
  66         ((_drv_weak << DDR_SDRAM_EMR_WEAK_STRENGTH_SHIFT) & DDR_SDRAM_EMR_WEAK_STRENGTH_MASK)
  67
  68 /* Prepare DDR SDRAM extended mode register 2 value */
  69 #define DDR_SDRAM_EMR2_PASR_SHIFT                               0
  70 #define DDR_SDRAM_EMR2_PASR_MASK                                BITS(DDR_SDRAM_EMR2_PASR_SHIFT, 3)
  71 #define DDR_SDRAM_EMR2_DCC_EN_SHIFT                             3
  72 #define DDR_SDRAM_EMR2_DCC_EN_MASK                              (1 << DDR_SDRAM_EMR2_DCC_EN_SHIFT)
  73 #define DDR_SDRAM_EMR2_SRF_EN_SHIFT                             7
  74 #define DDR_SDRAM_EMR2_SRF_EN_MASK                              (1 << DDR_SDRAM_EMR2_SRF_EN_SHIFT)
  75
  76 #define _ddr_sdram_emr2_val(_pasr,   \
  77                                                         _dcc_en, \
  78                                                         _srf_en) \
  79                                                                          \
  80         ((_pasr   << DDR_SDRAM_EMR2_PASR_SHIFT)   & DDR_SDRAM_EMR2_PASR_MASK)   |\
  81         ((_dcc_en << DDR_SDRAM_EMR2_DCC_EN_SHIFT) & DDR_SDRAM_EMR2_DCC_EN_MASK) |\
  82         ((_srf_en << DDR_SDRAM_EMR2_SRF_EN_SHIFT) & DDR_SDRAM_EMR2_SRF_EN_MASK)
  83
  84 /*
  85  * DDR timing related controller register values
  86  */
  87
  88 /* DDR_CONFIG */
  89 #define _qca_ddr_cfg_reg_val(_tras,  \
  90                                                          _trcd,  \
  91                                                          _trp,   \
  92                                                          _trrd,  \
  93                                                          _trfc,  \
  94                                                          _tmrd,  \
  95                                                          _cas,   \
  96                                                          _opage) \
  97                                                                          \
  98         ((_tras  << QCA_DDR_CFG_TRAS_SHIFT)       & QCA_DDR_CFG_TRAS_MASK)       |\
  99         ((_trcd  << QCA_DDR_CFG_TRCD_SHIFT)       & QCA_DDR_CFG_TRCD_MASK)       |\
 100         ((_trp   << QCA_DDR_CFG_TRP_SHIFT)        & QCA_DDR_CFG_TRP_MASK)        |\
 101         ((_trrd  << QCA_DDR_CFG_TRRD_SHIFT)       & QCA_DDR_CFG_TRRD_MASK)       |\
 102         ((_trfc  << QCA_DDR_CFG_TRFC_SHIFT)       & QCA_DDR_CFG_TRFC_MASK)       |\
 103         ((_tmrd  << QCA_DDR_CFG_TMRD_SHIFT)       & QCA_DDR_CFG_TMRD_MASK)       |\
 104         ((_cas   << QCA_DDR_CFG_CAS_3LSB_SHIFT)   & QCA_DDR_CFG_CAS_3LSB_MASK)   |\
 105         ((_opage << QCA_DDR_CFG_PAGE_CLOSE_SHIFT) & QCA_DDR_CFG_PAGE_CLOSE_MASK) |\
 106         (((_cas & 0x8) >> 3) << QCA_DDR_CFG_CAS_MSB_SHIFT)
 107
 108 /* DDR_CONFIG2 */
 109 #define _qca_ddr_cfg2_reg_val(_burst_type, \
 110                                                           _ctrl_oe_en, \
 111                                                           _phase_sel,  \
 112                                                           _cke,        \
 113                                                           _twr,        \
 114                                                           _trtw,       \
 115                                                           _trtp,       \
 116                                                           _twtr,       \
 117                                                           _gate_lat,   \
 118                                                           _half_width) \
 119                                                                                    \
 120         (0x8          << QCA_DDR_CFG2_BURST_LEN_SHIFT)                                  |\
 121         ((_burst_type << QCA_DDR_CFG2_BURST_TYPE_SHIFT) & QCA_DDR_CFG2_BURST_TYPE_MASK) |\
 122         ((_ctrl_oe_en << QCA_DDR_CFG2_CTRL_OE_EN_SHIFT) & QCA_DDR_CFG2_CTRL_OE_EN_MASK) |\
 123         ((_phase_sel  << QCA_DDR_CFG2_PHASE_SEL_SHIFT)  & QCA_DDR_CFG2_PHASE_SEL_MASK)  |\
 124         ((_cke        << QCA_DDR_CFG2_CKE_SHIFT)        & QCA_DDR_CFG2_CKE_MASK)        |\
 125         ((_twr        << QCA_DDR_CFG2_TWR_SHIFT)        & QCA_DDR_CFG2_TWR_MASK)        |\
 126         ((_trtw       << QCA_DDR_CFG2_TRTW_SHIFT)       & QCA_DDR_CFG2_TRTW_MASK)       |\
 127         ((_trtp       << QCA_DDR_CFG2_TRTP_SHIFT)       & QCA_DDR_CFG2_TRTP_MASK)       |\
 128         ((_twtr       << QCA_DDR_CFG2_TWTR_SHIFT)       & QCA_DDR_CFG2_TWTR_MASK)       |\
 129         ((_half_width << QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT)    & QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK) |\
 130         ((_gate_lat   << QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT) & QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK)
 131
 132 /* DDR_DDR2_CONFIG */
 133 #define _qca_ddr_ddr2_cfg_reg_val(_ddr2_en, \
 134                                                                   _tfaw,    \
 135                                                                   _twl)     \
 136                                                                                         \
 137         ((_ddr2_en << QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT)   & QCA_DDR_DDR2_CFG_DDR2_EN_MASK)   |\
 138         ((_tfaw    << QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT) & QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK) |\
 139         ((_twl     << QCA_DDR_DDR2_CFG_DDR2_TWL_SHIFT)  & QCA_DDR_DDR2_CFG_DDR2_TWL_MASK)
 140
 141 /*
 142  * DDR control functions
 143  */
 144
 145 /* Force MRS (mode register set) */
 146 static inline void qca_dram_force_mrs(void)
 147 {
 148         qca_soc_reg_write(QCA_DDR_CTRL_REG,
 149                                           QCA_DDR_CTRL_FORCE_MRS_MASK);
 150 }
 151
 152 /* Force EMRS (extended mode register set) */
 153 static inline void qca_dram_force_emrs(void)
 154 {
 155         qca_soc_reg_write(QCA_DDR_CTRL_REG,
 156                                           QCA_DDR_CTRL_FORCE_EMRS_MASK);
 157 }
 158
 159 /* Force EMR2S (extended mode register 2 set) */
 160 static inline void qca_dram_force_emr2s(void)
 161 {
 162         qca_soc_reg_write(QCA_DDR_CTRL_REG,
 163                                           QCA_DDR_CTRL_FORCE_EMR2S_MASK);
 164 }
 165
 166 /* Force EMR3S (extended mode register 3 set) */
 167 static inline void qca_dram_force_emr3s(void)
 168 {
 169         qca_soc_reg_write(QCA_DDR_CTRL_REG,
 170                                           QCA_DDR_CTRL_FORCE_EMR3S_MASK);
 171 }
 172
 173 /* Force auto refresh */
 174 static inline void qca_dram_force_aref(void)
 175 {
 176         qca_soc_reg_write(QCA_DDR_CTRL_REG,
 177                                           QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK);
 178 }
 179
 180 /* Force precharge all */
 181 static inline void qca_dram_force_preall(void)
 182 {
 183         qca_soc_reg_write(QCA_DDR_CTRL_REG,
 184                                           QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK);
 185 }
 186
 187 /*
 188  * DDR setup related functions
 189  */
 190
 191 /* Sets DDR mode register value and issue MRS update */
 192 static inline void qca_dram_set_mr(u32 value)
 193 {
 194         qca_soc_reg_write(QCA_DDR_MR_REG, value);
 195         qca_dram_force_mrs();
 196 }
 197
 198 /* Sets DDR extended mode register value and issue EMRS update */
 199 static inline void qca_dram_set_emr(u32 value)
 200 {
 201         qca_soc_reg_write(QCA_DDR_EMR_REG, value);
 202         qca_dram_force_emrs();
 203 }
 204
 205 /* Sets DDR extended mode register 2 value and issue EMR2S update */
 206 static inline void qca_dram_set_emr2(u32 value)
 207 {
 208         qca_soc_reg_write(QCA_DDR_EMR2_REG, value);
 209         qca_dram_force_emr2s();
 210 }
 211
 212 /* Sets DDR extended mode register 3 value and issue EMR3S update */
 213 static inline void qca_dram_set_emr3(u32 value)
 214 {
 215         qca_soc_reg_write(QCA_DDR_EMR3_REG, value);
 216         qca_dram_force_emr3s();
 217 }
 218
 219 /* Enables DDR refresh and sets refresh period based on XTAL */
 220 static inline void qca_dram_set_en_refresh(void)
 221 {
 222         /*
 223          * Enable DDR refresh and setup refresh period:
 224          * 1. We assume 7.8 us maximum average period refresh interval
 225          * 2. 7.8 us ~= 0.1282 MHz
 226          * 3. For 25 MHz XTAL: (25 / 0.1282) ~= 195
 227          * 4. For 40 MHz XTAL: (40 / 0.1282) ~= 312
 228          */
 229         if (qca_xtal_is_40mhz()) {
 230                 qca_soc_reg_write(QCA_DDR_REFRESH_REG,
 231                                                   QCA_DDR_REFRESH_EN_MASK
 232                                                   | (312 << QCA_DDR_REFRESH_PERIOD_SHIFT));
 233         } else {
 234                 qca_soc_reg_write(QCA_DDR_REFRESH_REG,
 235                                                   QCA_DDR_REFRESH_EN_MASK
 236                                                   | (195 << QCA_DDR_REFRESH_PERIOD_SHIFT));
 237         }
 238 }
 239
 240 #endif /* _QCA_DRAM_H_ */