u-boot/include/soc/ar933x_pll_init.h

   1 /*
   2  * Helper defines and macros related with
   3  * PLL and clocks configurations for
   4  * Qualcomm/Atheros AR933x WiSoC
   5  *
   6  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   7  *
   8  * SPDX-License-Identifier: GPL-2.0
   9  */
  10
  11 #ifndef _AR933X_PLL_INIT_H_
  12 #define _AR933X_PLL_INIT_H_
  13
  14 #include <soc/qca_soc_common.h>
  15
  16 /* CPU_PLL_CONFIG */
  17 #define _ar933x_cpu_pll_cfg_reg_val(_nint,   \
  18                                     _refdiv, \
  19                                     _range,  \
  20                                     _outdiv) \
  21                                              \
  22         ((_nint   << QCA_PLL_CPU_PLL_CFG_NINT_SHIFT)   & QCA_PLL_CPU_PLL_CFG_NINT_MASK)   |\
  23         ((_refdiv << QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK) |\
  24         ((_range  << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)  & QCA_PLL_CPU_PLL_CFG_RANGE_MASK)  |\
  25         ((_outdiv << QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK)
  26
  27 /* CPU_CLOCK_CONTROL */
  28 #define _ar933x_cpu_clk_ctrl_reg_val(_cpudiv, \
  29                                      _ddrdiv, \
  30                                      _ahbdiv) \
  31                                               \
  32         (((_cpudiv - 1) << QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT) &\
  33          QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK) |\
  34         (((_ddrdiv - 1) << QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT) &\
  35          QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK) |\
  36         (((_ahbdiv - 1) << QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT) &\
  37          QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK)
  38
  39 /* PLL_DITHER_FRAC */
  40 #define _ar933x_cpu_pll_dither_frac_reg_val(_nfracmin)  \
  41         ((_nfracmin << QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT) &\
  42          QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK)
  43
  44 /* SPI_CONTROL_ADDR */
  45 #define _ar933x_spi_ctrl_addr_reg_val(_clk_div,   \
  46                                       _remap_dis, \
  47                                       _reloc_spi) \
  48                                                   \
  49         ((((_clk_div / 2) - 1) << QCA_SPI_CTRL_CLK_DIV_SHIFT) & QCA_SPI_CTRL_CLK_DIV_MASK) |\
  50         ((_remap_dis << QCA_SPI_CTRL_REMAP_DIS_SHIFT)    & QCA_SPI_CTRL_REMAP_DIS_MASK)    |\
  51         ((_reloc_spi << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) & QCA_SPI_CTRL_SPI_RELOCATE_MASK)
  52
  53 /*
  54  * =============================
  55  * PLL configuration preset list
  56  * =============================
  57  */
  58 #if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50)       /* Tested! */
  59
  60         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1)
  61         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
  62
  63         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(10, 1, 1, 1)
  64         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
  65
  66         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
  67
  68 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100)    /* Tested! */
  69
  70         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
  71         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
  72
  73         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
  74         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
  75
  76         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
  77
  78 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150)    /* Tested! */
  79
  80         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
  81         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
  82
  83         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
  84         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
  85
  86         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
  87
  88 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80)     /* Tested! */
  89
  90         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
  91         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
  92         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
  93
  94         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(16, 1, 0, 1)
  95         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
  96
  97         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
  98
  99 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100)    /* Tested! */
 100
 101         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
 102         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 103
 104         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
 105         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 106
 107         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
 108
 109 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200)    /* Tested! */
 110
 111         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
 112         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
 113
 114         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
 115         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
 116
 117 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150)    /* Tested! */
 118
 119         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
 120         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 121
 122         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
 123         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 124
 125         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 126
 127 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175)    /* Tested! */
 128
 129         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
 130         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 131
 132         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(17, 1, 0, 1)
 133         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 134         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
 135
 136         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 137
 138 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200)    /* Tested! */
 139
 140         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
 141         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 142
 143         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
 144         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 145
 146 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_410_410_205)    /* Tested! */
 147
 148         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
 149         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 150         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(820)
 151
 152         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
 153         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 154         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
 155
 156 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_420_420_210)    /* Tested! */
 157
 158         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(33, 1, 0, 1)
 159         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 160         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
 161
 162         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1)
 163         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 164
 165 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_430_430_215)    /* Tested! */
 166
 167         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(34, 1, 0, 1)
 168         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 169         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(410)
 170
 171         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1)
 172         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 173         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
 174
 175 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_440_440_220)    /* Tested! */
 176
 177         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(35, 1, 0, 1)
 178         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 179         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(205)
 180
 181         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(22, 1, 0, 1)
 182         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 183
 184 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_450_450_225)    /* Tested! */
 185
 186         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1)
 187         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 188
 189         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(45, 2, 0, 1)
 190         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 191
 192 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_460_460_230)    /* Tested! */
 193
 194         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1)
 195         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 196         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(820)
 197
 198         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1)
 199         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 200
 201 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_470_470_235)    /* Tested! */
 202
 203         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(37, 1, 0, 1)
 204         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 205         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
 206
 207         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1)
 208         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 209         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
 210
 211 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_480_480_240)    /* Tested! */
 212
 213         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(38, 1, 0, 1)
 214         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 215         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(410)
 216
 217         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
 218         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 219
 220 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_490_490_245)    /* Tested! */
 221
 222         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(39, 1, 0, 1)
 223         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 224         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(205)
 225
 226         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
 227         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 228         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
 229
 230 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250)    /* Tested! */
 231
 232         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1)
 233         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 234
 235         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
 236         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 237
 238         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
 239
 240 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_510_510_255)    /* Tested! */
 241
 242         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1)
 243         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 244         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(820)
 245
 246         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
 247         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 248         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
 249
 250         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
 251
 252 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_520_520_260)    /* Tested! */
 253
 254         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(41, 1, 0, 1)
 255         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 256         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
 257
 258         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1)
 259         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 260
 261         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
 262
 263 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_530_265_132)    /* Tested! */
 264
 265         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(42, 1, 0, 1)
 266         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 267         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(410)
 268
 269         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1)
 270         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 271         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
 272
 273         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 274
 275 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_540_270_135)    /* Tested! */
 276
 277         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(43, 1, 0, 1)
 278         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 279         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(205)
 280
 281         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1)
 282         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 283
 284         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 285
 286 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_275_137)    /* Tested! */
 287
 288         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1)
 289         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 290
 291         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1)
 292         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 293         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
 294
 295         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 296
 297 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_560_280_140)    /* Tested! */
 298
 299         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1)
 300         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 301         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(820)
 302
 303         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
 304         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 305
 306         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 307
 308 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_570_285_142)    /* Tested! */
 309
 310         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(45, 1, 0, 1)
 311         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 312         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
 313
 314         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
 315         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 316         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
 317
 318         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 319
 320 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_580_290_145)    /* Tested! */
 321
 322         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25              _ar933x_cpu_pll_cfg_reg_val(46, 1, 0, 1)
 323         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 324         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(410)
 325
 326         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40              _ar933x_cpu_pll_cfg_reg_val(29, 1, 0, 1)
 327         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40             _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4)
 328
 329         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 330
 331 #else
 332         #error "QCA PLL configuration not supported or not selected!"
 333 #endif
 334
 335 /*
 336  * Safe configuration, used in "O/C recovery" mode:
 337  * CPU/DDR/AHB/SPI: 400/400/200/20
 338  */
 339 #define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25                 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
 340 #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL25                _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 341 #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL25         _ar933x_cpu_pll_dither_frac_reg_val(0)
 342
 343 #define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40                 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
 344 #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL40                _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 345 #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL40         _ar933x_cpu_pll_dither_frac_reg_val(0)
 346
 347 #define QCA_SPI_CTRL_REG_VAL_SAFE                               _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
 348
 349 /*
 350  * Default values (if not defined above)
 351  */
 352
 353 /* Maximum clock for SPI NOR FLASH */
 354 #ifndef CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ
 355         #define CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ            30
 356 #endif
 357
 358 /* SPI_CONTROL_ADDR register value */
 359 #ifndef QCA_SPI_CTRL_REG_VAL
 360         #define QCA_SPI_CTRL_REG_VAL                            _ar933x_spi_ctrl_addr_reg_val(8, 1, 0)
 361 #endif
 362
 363 /* CPU PLL dither register values */
 364 #ifndef QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25
 365         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(0)
 366 #endif
 367
 368 #ifndef QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40
 369         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(0)
 370 #endif
 371
 372 /* CPU PLL settle time */
 373 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL25         0x550
 374 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL40         0x352
 375
 376 #endif /* _AR933X_PLL_INIT_H_ */