u-boot/include/soc/ar933x_pll_init.h

   1 /*
   2  * Helper defines and macros related with
   3  * PLL and clocks configurations for
   4  * Qualcomm/Atheros AR933x WiSoC
   5  *
   6  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   7  *
   8  * SPDX-License-Identifier: GPL-2.0
   9  */
  10
  11 #ifndef _AR933X_PLL_INIT_H_
  12 #define _AR933X_PLL_INIT_H_
  13
  14 #include <soc/qca_soc_common.h>
  15
  16 /* CPU_PLL_CONFIG */
  17 #define _ar933x_cpu_pll_cfg_reg_val(_nint,   \
  18                                                                         _refdiv, \
  19                                                                         _range,  \
  20                                                                         _outdiv) \
  21                                                                                          \
  22                 ((_nint   << QCA_PLL_CPU_PLL_CFG_NINT_SHIFT)   & QCA_PLL_CPU_PLL_CFG_NINT_MASK)   |\
  23                 ((_refdiv << QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK) |\
  24                 ((_range  << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT)  & QCA_PLL_CPU_PLL_CFG_RANGE_MASK)  |\
  25                 ((_outdiv << QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK)
  26
  27 /* CPU_CLOCK_CONTROL */
  28 #define _ar933x_cpu_clk_ctrl_reg_val(_cpudiv, \
  29                                                                          _ddrdiv, \
  30                                                                          _ahbdiv) \
  31                                                                                           \
  32                 (((_cpudiv - 1) << QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT) &\
  33                  QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK) |\
  34                 (((_ddrdiv - 1) << QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT) &\
  35                  QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK) |\
  36                 (((_ahbdiv - 1) << QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT) &\
  37                  QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK)
  38
  39 /* PLL_DITHER_FRAC */
  40 #define _ar933x_cpu_pll_dither_frac_reg_val(_nfracmin)  \
  41                 ((_nfracmin << QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT) &\
  42                  QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK)
  43
  44 /* SPI_CONTROL_ADDR */
  45 #define _ar933x_spi_ctrl_addr_reg_val(_clk_div,   \
  46                                                                           _remap_dis, \
  47                                                                           _reloc_spi) \
  48                                                                                                   \
  49                 ((((_clk_div / 2) - 1) << QCA_SPI_CTRL_CLK_DIV_SHIFT) & QCA_SPI_CTRL_CLK_DIV_MASK) |\
  50                 ((_remap_dis << QCA_SPI_CTRL_REMAP_DIS_SHIFT)    & QCA_SPI_CTRL_REMAP_DIS_MASK)    |\
  51                 ((_reloc_spi << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) & QCA_SPI_CTRL_SPI_RELOCATE_MASK)
  52
  53 /*
  54  * =============================
  55  * PLL configuration preset list
  56  * =============================
  57  */
  58 #if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50)
  59
  60         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(16, 1, 1, 1)
  61         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
  62
  63         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(10, 1, 1, 1)
  64         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
  65
  66         #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
  67
  68 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100)
  69
  70         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
  71         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
  72
  73         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
  74         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(4, 4, 4)
  75
  76         #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
  77
  78 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150)
  79
  80         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
  81         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
  82
  83         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
  84         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 2)
  85
  86         #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
  87
  88 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80)
  89
  90         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
  91         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
  92         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25      _ar933x_cpu_pll_dither_frac_reg_val(615)
  93
  94         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(16, 1, 0, 1)
  95         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(2, 2, 4)
  96
  97         #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
  98
  99 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100)
 100
 101         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
 102         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 103
 104         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
 105         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 106
 107         #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(4, 1, 0)
 108
 109 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200)
 110
 111         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2)
 112         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
 113
 114         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2)
 115         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1)
 116
 117 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150)
 118
 119         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1)
 120         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 121
 122         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1)
 123         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 124
 125         #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 126
 127 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175)
 128
 129         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1)
 130         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 131
 132         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(17, 1, 0, 1)
 133         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 134         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40      _ar933x_cpu_pll_dither_frac_reg_val(512)
 135
 136         #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(6, 1, 0)
 137
 138 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200)
 139
 140         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
 141         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 142
 143         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
 144         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 145
 146 #elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250)
 147
 148         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25                      _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1)
 149         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 150
 151         #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40                      _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1)
 152         #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40                     _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 153
 154         #define QCA_SPI_CTRL_REG_VAL                                            _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
 155
 156 #else
 157         #error "QCA PLL configuration not supported or not selected!"
 158 #endif
 159
 160 /*
 161  * Safe configuration, used in "O/C recovery" mode:
 162  * CPU/DDR/AHB/SPI: 400/400/200/20
 163  */
 164 #define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25                         _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1)
 165 #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL25                        _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 166 #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL25         _ar933x_cpu_pll_dither_frac_reg_val(0)
 167
 168 #define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40                         _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1)
 169 #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL40                        _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2)
 170 #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL40         _ar933x_cpu_pll_dither_frac_reg_val(0)
 171
 172 #define QCA_SPI_CTRL_REG_VAL_SAFE                                                       _ar933x_spi_ctrl_addr_reg_val(10, 1, 0)
 173
 174 /*
 175  * Default values (if not defined above)
 176  */
 177
 178 /* Maximum clock for SPI NOR FLASH */
 179 #ifndef CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ
 180         #define CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ    30
 181 #endif
 182
 183 /* SPI_CONTROL_ADDR register value */
 184 #ifndef QCA_SPI_CTRL_REG_VAL
 185         #define QCA_SPI_CTRL_REG_VAL                                    _ar933x_spi_ctrl_addr_reg_val(8, 1, 0)
 186 #endif
 187
 188 /* CPU PLL dither register values */
 189 #ifndef QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25
 190         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25              _ar933x_cpu_pll_dither_frac_reg_val(0)
 191 #endif
 192
 193 #ifndef QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40
 194         #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40              _ar933x_cpu_pll_dither_frac_reg_val(0)
 195 #endif
 196
 197 /* CPU PLL settle time */
 198 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL25         0x550
 199 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL40         0x352
 200
 201 #endif /* _AR933X_PLL_INIT_H_ */