2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
\r
3 * Andreas Heppel <aheppel@sysgo.de>
\r
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
\r
8 * See file CREDITS for list of people who contributed to this
\r
11 * This program is free software; you can redistribute it and/or
\r
12 * modify it under the terms of the GNU General Public License as
\r
13 * published by the Free Software Foundation; either version 2 of
\r
14 * the License, or (at your option) any later version.
\r
16 * This program is distributed in the hope that it will be useful,
\r
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
\r
19 * GNU General Public License for more details.
\r
21 * You should have received a copy of the GNU General Public License
\r
22 * aloong with this program; if not, write to the Free Software
\r
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
\r
31 * Under PCI, each device has 256 bytes of configuration address space,
\r
32 * of which the first 64 bytes are standardized as follows:
\r
34 #define PCI_VENDOR_ID 0x00 /* 16 bits */
\r
35 #define PCI_DEVICE_ID 0x02 /* 16 bits */
\r
36 #define PCI_COMMAND 0x04 /* 16 bits */
\r
37 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
\r
38 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
\r
39 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
\r
40 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
\r
41 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
\r
42 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
\r
43 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
\r
44 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
\r
45 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
\r
46 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
\r
48 #define PCI_STATUS 0x06 /* 16 bits */
\r
49 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
\r
50 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
\r
51 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
\r
52 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
\r
53 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
\r
54 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
\r
55 #define PCI_STATUS_DEVSEL_FAST 0x000
\r
56 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
\r
57 #define PCI_STATUS_DEVSEL_SLOW 0x400
\r
58 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
\r
59 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
\r
60 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
\r
61 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
\r
62 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
\r
64 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
\r
66 #define PCI_REVISION_ID 0x08 /* Revision ID */
\r
67 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
\r
68 #define PCI_CLASS_DEVICE 0x0a /* Device class */
\r
69 #define PCI_CLASS_CODE 0x0b /* Device class code */
\r
70 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
\r
72 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
\r
73 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
\r
74 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
\r
75 #define PCI_HEADER_TYPE_NORMAL 0
\r
76 #define PCI_HEADER_TYPE_BRIDGE 1
\r
77 #define PCI_HEADER_TYPE_CARDBUS 2
\r
79 #define PCI_BIST 0x0f /* 8 bits */
\r
80 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
\r
81 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
\r
82 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
\r
85 * Base addresses specify locations in memory or I/O space.
\r
86 * Decoded size can be determined by writing a value of
\r
87 * 0xffffffff to the register, and reading it back. Only
\r
88 * 1 bits are decoded.
\r
90 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
\r
91 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
\r
92 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
\r
93 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
\r
94 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
\r
95 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
\r
96 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
\r
97 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
\r
98 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
\r
99 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
\r
100 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
\r
101 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
\r
102 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
\r
103 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
\r
104 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
\r
105 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
\r
106 /* bit 1 is reserved if address_space = 1 */
\r
108 /* Header type 0 (normal devices) */
\r
109 #define PCI_CARDBUS_CIS 0x28
\r
110 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
\r
111 #define PCI_SUBSYSTEM_ID 0x2e
\r
112 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
\r
113 #define PCI_ROM_ADDRESS_ENABLE 0x01
\r
114 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
\r
116 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
\r
118 /* 0x35-0x3b are reserved */
\r
119 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
\r
120 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
\r
121 #define PCI_MIN_GNT 0x3e /* 8 bits */
\r
122 #define PCI_MAX_LAT 0x3f /* 8 bits */
\r
124 /* Header type 1 (PCI-to-PCI bridges) */
\r
125 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
\r
126 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
\r
127 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
\r
128 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
\r
129 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
\r
130 #define PCI_IO_LIMIT 0x1d
\r
131 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
\r
132 #define PCI_IO_RANGE_TYPE_16 0x00
\r
133 #define PCI_IO_RANGE_TYPE_32 0x01
\r
134 #define PCI_IO_RANGE_MASK ~0x0f
\r
135 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
\r
136 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
\r
137 #define PCI_MEMORY_LIMIT 0x22
\r
138 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
\r
139 #define PCI_MEMORY_RANGE_MASK ~0x0f
\r
140 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
\r
141 #define PCI_PREF_MEMORY_LIMIT 0x26
\r
142 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
\r
143 #define PCI_PREF_RANGE_TYPE_32 0x00
\r
144 #define PCI_PREF_RANGE_TYPE_64 0x01
\r
145 #define PCI_PREF_RANGE_MASK ~0x0f
\r
146 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
\r
147 #define PCI_PREF_LIMIT_UPPER32 0x2c
\r
148 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
\r
149 #define PCI_IO_LIMIT_UPPER16 0x32
\r
150 /* 0x34 same as for htype 0 */
\r
151 /* 0x35-0x3b is reserved */
\r
152 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
\r
153 /* 0x3c-0x3d are same as for htype 0 */
\r
154 #define PCI_BRIDGE_CONTROL 0x3e
\r
155 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
\r
156 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
\r
157 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
\r
158 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
\r
159 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
\r
160 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
\r
161 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
\r
164 #define PCI_ERREN 0x48 /* Error Enable */
\r
165 #define PCI_ERRSTS 0x49 /* Error Status */
\r
166 #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
\r
167 #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
\r
168 #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
\r
169 #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
\r
170 #define PCI_CAPID 0x58 /* Capability Identifier */
\r
171 #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
\r
172 #define PCI_PMC 0x5A /* Power Management Capabilities */
\r
173 #define PCI_PMCSR 0x5C /* Power Management Control Status */
\r
174 #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
\r
175 #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
\r
176 #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
\r
178 /* Header type 2 (CardBus bridges) */
\r
179 #define PCI_CB_CAPABILITY_LIST 0x14
\r
180 /* 0x15 reserved */
\r
181 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
\r
182 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
\r
183 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
\r
184 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
\r
185 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
\r
186 #define PCI_CB_MEMORY_BASE_0 0x1c
\r
187 #define PCI_CB_MEMORY_LIMIT_0 0x20
\r
188 #define PCI_CB_MEMORY_BASE_1 0x24
\r
189 #define PCI_CB_MEMORY_LIMIT_1 0x28
\r
190 #define PCI_CB_IO_BASE_0 0x2c
\r
191 #define PCI_CB_IO_BASE_0_HI 0x2e
\r
192 #define PCI_CB_IO_LIMIT_0 0x30
\r
193 #define PCI_CB_IO_LIMIT_0_HI 0x32
\r
194 #define PCI_CB_IO_BASE_1 0x34
\r
195 #define PCI_CB_IO_BASE_1_HI 0x36
\r
196 #define PCI_CB_IO_LIMIT_1 0x38
\r
197 #define PCI_CB_IO_LIMIT_1_HI 0x3a
\r
198 #define PCI_CB_IO_RANGE_MASK ~0x03
\r
199 /* 0x3c-0x3d are same as for htype 0 */
\r
200 #define PCI_CB_BRIDGE_CONTROL 0x3e
\r
201 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
\r
202 #define PCI_CB_BRIDGE_CTL_SERR 0x02
\r
203 #define PCI_CB_BRIDGE_CTL_ISA 0x04
\r
204 #define PCI_CB_BRIDGE_CTL_VGA 0x08
\r
205 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
\r
206 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
\r
207 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
\r
208 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
\r
209 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
\r
210 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
\r
211 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
\r
212 #define PCI_CB_SUBSYSTEM_ID 0x42
\r
213 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
\r
214 /* 0x48-0x7f reserved */
\r
216 /* Capability lists */
\r
218 #define PCI_CAP_LIST_ID 0 /* Capability ID */
\r
219 #define PCI_CAP_ID_PM 0x01 /* Power Management */
\r
220 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
\r
221 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
\r
222 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
\r
223 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
\r
224 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
\r
225 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
\r
226 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
\r
227 #define PCI_CAP_SIZEOF 4
\r
229 /* Power Management Registers */
\r
231 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
\r
232 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
\r
233 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
\r
234 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
\r
235 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
\r
236 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
\r
237 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
\r
238 #define PCI_PM_CTRL 4 /* PM control and status register */
\r
239 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
\r
240 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
\r
241 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
\r
242 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
\r
243 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
\r
244 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
\r
245 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
\r
246 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
\r
247 #define PCI_PM_DATA_REGISTER 7 /* (??) */
\r
248 #define PCI_PM_SIZEOF 8
\r
250 /* AGP registers */
\r
252 #define PCI_AGP_VERSION 2 /* BCD version number */
\r
253 #define PCI_AGP_RFU 3 /* Rest of capability flags */
\r
254 #define PCI_AGP_STATUS 4 /* Status register */
\r
255 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
\r
256 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
\r
257 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
\r
258 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
\r
259 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
\r
260 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
\r
261 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
\r
262 #define PCI_AGP_COMMAND 8 /* Control register */
\r
263 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
\r
264 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
\r
265 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
\r
266 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
\r
267 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
\r
268 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
\r
269 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
\r
270 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
\r
271 #define PCI_AGP_SIZEOF 12
\r
273 /* Slot Identification */
\r
275 #define PCI_SID_ESR 2 /* Expansion Slot Register */
\r
276 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
\r
277 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
\r
278 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
\r
280 /* Message Signalled Interrupts registers */
\r
282 #define PCI_MSI_FLAGS 2 /* Various flags */
\r
283 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
\r
284 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
\r
285 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
\r
286 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
\r
287 #define PCI_MSI_RFU 3 /* Rest of capability flags */
\r
288 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
\r
289 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
\r
290 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
\r
291 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
\r
293 #define PCI_MAX_PCI_DEVICES 32
\r
294 #define PCI_MAX_PCI_FUNCTIONS 8
\r
296 /* Include the ID list */
\r
298 #include <pci_ids.h>
\r
300 struct pci_region {
\r
301 unsigned long bus_start; /* Start on the bus */
\r
302 unsigned long phys_start; /* Start in physical address space */
\r
303 unsigned long size; /* Size */
\r
304 unsigned long flags; /* Resource flags */
\r
306 unsigned long bus_lower;
\r
309 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */
\r
310 #define PCI_REGION_IO 0x00000001 /* PCI IO space */
\r
311 #define PCI_REGION_TYPE 0x00000001
\r
312 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
\r
314 #define PCI_REGION_MEMORY 0x00000100 /* System memory */
\r
315 #define PCI_REGION_RO 0x00000200 /* Read-only memory */
\r
317 typedef int pci_dev_t;
\r
319 #define PCI_BUS(d) (((d) >> 16) & 0xff)
\r
320 #define PCI_DEV(d) (((d) >> 11) & 0x1f)
\r
321 #define PCI_FUNC(d) (((d) >> 8) & 0x7)
\r
322 #define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
\r
324 #define PCI_ANY_ID (~0)
\r
326 struct pci_controller;
\r
328 struct pci_config_table {
\r
329 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
\r
330 unsigned int class; /* Class ID, or PCI_ANY_ID */
\r
331 unsigned int bus; /* Bus number, or PCI_ANY_ID */
\r
332 unsigned int dev; /* Device number, or PCI_ANY_ID */
\r
333 unsigned int func; /* Function number, or PCI_ANY_ID */
\r
335 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *);
\r
336 unsigned long priv[3];
\r
339 #define MAX_PCI_REGIONS 7
\r
342 * Structure of a PCI controller (host bridge)
\r
344 struct pci_controller {
\r
345 struct pci_controller *next;
\r
350 volatile unsigned int *cfg_addr;
\r
351 volatile unsigned char *cfg_data;
\r
353 struct pci_region regions[MAX_PCI_REGIONS];
\r
356 struct pci_config_table *config_table;
\r
358 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
\r
360 /* Low-level architecture-dependent routines */
\r
361 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
\r
362 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
\r
363 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
\r
364 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
\r
365 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
\r
366 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
\r
368 /* Used by auto config */
\r
369 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
\r
371 /* Used by ppc405 autoconfig*/
\r
372 struct pci_region *pci_fb;
\r
376 #endif /* _PCI_H */
\r