2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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3 * Andreas Heppel <aheppel@sysgo.de>
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6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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8 * See file CREDITS for list of people who contributed to this
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11 * This program is free software; you can redistribute it and/or
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12 * modify it under the terms of the GNU General Public License as
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13 * published by the Free Software Foundation; either version 2 of
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14 * the License, or (at your option) any later version.
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16 * This program is distributed in the hope that it will be useful,
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17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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19 * GNU General Public License for more details.
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21 * You should have received a copy of the GNU General Public License
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22 * aloong with this program; if not, write to the Free Software
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23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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31 * Under PCI, each device has 256 bytes of configuration address space,
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32 * of which the first 64 bytes are standardized as follows:
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34 #define PCI_VENDOR_ID 0x00 /* 16 bits */
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35 #define PCI_DEVICE_ID 0x02 /* 16 bits */
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36 #define PCI_COMMAND 0x04 /* 16 bits */
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37 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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38 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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39 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
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40 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
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41 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
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42 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
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43 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
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44 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
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45 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
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46 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
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48 #define PCI_STATUS 0x06 /* 16 bits */
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49 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
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50 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
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51 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
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52 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
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53 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
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54 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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55 #define PCI_STATUS_DEVSEL_FAST 0x000
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56 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
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57 #define PCI_STATUS_DEVSEL_SLOW 0x400
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58 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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59 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
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60 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
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61 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
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62 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
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64 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
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66 #define PCI_REVISION_ID 0x08 /* Revision ID */
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67 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
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68 #define PCI_CLASS_DEVICE 0x0a /* Device class */
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69 #define PCI_CLASS_CODE 0x0b /* Device class code */
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70 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
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72 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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73 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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74 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
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75 #define PCI_HEADER_TYPE_NORMAL 0
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76 #define PCI_HEADER_TYPE_BRIDGE 1
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77 #define PCI_HEADER_TYPE_CARDBUS 2
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79 #define PCI_BIST 0x0f /* 8 bits */
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80 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
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81 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
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82 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
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85 * Base addresses specify locations in memory or I/O space.
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86 * Decoded size can be determined by writing a value of
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87 * 0xffffffff to the register, and reading it back. Only
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88 * 1 bits are decoded.
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90 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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91 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
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92 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
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93 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
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94 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
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95 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
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96 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
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97 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
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98 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
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99 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
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100 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
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101 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
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102 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
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103 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
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104 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
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105 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
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106 /* bit 1 is reserved if address_space = 1 */
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108 /* Header type 0 (normal devices) */
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109 #define PCI_CARDBUS_CIS 0x28
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110 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
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111 #define PCI_SUBSYSTEM_ID 0x2e
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112 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
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113 #define PCI_ROM_ADDRESS_ENABLE 0x01
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114 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
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116 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
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118 /* 0x35-0x3b are reserved */
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119 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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120 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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121 #define PCI_MIN_GNT 0x3e /* 8 bits */
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122 #define PCI_MAX_LAT 0x3f /* 8 bits */
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124 /* Header type 1 (PCI-to-PCI bridges) */
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125 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
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126 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
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127 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
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128 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
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129 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
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130 #define PCI_IO_LIMIT 0x1d
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131 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
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132 #define PCI_IO_RANGE_TYPE_16 0x00
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133 #define PCI_IO_RANGE_TYPE_32 0x01
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134 #define PCI_IO_RANGE_MASK ~0x0f
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135 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
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136 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
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137 #define PCI_MEMORY_LIMIT 0x22
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138 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
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139 #define PCI_MEMORY_RANGE_MASK ~0x0f
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140 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
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141 #define PCI_PREF_MEMORY_LIMIT 0x26
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142 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
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143 #define PCI_PREF_RANGE_TYPE_32 0x00
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144 #define PCI_PREF_RANGE_TYPE_64 0x01
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145 #define PCI_PREF_RANGE_MASK ~0x0f
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146 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
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147 #define PCI_PREF_LIMIT_UPPER32 0x2c
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148 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
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149 #define PCI_IO_LIMIT_UPPER16 0x32
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150 /* 0x34 same as for htype 0 */
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151 /* 0x35-0x3b is reserved */
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152 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
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153 /* 0x3c-0x3d are same as for htype 0 */
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154 #define PCI_BRIDGE_CONTROL 0x3e
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155 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
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156 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
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157 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
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158 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
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159 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
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160 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
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161 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
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164 #define PCI_ERREN 0x48 /* Error Enable */
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165 #define PCI_ERRSTS 0x49 /* Error Status */
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166 #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
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167 #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
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168 #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
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169 #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
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170 #define PCI_CAPID 0x58 /* Capability Identifier */
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171 #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
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172 #define PCI_PMC 0x5A /* Power Management Capabilities */
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173 #define PCI_PMCSR 0x5C /* Power Management Control Status */
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174 #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
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175 #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
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176 #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
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178 /* Header type 2 (CardBus bridges) */
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179 #define PCI_CB_CAPABILITY_LIST 0x14
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180 /* 0x15 reserved */
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181 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
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182 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
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183 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
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184 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
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185 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
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186 #define PCI_CB_MEMORY_BASE_0 0x1c
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187 #define PCI_CB_MEMORY_LIMIT_0 0x20
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188 #define PCI_CB_MEMORY_BASE_1 0x24
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189 #define PCI_CB_MEMORY_LIMIT_1 0x28
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190 #define PCI_CB_IO_BASE_0 0x2c
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191 #define PCI_CB_IO_BASE_0_HI 0x2e
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192 #define PCI_CB_IO_LIMIT_0 0x30
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193 #define PCI_CB_IO_LIMIT_0_HI 0x32
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194 #define PCI_CB_IO_BASE_1 0x34
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195 #define PCI_CB_IO_BASE_1_HI 0x36
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196 #define PCI_CB_IO_LIMIT_1 0x38
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197 #define PCI_CB_IO_LIMIT_1_HI 0x3a
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198 #define PCI_CB_IO_RANGE_MASK ~0x03
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199 /* 0x3c-0x3d are same as for htype 0 */
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200 #define PCI_CB_BRIDGE_CONTROL 0x3e
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201 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
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202 #define PCI_CB_BRIDGE_CTL_SERR 0x02
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203 #define PCI_CB_BRIDGE_CTL_ISA 0x04
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204 #define PCI_CB_BRIDGE_CTL_VGA 0x08
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205 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
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206 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
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207 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
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208 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
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209 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
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210 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
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211 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
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212 #define PCI_CB_SUBSYSTEM_ID 0x42
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213 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
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214 /* 0x48-0x7f reserved */
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216 /* Capability lists */
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218 #define PCI_CAP_LIST_ID 0 /* Capability ID */
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219 #define PCI_CAP_ID_PM 0x01 /* Power Management */
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220 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
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221 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
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222 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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223 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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224 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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225 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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226 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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227 #define PCI_CAP_SIZEOF 4
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229 /* Power Management Registers */
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231 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
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232 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
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233 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
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234 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
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235 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
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236 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
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237 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
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238 #define PCI_PM_CTRL 4 /* PM control and status register */
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239 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
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240 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
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241 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
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242 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
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243 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
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244 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
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245 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
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246 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
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247 #define PCI_PM_DATA_REGISTER 7 /* (??) */
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248 #define PCI_PM_SIZEOF 8
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250 /* AGP registers */
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252 #define PCI_AGP_VERSION 2 /* BCD version number */
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253 #define PCI_AGP_RFU 3 /* Rest of capability flags */
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254 #define PCI_AGP_STATUS 4 /* Status register */
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255 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
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256 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
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257 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
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258 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
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259 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
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260 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
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261 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
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262 #define PCI_AGP_COMMAND 8 /* Control register */
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263 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
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264 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
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265 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
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266 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
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267 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
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268 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
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269 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
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270 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
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271 #define PCI_AGP_SIZEOF 12
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273 /* Slot Identification */
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275 #define PCI_SID_ESR 2 /* Expansion Slot Register */
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276 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
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277 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
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278 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
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280 /* Message Signalled Interrupts registers */
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282 #define PCI_MSI_FLAGS 2 /* Various flags */
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283 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
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284 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
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285 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
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286 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
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287 #define PCI_MSI_RFU 3 /* Rest of capability flags */
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288 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
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289 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
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290 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
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291 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
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293 #define PCI_MAX_PCI_DEVICES 32
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294 #define PCI_MAX_PCI_FUNCTIONS 8
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296 /* Include the ID list */
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298 #include <pci_ids.h>
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300 struct pci_region {
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301 unsigned long bus_start; /* Start on the bus */
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302 unsigned long phys_start; /* Start in physical address space */
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303 unsigned long size; /* Size */
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304 unsigned long flags; /* Resource flags */
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306 unsigned long bus_lower;
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309 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */
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310 #define PCI_REGION_IO 0x00000001 /* PCI IO space */
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311 #define PCI_REGION_TYPE 0x00000001
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312 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
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314 #define PCI_REGION_MEMORY 0x00000100 /* System memory */
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315 #define PCI_REGION_RO 0x00000200 /* Read-only memory */
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317 typedef int pci_dev_t;
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319 #define PCI_BUS(d) (((d) >> 16) & 0xff)
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320 #define PCI_DEV(d) (((d) >> 11) & 0x1f)
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321 #define PCI_FUNC(d) (((d) >> 8) & 0x7)
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322 #define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
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324 #define PCI_ANY_ID (~0)
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326 struct pci_controller;
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328 struct pci_config_table {
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329 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
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330 unsigned int class; /* Class ID, or PCI_ANY_ID */
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331 unsigned int bus; /* Bus number, or PCI_ANY_ID */
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332 unsigned int dev; /* Device number, or PCI_ANY_ID */
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333 unsigned int func; /* Function number, or PCI_ANY_ID */
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335 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *);
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336 unsigned long priv[3];
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339 #define MAX_PCI_REGIONS 7
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342 * Structure of a PCI controller (host bridge)
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344 struct pci_controller {
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345 struct pci_controller *next;
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350 volatile unsigned int *cfg_addr;
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351 volatile unsigned char *cfg_data;
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353 struct pci_region regions[MAX_PCI_REGIONS];
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356 struct pci_config_table *config_table;
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358 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
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360 /* Low-level architecture-dependent routines */
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361 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
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362 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
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363 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
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364 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
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365 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
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366 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
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368 /* Used by auto config */
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369 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
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371 /* Used by ppc405 autoconfig*/
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372 struct pci_region *pci_fb;
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376 #endif /* _PCI_H */
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