u-boot/include/miiphy.h

   1 /*----------------------------------------------------------------------------+
   2 |
   3 |       This source code has been made available to you by IBM on an AS-IS
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   5 |       copyrights to use it in any way he or she deems fit, including
   6 |       copying it, modifying it, compiling it, and redistributing it either
   7 |       with or without modifications.  No license under IBM patents or
   8 |       patent applications is to be implied by the copyright license.
   9 |
  10 |       Any user of this software should understand that IBM cannot provide
  11 |       technical support for this software and will not be responsible for
  12 |       any consequences resulting from the use of this software.
  13 |
  14 |       Any person who transfers this source code or any derivative work
  15 |       must include the IBM copyright notice, this paragraph, and the
  16 |       preceding two paragraphs in the transferred software.
  17 |
  18 |       COPYRIGHT   I B M   CORPORATION 1999
  19 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20 +----------------------------------------------------------------------------*/
  21 /*----------------------------------------------------------------------------+
  22 |
  23 |  File Name:   miiphy.h
  24 |
  25 |  Function:    Include file defining PHY registers.
  26 |
  27 |  Author:      Mark Wisner
  28 |
  29 |  Change Activity-
  30 |
  31 |  Date        Description of Change                                    BY
  32 |  ---------   ---------------------                                    ---
  33 |  04-May-99   Created                                                  MKW
  34 |  07-Jul-99   Added full duplex support                                MKW
  35 |  08-Sep-01   Tweaks                                                   gvb
  36 |
  37 +----------------------------------------------------------------------------*/
  38 #ifndef _miiphy_h_
  39 #define _miiphy_h_
  40
  41 #include <net.h>
  42
  43 int miiphy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value);
  44 int miiphy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value);
  45 int miiphy_info(char *devname, unsigned char addr, unsigned int *oui, unsigned char *model, unsigned char *rev);
  46 int miiphy_reset(char *devname, unsigned char addr);
  47 int miiphy_speed(char *devname, unsigned char addr);
  48 int miiphy_duplex(char *devname, unsigned char addr);
  49
  50 void miiphy_init(void);
  51
  52 void miiphy_register(char *devname,     int (* read)(char *devname, unsigned char addr, unsigned char reg, unsigned short *value), int (* write)(char *devname, unsigned char addr, unsigned char reg, unsigned short value));
  53
  54 int miiphy_set_current_dev(char *devname);
  55 char *miiphy_get_current_dev(void);
  56
  57 void miiphy_listdev(void);
  58
  59 #define BB_MII_DEVNAME  "bbmii"
  60
  61 int bb_miiphy_read (char *devname, unsigned char addr, unsigned char reg, unsigned short *value);
  62 int bb_miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value);
  63
  64 /* phy speed setup */
  65 #define AUTO                                    99
  66 #define _1000BASET                              1000
  67 #define _100BASET                               100
  68 #define _10BASET                                10
  69 #define HALF                                    22
  70 #define FULL                                    44
  71
  72 /* phy register offsets */
  73 #define PHY_BMCR                                0x00
  74 #define PHY_BMSR                                0x01
  75 #define PHY_PHYIDR1                             0x02
  76 #define PHY_PHYIDR2                             0x03
  77 #define PHY_ANAR                                0x04
  78 #define PHY_ANLPAR                              0x05
  79 #define PHY_ANER                                0x06
  80 #define PHY_ANNPTR                              0x07
  81 #define PHY_ANLPNP                              0x08
  82 #define PHY_1000BTCR                    0x09
  83 #define PHY_1000BTSR                    0x0A
  84 #define PHY_PHYSTS                              0x10
  85 #define PHY_MIPSCR                              0x11
  86 #define PHY_MIPGSR                              0x12
  87 #define PHY_DCR                                 0x13
  88 #define PHY_FCSCR                               0x14
  89 #define PHY_RECR                                0x15
  90 #define PHY_PCSR                                0x16
  91 #define PHY_LBR                                 0x17
  92 #define PHY_10BTSCR                             0x18
  93 #define PHY_PHYCTRL                             0x19
  94
  95 /* PHY BMCR */
  96 #define PHY_BMCR_RESET                  0x8000
  97 #define PHY_BMCR_LOOP                   0x4000
  98 #define PHY_BMCR_100MB                  0x2000
  99 #define PHY_BMCR_AUTON                  0x1000
 100 #define PHY_BMCR_POWD                   0x0800
 101 #define PHY_BMCR_ISO                    0x0400
 102 #define PHY_BMCR_RST_NEG                0x0200
 103 #define PHY_BMCR_DPLX                   0x0100
 104 #define PHY_BMCR_COL_TST                0x0080
 105
 106 #define PHY_BMCR_SPEED_MASK             0x2040
 107 #define PHY_BMCR_1000_MBPS              0x0040
 108 #define PHY_BMCR_100_MBPS               0x2000
 109 #define PHY_BMCR_10_MBPS                0x0000
 110
 111 /* phy BMSR */
 112 #define PHY_BMSR_100T4                  0x8000
 113 #define PHY_BMSR_100TXF                 0x4000
 114 #define PHY_BMSR_100TXH                 0x2000
 115 #define PHY_BMSR_10TF                   0x1000
 116 #define PHY_BMSR_10TH                   0x0800
 117 #define PHY_BMSR_PRE_SUP                0x0040
 118 #define PHY_BMSR_AUTN_COMP              0x0020
 119 #define PHY_BMSR_RF                             0x0010
 120 #define PHY_BMSR_AUTN_ABLE              0x0008
 121 #define PHY_BMSR_LS                             0x0004
 122 #define PHY_BMSR_JD                             0x0002
 123 #define PHY_BMSR_EXT                    0x0001
 124
 125 /*phy ANLPAR */
 126 #define PHY_ANLPAR_NP                   0x8000
 127 #define PHY_ANLPAR_ACK                  0x4000
 128 #define PHY_ANLPAR_RF                   0x2000
 129 #define PHY_ANLPAR_T4                   0x0200
 130 #define PHY_ANLPAR_TXFD                 0x0100
 131 #define PHY_ANLPAR_TX                   0x0080
 132 #define PHY_ANLPAR_10FD                 0x0040
 133 #define PHY_ANLPAR_10                   0x0020
 134 #define PHY_ANLPAR_100                  0x0380      /* we can run at 100 */
 135
 136 #define PHY_ANLPAR_PSB_MASK             0x001f
 137 #define PHY_ANLPAR_PSB_802_3    0x0001
 138 #define PHY_ANLPAR_PSB_802_9    0x0002
 139
 140 /* PHY_1000BTSR */
 141 #define PHY_1000BTSR_MSCF               0x8000
 142 #define PHY_1000BTSR_MSCR               0x4000
 143 #define PHY_1000BTSR_LRS                0x2000
 144 #define PHY_1000BTSR_RRS                0x1000
 145 #define PHY_1000BTSR_1000FD             0x0800
 146 #define PHY_1000BTSR_1000HD             0x0400
 147
 148 #endif