2 * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
4 * This file contains the configuration parameters
5 * for Qualcomm Atheros AR934x based devices
7 * Reference designs: AP123, MI124, DB120
9 * SPDX-License-Identifier: GPL-2.0
16 #include <configs/qca9k_common.h>
17 #include <soc/soc_common.h>
24 #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1)
26 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO11 | GPIO12 | GPIO13 |\
28 #define CONFIG_QCA_GPIO_MASK_OUT GPIO21 | GPIO22 |\
29 CONFIG_QCA_GPIO_MASK_LED_ACT_L
30 #define CONFIG_QCA_GPIO_MASK_IN GPIO16 | GPIO17
31 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO21 | GPIO22 |\
32 CONFIG_QCA_GPIO_MASK_LED_ACT_L
34 #elif defined(CONFIG_FOR_TPLINK_WDR3500_V1)
36 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO11 | GPIO13 | GPIO14 |\
37 GPIO15 | GPIO18 | GPIO19 |\
38 GPIO20 | GPIO21 | GPIO22
39 #define CONFIG_QCA_GPIO_MASK_OUT GPIO12 |\
40 CONFIG_QCA_GPIO_MASK_LED_ACT_L
41 #define CONFIG_QCA_GPIO_MASK_IN GPIO16 | GPIO17
42 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO12 |\
43 CONFIG_QCA_GPIO_MASK_LED_ACT_L
45 #elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
47 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO11 | GPIO12 | GPIO13 |\
48 GPIO14 | GPIO15 | GPIO18 |\
49 GPIO19 | GPIO20 | GPIO21
50 #define CONFIG_QCA_GPIO_MASK_OUT GPIO4 |\
51 CONFIG_QCA_GPIO_MASK_LED_ACT_L
52 #define CONFIG_QCA_GPIO_MASK_IN GPIO16 | GPIO17
53 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO4 |\
54 CONFIG_QCA_GPIO_MASK_LED_ACT_L
56 #elif defined(CONFIG_FOR_TPLINK_WR841N_V8)
58 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO12 | GPIO13 | GPIO14 |\
59 GPIO15 | GPIO18 | GPIO19 |\
61 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
62 #define CONFIG_QCA_GPIO_MASK_IN GPIO16 | GPIO17
63 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
65 #elif defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
67 #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13 | GPIO14 | GPIO15 |\
69 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
70 #define CONFIG_QCA_GPIO_MASK_IN GPIO16 | GPIO17
71 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
80 #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) ||\
81 defined(CONFIG_FOR_TPLINK_WDR3500_V1)
83 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
84 "rootfstype=squashfs init=/sbin/init "\
85 "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(art)"
89 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
90 "rootfstype=squashfs init=/sbin/init "\
91 "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
96 * =============================
97 * Load address and boot command
98 * =============================
100 #define CFG_LOAD_ADDR 0x9F020000
101 #define CONFIG_BOOTCOMMAND "bootm " MK_STR(CFG_LOAD_ADDR)
104 * =========================
105 * Environment configuration
106 * =========================
108 #define CFG_ENV_ADDR 0x9F01EC00
109 #define CFG_ENV_SIZE 0x1000
110 #define CFG_ENV_SECT_SIZE 0x10000
113 * ===========================
114 * List of available baudrates
115 * ===========================
117 #define CFG_BAUDRATE_TABLE \
118 { 600, 1200, 2400, 4800, 9600, 14400, \
119 19200, 28800, 38400, 56000, 57600, 115200 }
122 * ==================================================
123 * MAC address/es, model and WPS pin offsets in FLASH
124 * ==================================================
126 #define OFFSET_MAC_DATA_BLOCK 0x010000
127 #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
128 #define OFFSET_MAC_ADDRESS 0x00FC00
129 #define OFFSET_ROUTER_MODEL 0x00FD00
130 #define OFFSET_PIN_NUMBER 0x00FE00
133 * ===========================
134 * HTTP recovery configuration
135 * ===========================
137 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_LOAD_ADDR
139 /* Firmware size limit */
140 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
143 * ========================
144 * PLL/Clocks configuration
145 * ========================
147 #define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200
149 #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) ||\
150 defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\
151 defined(CONFIG_FOR_TPLINK_MR3420_V2) ||\
152 defined(CONFIG_FOR_TPLINK_WR841N_V8) ||\
153 defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
155 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x10000
156 #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
161 * ===================
162 * Other configuration
163 * ===================
166 /* Cache lock for stack */
167 #define CONFIG_INIT_SRAM_SP_OFFSET 0xbd007000
169 #endif /* _DB12X_H */