u-boot/include/configs/db12x.h

   1 /*
   2  * This file contains the configuration parameters for the DB12x (AR9344) board.
   3  */
   4
   5 #ifndef __CONFIG_H
   6 #define __CONFIG_H
   7
   8 #include <configs/ar7240.h>
   9 #include <config.h>
  10
  11 /*
  12  * FLASH and environment organization
  13  */
  14 #define CFG_MAX_FLASH_BANKS                     1
  15 #define CFG_MAX_FLASH_SECT                      4096    // 4 KB sectors in 16 MB flash
  16 /*
  17  * We boot from this flash
  18  */
  19 #define CFG_FLASH_BASE                                  0x9F000000
  20 #ifdef COMPRESSED_UBOOT
  21         #define BOOTSTRAP_TEXT_BASE                     CFG_FLASH_BASE
  22         #define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE
  23 #endif
  24
  25 /*
  26  * The following #defines are needed to get flash environment right
  27  */
  28 #define CFG_MONITOR_BASE        TEXT_BASE
  29 #define CFG_MONITOR_LEN         (192 << 10)
  30
  31 /*
  32  * Default bootargs
  33  */
  34 #undef CONFIG_BOOTARGS
  35 #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) || defined (CONFIG_FOR_TPLINK_WDR3500_V1)
  36 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)"
  37 #else
  38 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
  39 #endif
  40
  41 /*
  42  * Other env default values
  43  */
  44 #undef CONFIG_BOOTFILE
  45 #define CONFIG_BOOTFILE         "firmware.bin"
  46
  47 #undef CONFIG_LOADADDR
  48 #define CONFIG_LOADADDR         0x80800000
  49
  50 #define CFG_LOAD_ADDR                    0x9F020000
  51 #define UPDATE_SCRIPT_FW_ADDR   "0x9F020000"
  52 #define CONFIG_BOOTCOMMAND              "bootm 0x9F020000"
  53
  54
  55 #define CONFIG_IPADDR           192.168.1.1
  56 #define CONFIG_SERVERIP         192.168.1.2
  57
  58 #undef CFG_PLL_FREQ
  59 #undef CFG_HZ
  60
  61 // CPU-RAM-AHB frequency setting
  62 #if !defined(CONFIG_AP123)
  63 #define CFG_PLL_FREQ                            CFG_PLL_560_480_240
  64 #define CFG_HZ_FALLBACK                         (560000000LU/2)
  65 #else
  66 #define CFG_PLL_FREQ                            CFG_PLL_533_400_200
  67 #define CFG_HZ_FALLBACK                         (535000000LU/2)
  68 #endif
  69
  70 #define CFG_HZ                                          bd->bi_cfg_hz
  71 #define AR7240_SPI_CONTROL                      0x43
  72 #define AR7240_SPI_CONTROL_DEFAULT      AR7240_SPI_CONTROL
  73 /*
  74  * MIPS32 24K Processor Core Family Software User's Manual
  75  *
  76  * 6.2.9 Count Register (CP0 Register 9, Select 0)
  77  * The Count register acts as a timer, incrementing at a constant
  78  * rate, whether or not an instruction is executed, retired, or
  79  * any forward progress is made through the pipeline.  The counter
  80  * increments every other clock, if the DC bit in the Cause register
  81  * is 0.
  82  *
  83  * Since the count is incremented every other tick, divide by 2
  84  * XXX derive this from CFG_PLL_FREQ
  85  */
  86
  87 /*
  88  * Cache lock for stack
  89  */
  90 #define CFG_INIT_SP_OFFSET              0x1000
  91
  92 /*
  93  * Address and size of Primary Environment Sector
  94  */
  95 #define CFG_ENV_IS_IN_FLASH     1
  96 #undef  CFG_ENV_IS_NOWHERE
  97
  98 #define CFG_ENV_ADDR            0x9F01EC00
  99 #define CFG_ENV_SIZE            0x1000
 100 #define CFG_ENV_SECT_SIZE       0x10000
 101
 102 /*
 103  * Available commands
 104  */
 105 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 106                                                  CFG_CMD_DHCP   | \
 107                                                  CFG_CMD_PING   | \
 108                                                  CFG_CMD_FLASH  | \
 109                                                  CFG_CMD_NET    | \
 110                                                  CFG_CMD_RUN    | \
 111                                                  CFG_CMD_DATE   | \
 112                                                  CFG_CMD_SNTP   | \
 113                                                  CFG_CMD_ECHO   | \
 114                                                  CFG_CMD_BOOTD  | \
 115                                                  CFG_CMD_ITEST  | \
 116                                                  CFG_CMD_ENV    | \
 117                                                  CFG_CMD_LOADB)
 118
 119 // Enable NetConsole and custom NetConsole port
 120 #define CONFIG_NETCONSOLE
 121 #define CONFIG_NETCONSOLE_PORT  6666
 122
 123 /* DDR settings for WASP */
 124 #define CFG_DDR_REFRESH_VAL     0x4270
 125 #define CFG_DDR_CONFIG_VAL      0xc7bc8cd0
 126 #define CFG_DDR_MODE_VAL_INIT   0x133
 127 #define CFG_DDR_EXT_MODE_VAL    0x0
 128 #define CFG_DDR_MODE_VAL        0x33
 129 #define CFG_DDR_TRTW_VAL        0x1f
 130 #define CFG_DDR_TWTR_VAL        0x1e
 131 #define CFG_DDR_CONFIG2_VAL     0x9dd0e6a8
 132
 133 #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32      0xff
 134 #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16      0xffff
 135
 136 #if DDR2_32BIT_SUPPORT
 137         #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL         CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32
 138 #else
 139         #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL         CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16
 140 #endif
 141
 142 #define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL         0xffff
 143 #define CFG_SDRAM_RD_DATA_THIS_CYCLE_VAL        0xffffffff
 144
 145 /* DDR2 Init values */
 146 #define CFG_DDR2_EXT_MODE_VAL    0x402
 147
 148 #define CONFIG_NET_MULTI
 149
 150 #ifdef CFG_ATHRS27_PHY
 151         /* use eth1(LAN) as the net interface */
 152         #define CONFIG_AG7240_SPEPHY
 153 #endif
 154
 155 #define CONFIG_PCI 1
 156
 157 /*
 158  * Web Failsafe configuration
 159  */
 160 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS                          CONFIG_LOADADDR
 161 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS                        CFG_FLASH_BASE
 162
 163 // Firmware partition offset
 164 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS                       WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
 165
 166 // U-Boot partition size
 167 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES          (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
 168
 169 // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
 170 #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x1EC00"
 171 #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        "0x20000"
 172
 173 // ART partition size
 174 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES            (64 * 1024)
 175
 176 // max. firmware size <= (FLASH_SIZE -  WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
 177 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
 178 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 179
 180 // progress state info
 181 #define WEBFAILSAFE_PROGRESS_START                              0
 182 #define WEBFAILSAFE_PROGRESS_TIMEOUT                    1
 183 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY               2
 184 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY              3
 185 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED             4
 186
 187 // update type
 188 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE               0
 189 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT                  1
 190 #define WEBFAILSAFE_UPGRADE_TYPE_ART                    2
 191
 192 /*-----------------------------------------------------------------------*/
 193
 194 /*
 195  * Additional environment variables for simple upgrades
 196  */
 197 #define CONFIG_EXTRA_ENV_SETTINGS       "uboot_addr=0x9F000000\0" \
 198                                                                         "uboot_name=uboot.bin\0" \
 199                                                                         "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
 200                                                                         "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \
 201                                                                         "uboot_upg=" \
 202                                                                                 "if ping $serverip; then " \
 203                                                                                         "mw.b $loadaddr 0xFF $uboot_backup_size && " \
 204                                                                                         "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \
 205                                                                                         "tftp $loadaddr $uboot_name && " \
 206                                                                                         "if itest.l $filesize <= $uboot_size; then " \
 207                                                                                                 "erase $uboot_addr +$uboot_backup_size && " \
 208                                                                                                 "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \
 209                                                                                                 "echo OK!; " \
 210                                                                                         "else " \
 211                                                                                                 "echo ERROR! Wrong file size!; " \
 212                                                                                         "fi; " \
 213                                                                                 "else " \
 214                                                                                         "echo ERROR! Server not reachable!; " \
 215                                                                                 "fi\0" \
 216                                                                         "firmware_addr=" UPDATE_SCRIPT_FW_ADDR "\0" \
 217                                                                         "firmware_name=firmware.bin\0" \
 218                                                                         "firmware_upg=" \
 219                                                                                 "if ping $serverip; then " \
 220                                                                                         "tftp $loadaddr $firmware_name && " \
 221                                                                                         "erase $firmware_addr +$filesize && " \
 222                                                                                         "cp.b $loadaddr $firmware_addr $filesize && " \
 223                                                                                         "echo OK!; " \
 224                                                                                 "else " \
 225                                                                                         "echo ERROR! Server not reachable!; " \
 226                                                                                 "fi\0" \
 227                                                                         SILENT_ENV_VARIABLE
 228
 229 /* For Merlin, both PCI, PCI-E interfaces are valid */
 230 #define AR7240_ART_PCICFG_OFFSET        12
 231
 232 #define WLANCAL                                         0x9fff1000
 233 #define CFG_MII0_RMII                           1
 234 #define CFG_BOOTM_LEN                           (16 << 20) /* 16 MB */
 235
 236 #undef DEBUG
 237 #define milisecdelay(_x)                        udelay((_x) * 1000)
 238
 239 /* MAC address, model and PIN number offsets in FLASH */
 240 #define OFFSET_MAC_DATA_BLOCK                   0x010000
 241 #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 242 #define OFFSET_MAC_ADDRESS                              0x00FC00
 243 #define OFFSET_ROUTER_MODEL                             0x00FD00
 244 #define OFFSET_PIN_NUMBER                               0x00FE00
 245
 246 #include <cmd_confdefs.h>
 247
 248 #endif  /* __CONFIG_H */