u-boot/include/configs/db12x.h

   1 /*
   2  * This file contains the configuration parameters for the DB12x (AR9344) board.
   3  */
   4
   5 #ifndef __CONFIG_H
   6 #define __CONFIG_H
   7
   8 #include <configs/ar7240.h>
   9 #include <config.h>
  10 #include <soc/soc_common.h>
  11
  12 /*
  13  * GPIO configuration
  14  */
  15 #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1)
  16         /* LEDs */
  17         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO11 | GPIO12 | GPIO13 | GPIO14 | GPIO15)
  18
  19         /* Outputs, inputs */
  20         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO21 | GPIO22)
  21         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO16 | GPIO17)
  22
  23         /* Initial states */
  24         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO21 | GPIO22)
  25
  26 #elif defined(CONFIG_FOR_TPLINK_WDR3500_V1)
  27         /* LEDs */
  28         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO11 | GPIO13 | GPIO14 | GPIO15 | GPIO18 |\
  29                                                                                                          GPIO19 | GPIO20 | GPIO21 | GPIO22)
  30
  31         /* Outputs, inputs */
  32         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO12)
  33         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO16 | GPIO17)
  34
  35         /* Initial states */
  36         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO12)
  37
  38 #elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
  39         /* LEDs */
  40         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO11 | GPIO12 | GPIO13 | GPIO14 | GPIO15 |\
  41                                                                                                          GPIO18 | GPIO19 | GPIO20 | GPIO21)
  42
  43         /* Outputs, inputs */
  44         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO4)
  45         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO16 | GPIO17)
  46
  47         /* Initial states */
  48         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    (CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO | GPIO4)
  49
  50 #elif defined(CONFIG_FOR_TPLINK_WR841N_V8)
  51         /* LEDs */
  52         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO12 | GPIO13 | GPIO14 | GPIO15 | GPIO18 |\
  53                                                                                                          GPIO19 | GPIO20 | GPIO21)
  54
  55         /* Outputs, inputs */
  56         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  57         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO16 | GPIO17)
  58
  59         /* Initial states */
  60         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  61
  62 #elif defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
  63         /* LEDs */
  64         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO13 | GPIO14 | GPIO15 | GPIO18)
  65
  66         /* Outputs, inputs */
  67         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  68         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO16 | GPIO17)
  69
  70         /* Initial states */
  71         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  72
  73 #endif
  74
  75 /*
  76  * FLASH and environment organization
  77  */
  78 #define CFG_MAX_FLASH_BANKS                     1
  79 #define CFG_MAX_FLASH_SECT                      4096    // 4 KB sectors in 16 MB flash
  80 /*
  81  * We boot from this flash
  82  */
  83 #define CFG_FLASH_BASE                                  0x9F000000
  84 #ifdef COMPRESSED_UBOOT
  85         #define BOOTSTRAP_TEXT_BASE                     CFG_FLASH_BASE
  86         #define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE
  87 #endif
  88
  89 /*
  90  * The following #defines are needed to get flash environment right
  91  */
  92 #define CFG_MONITOR_BASE        TEXT_BASE
  93 #define CFG_MONITOR_LEN         (192 << 10)
  94
  95 /*
  96  * Default bootargs
  97  */
  98 #undef CONFIG_BOOTARGS
  99 #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) || defined (CONFIG_FOR_TPLINK_WDR3500_V1)
 100 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)"
 101 #else
 102 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 103 #endif
 104
 105 /*
 106  * Other env default values
 107  */
 108 #undef CONFIG_BOOTFILE
 109 #define CONFIG_BOOTFILE         "firmware.bin"
 110
 111 #undef CONFIG_LOADADDR
 112 #define CONFIG_LOADADDR         0x80800000
 113
 114 #define CFG_LOAD_ADDR                    0x9F020000
 115 #define UPDATE_SCRIPT_FW_ADDR   "0x9F020000"
 116 #define CONFIG_BOOTCOMMAND              "bootm 0x9F020000"
 117
 118
 119 #define CONFIG_IPADDR           192.168.1.1
 120 #define CONFIG_SERVERIP         192.168.1.2
 121
 122 /*
 123  * PLL/Clocks configuration
 124  */
 125 #ifdef CFG_HZ
 126         #undef  CFG_HZ
 127 #endif
 128 #define CFG_HZ  bd->bi_cfg_hz
 129
 130 /* For now, use some safe clocks for all AR934x */
 131 #define CONFIG_QCA_PLL          QCA_PLL_PRESET_550_400_200
 132
 133
 134 /*
 135  * For PLL/clocks recovery use reset button by default
 136  */
 137 #ifdef CONFIG_GPIO_RESET_BTN
 138         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN         CONFIG_GPIO_RESET_BTN
 139 #endif
 140
 141 #ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW
 142         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW      1
 143 #endif
 144
 145 /*
 146  * MIPS32 24K Processor Core Family Software User's Manual
 147  *
 148  * 6.2.9 Count Register (CP0 Register 9, Select 0)
 149  * The Count register acts as a timer, incrementing at a constant
 150  * rate, whether or not an instruction is executed, retired, or
 151  * any forward progress is made through the pipeline.  The counter
 152  * increments every other clock, if the DC bit in the Cause register
 153  * is 0.
 154  *
 155  * Since the count is incremented every other tick, divide by 2
 156  * XXX derive this from CFG_PLL_FREQ
 157  */
 158
 159 /*
 160  * Cache lock for stack
 161  */
 162 #define CFG_INIT_SP_OFFSET                      0x1000
 163 #define CONFIG_INIT_SRAM_SP_OFFSET      0xbd007000
 164
 165 /*
 166  * Address and size of Primary Environment Sector
 167  */
 168 #define CFG_ENV_IS_IN_FLASH     1
 169 #undef  CFG_ENV_IS_NOWHERE
 170
 171 #define CFG_ENV_ADDR            0x9F01EC00
 172 #define CFG_ENV_SIZE            0x1000
 173 #define CFG_ENV_SECT_SIZE       0x10000
 174
 175 /*
 176  * Available commands
 177  */
 178 #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 179                                                  CFG_CMD_DHCP   | \
 180                                                  CFG_CMD_PING   | \
 181                                                  CFG_CMD_FLASH  | \
 182                                                  CFG_CMD_NET    | \
 183                                                  CFG_CMD_RUN    | \
 184                                                  CFG_CMD_DATE   | \
 185                                                  CFG_CMD_SNTP   | \
 186                                                  CFG_CMD_ECHO   | \
 187                                                  CFG_CMD_BOOTD  | \
 188                                                  CFG_CMD_ITEST  | \
 189                                                  CFG_CMD_ENV    | \
 190                                                  CFG_CMD_LOADB)
 191
 192 // Enable NetConsole and custom NetConsole port
 193 #define CONFIG_NETCONSOLE
 194 #define CONFIG_NETCONSOLE_PORT  6666
 195
 196 #define CONFIG_NET_MULTI
 197
 198 #ifdef CFG_ATHRS27_PHY
 199         /* use eth1(LAN) as the net interface */
 200         #define CONFIG_AG7240_SPEPHY
 201 #endif
 202
 203 #define CONFIG_PCI 1
 204
 205 /*
 206  * Web Failsafe configuration
 207  */
 208 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS                          CONFIG_LOADADDR
 209 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS                        CFG_FLASH_BASE
 210
 211 // Firmware partition offset
 212 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS                       WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
 213
 214 // U-Boot partition size
 215 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES          (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
 216
 217 // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
 218 #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x1EC00"
 219 #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        "0x20000"
 220
 221 // ART partition size
 222 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES            (64 * 1024)
 223
 224 // max. firmware size <= (FLASH_SIZE -  WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
 225 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
 226 #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 227
 228 // progress state info
 229 #define WEBFAILSAFE_PROGRESS_START                              0
 230 #define WEBFAILSAFE_PROGRESS_TIMEOUT                    1
 231 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY               2
 232 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY              3
 233 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED             4
 234
 235 // update type
 236 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE               0
 237 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT                  1
 238 #define WEBFAILSAFE_UPGRADE_TYPE_ART                    2
 239
 240 /*-----------------------------------------------------------------------*/
 241
 242 /*
 243  * Additional environment variables for simple upgrades
 244  */
 245 #define CONFIG_EXTRA_ENV_SETTINGS       "uboot_addr=0x9F000000\0" \
 246                                                                         "uboot_name=uboot.bin\0" \
 247                                                                         "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
 248                                                                         "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \
 249                                                                         "uboot_upg=" \
 250                                                                                 "if ping $serverip; then " \
 251                                                                                         "mw.b $loadaddr 0xFF $uboot_backup_size && " \
 252                                                                                         "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \
 253                                                                                         "tftp $loadaddr $uboot_name && " \
 254                                                                                         "if itest.l $filesize <= $uboot_size; then " \
 255                                                                                                 "erase $uboot_addr +$uboot_backup_size && " \
 256                                                                                                 "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \
 257                                                                                                 "echo OK!; " \
 258                                                                                         "else " \
 259                                                                                                 "echo ERROR! Wrong file size!; " \
 260                                                                                         "fi; " \
 261                                                                                 "else " \
 262                                                                                         "echo ERROR! Server not reachable!; " \
 263                                                                                 "fi\0" \
 264                                                                         "firmware_addr=" UPDATE_SCRIPT_FW_ADDR "\0" \
 265                                                                         "firmware_name=firmware.bin\0" \
 266                                                                         "firmware_upg=" \
 267                                                                                 "if ping $serverip; then " \
 268                                                                                         "tftp $loadaddr $firmware_name && " \
 269                                                                                         "erase $firmware_addr +$filesize && " \
 270                                                                                         "cp.b $loadaddr $firmware_addr $filesize && " \
 271                                                                                         "echo OK!; " \
 272                                                                                 "else " \
 273                                                                                         "echo ERROR! Server not reachable!; " \
 274                                                                                 "fi\0" \
 275                                                                         SILENT_ENV_VARIABLE
 276
 277 #define CFG_MII0_RMII                           1
 278 #define CFG_BOOTM_LEN                           (16 << 20) /* 16 MB */
 279
 280 #undef DEBUG
 281
 282 /* MAC address, model and PIN number offsets in FLASH */
 283 #define OFFSET_MAC_DATA_BLOCK                   0x010000
 284 #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 285 #define OFFSET_MAC_ADDRESS                              0x00FC00
 286 #define OFFSET_ROUTER_MODEL                             0x00FD00
 287 #define OFFSET_PIN_NUMBER                               0x00FE00
 288
 289 /*
 290  * PLL and clocks configurations from FLASH
 291  */
 292 #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) || \
 293         defined(CONFIG_FOR_TPLINK_WDR3500_V1)         || \
 294         defined(CONFIG_FOR_TPLINK_MR3420_V2)          || \
 295         defined(CONFIG_FOR_TPLINK_WR841N_V8)          || \
 296         defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2)
 297         /*
 298          * All TP-Link routers have a lot of unused space
 299          * in FLASH, in second 64 KiB block.
 300          * We will store there PLL and CLOCK
 301          * registers configuration.
 302          */
 303         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00010000
 304         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 305
 306 #endif
 307
 308 #if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
 309         /* Use last 32 bytes */
 310         #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET    (CFG_FLASH_BASE + \
 311                                                                                                          CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
 312                                                                                                          0x0000FFE0)
 313 #endif
 314
 315 #include <cmd_confdefs.h>
 316
 317 #endif  /* __CONFIG_H */